A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs

A compact, physical, short-channel threshold voltage model for undoped symmetric double-gate MOSFETs has been derived based on an analytical solution of the two-dimensional (2-D) Poisson equation with the mobile charge term included. The new model is verified by published numerical simulations with close agreement. Applying the newly developed model, threshold voltage sensitivities to channel length, channel thickness, and gate oxide thickness have been comprehensively investigated. For practical device designs the channel length causes 30-50% more threshold voltage variation than does the channel thickness for the same process tolerance, while the gate oxide thickness causes the least, relatively insignificant threshold voltage variation. Model predictions indicate that individual DG MOSFETs with good turn-off behavior are feasible at 10 nm scale; however, practical exploitation of these devices toward gigascale integrated systems requires development of novel technologies for significant improvement in process control.     

Electric potential and threshold voltage models for double-gate Schottky-barrier source/drain MOSFETs

The threshold voltage, V_th of a double-gate (DG) Schottky-barrier (SB) source/drain (S/D) metal-oxide-semiconductor field-effect transistor (MOSFET) has been investigated. An analytic expression for surface potential is obtained by using Gauss's law and solving Poisson's equation, the results of which are compared with simulations, and good agreement is observed. Based on the potential model, a new definition for V_th is developed, and an analytic expression for V_th is obtained, including quantum mechanical effects and SB lowering effect. We find that V_th is very sensitive to the silicon body thickness, t_si. For a device with a small t_si (<3 nm), V_th increases dramatically with the reduction of t_si. V_th decreases with the increase of the back-gate oxide thickness, and with the increasing of the drain bias. All the results can be of great help to the ultra-large scale integrated-circuit (ULSI) designers.     

Process/physics-based threshold voltage model for nano-scaled double-gate devices

Compact physics/process-based model for threshold voltage in double-gate devices is presented. Predominant short-channel effects for double-gate devices, which are drain-induced barrier lowering (DIBL) and short-channel-induced barrier lowering (SCIBL), are physically analysed and modeled to be applicable to SPICE-compatible circuit simulators. The short-channel models are also developed for bulk-Si device and compared to those of double-gate devices. The validity and predictability of the models are demonstrated and confirmed by numerical device simulation results for extremely scaled L _eff = 25?nm double-gate devices and bulk-Si device.     

Modeling of subthreshold characteristics for undoped and doped deep nanoscale short channel double-gate MOSFETs

A model of subthreshold characteristics for both undoped and doped double-gate (DG) MOSFETs has been proposed. The models were developed based on solution of 2-D Poisson's equation using variable separation technique. Without any fitting parameters, our proposed models can exactly reflect the degraded subthreshold characteristics due to nanoscale channel length. Also, design parameters such as body thickness, gate oxide thickness and body doping concentrations can be directly reflected from our models. The models have been verified by comparing with device simulations' results and found very good agreement.     

Analytical threshold voltage model for short channeln+-p+ double-gate SOI MOSFETs

Solving a two-dimensional (2-D) Poisson equation in the channel region, we have developed models for short channel n⁺-p⁺ double-gate SOI MOSFETs, and showed how to design a device with a decreased gate length, suppressing short channel threshold voltage shift ΔVth and subthreshold swing (S-swing) degradation. According to our model, we can design a 0.05 μm L_G device of which threshold voltage is 0.2 V, ΔVth is 25 mV, and S-swing is 65 mV/decade with a 3-nm-thick gate oxide and 12-nm-thick SOI     

Design and simulation of nanoscale double-gate TFET/tunnel CNTFET

A double-gate tunnel field-effect transistor (DG tunnel FET) has been designed and investigated for various channel materials such as silicon (Si),gallium arsenide (GaAs),alminium gallium arsenide (AlxGa1xAs) and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator.The proposed devices are compared on the basis of inverse subthreshold slope (SS),ION/IoFF current ratio and leakage current.Using Si as the channel material limits the property to reduce leakage current with scaling of channel,whereas the AlxGalxAs based DG tunnel FET provides a better ION/IoFF current ratio (2.51 × 106) as compared to other devices keeping the leakage current within permissible limits.The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down.The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time,which makes it suitable for memory based circuits.     

Quantum mechanical analytical modeling of nanoscale DG FinFET: evaluation of potential,threshold voltage and source/drain resistance

Two-dimensional (2D) quantum mechanical analytical modeling has been presented in order to evaluate the 2D potential profile within the active area of FinFET structure. Various potential profiles such as surface, back to front gate and source to drain potential have been presented in order to appreciate the usefulness of the device for circuit simulation purposes. As we move from source end of the gate to the drain end of the gate, there is substantial increase in the potential at any point in the channel. This is attributed to the increased value of longitudinal electric field at the drain end on application of a drain to source voltage. Further, in this paper, the detailed study of threshold voltage and its variation with the process parameters are presented. A threshold voltage roll-off with fin thickness is observed for both theoretical and experimental results. The fin thickness is varied from 10 nm to 60 nm. The percentage roll-off for our model is 77% and that for experimental result it is 75%. Form the analysis of source/drain (S/D) resistance, it is observed that for a fixed fin width, as the channel length increases, there is an enhancement in the parasitic S/D resistance. This can be inferred from the fact that as the channel length decreases, quantum confinement along the S/D direction becomes more extensive. For our proposed devices a close match is obtained with the results through the analytical model and reported experimental results, thereby validating our proposed QM analytical model for DG FinFET device.     

A self-aligned, electrically separable double-gate MOS transistor technology for dynamic threshold voltage application

In this brief, a self-aligned electrically separable double-gate (SA ESDG) MOS transistor technology is proposed and demonstrated. The SA ESDG structure is implemented by defining a dummy top gate that is self-aligned to the bottom gate and then later replacing the dummy using a real top gate. The proposed process is applied to the single-grain Si film formed by recrystallizing a low-pressure chemical vapor deposition a-Si with a metal induced unilateral crystallization technique and enhancing the grain sizes in a subsequent high temperature annealing step. The ideal device structure resulting from the process is verified by scanning electron microscope imaging. The good current-voltage characteristics and the noticeable dynamic threshold voltage effects are also observed in the implemented SA ESDG device.     

Analytical solution of fundamental surface potential equations for symmetric double-gate metal-oxide-semiconductor field-effect transistors

Both the fundamental surface potential equations for undoped and doped symmetric double-gate MOSFETs are transcendental equations with exponentials, to which a general analytical solution is introduced. Given the lowest potential in the channel film, this solution can calculate the surface potentials of both undoped and doped symmetric double-gate MOSFETs accurately. This analytical approach could also be applied to solve other similar device equations with exponential transcendent structures.     

An analytic model for channel potential and subthreshold swing of the symmetric and asymmetric double-gate MOSFETs

An analytical model for channel potential and subthreshold swing of the symmetric and asymmetric double-gate Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is presented. Two-dimensional Poisson equation is solved analytically using series method and channel potential is obtained. The analytical expression for subthreshold swing is achieved. Model results are compared with Medici simulation results, both of them turn out to agree very well. The results show the variation of channel potential and subthreshold swing with channel length, gate bias, and oxide thickness, which will provide some guidance for the integrated circuit designs.     

Process-variation- and random-dopants-induced threshold voltage fluctuations in nanoscale CMOS and SOI devices

In this paper, we investigate the threshold voltage fluctuation for nanoscale metal-oxide-semiconductor field effect transistor (MOSFET) and silicon-on-insulator (SOI) devices. The threshold voltage fluctuation comes from random dopant and short channel effects. The random-dopant-induced fluctuation is due to the random nature of ion implantation. The gate-length deviation and the line-edge roughness are mainly resulted from the short-channel effect. For the SOI devices, we should also consider the body thickness variation. In our investigation, the metal gate with high-κ material MOSFET is a good choice to reduce fluctuation of threshold voltage when comparing to the poly gate MOSFET and thin-body SOI devices.     

对称双栅多晶硅薄膜晶体管的沟道电势显式求解和漏电流模型

A physical and explicit surface potential model for undoped symmetric double-gate polysilicon thinfilm transistors has been derived based on an effective charge density approach of Poisson＇s equation with both exponential deep and tail state terms included. The proposed surface potential calculation is single-piece and eliminatestheregionalapproach.Modelpredictionsarecomparedtonumericalsimulationswithcloseagreement,having absolute error in the millivolt range. Furthermore, expressions of the drain current are given for a wide range of operation regions, which have been justified by thorough comparisons with experimental data.     

Modeling of ultrathin double-gate nMOS/SOI transistors

An analytical model valid near and below threshold is derived for double-gate nMOS/SOI devices. The model is based on Poisson's equation, containing both the doping impurity charges and the electron concentration. An original assumption of the constant difference between surface and mid-film potentials is successfully introduced. The model provides explicit expressions of the threshold voltage and threshold surface potential, which may no longer be assumed to be pinned at the limit of strong inversion, and demonstrates the nearly ideal subthreshold slope of ultrathin double-gate SOI transistors. Very good agreement with numerical simulations is observed. Throughout the paper we give an insight into weak inversion mechanisms occurring in thin double-gate structures     

Modeling the anomalous threshold voltage behavior of submicrometerMOSFET's

A simple yet accurate semi-empirical analytical model for simulating the anomalous threshold voltage behavior in submicrometer MOSFETs is reported. The increase in the threshold voltage with decreasing channel length has been modeled by assuming a bias-independent, but channel-length-dependent, fixed charge at the source and drain ends. The new model requires two extra parameters in addition to the usual short-channel threshold voltage model parameters. These two parameters represent the magnitude of the fixed charge and the length over which the charge is spread at the source and drain ends. The model shows excellent agreement with the experimental threshold voltage data (within 2%) for submicrometer devices with varying oxide thickness, junction depth, and channel doping concentration     

Modeling of threshold voltage of a quadruple gate transistor

In this paper, a three dimensional analytical solution of electrostatic potential is presented for undoped (or lightly doped) quadruple gate MOSFET by solving 3-D Poisson's equation. It is shown that the threshold voltage predicted by the analytical solution is in close agreement with TCAD 3-D numerical simulation results. For numerical simulation, self-consistent Schrodinger-Poisson equations, calibrated by 2D non equilibrium green function simulation, are used. This analytical model not only provides useful physics insight of effects of gate length and body width on the threshold voltage, but also serves as a basis for compact modeling of quadruple gate MOSFETs.     

Multi-bias capacitance voltage characteristic of AlGaN/GaN HEMT

The method of multi-bias capacitance voltage measurement is presented. The physical meaning of gate-source and gate-drain capacitances in AlGaN/GaN HEMT and the variations in them with different bias con-ditions are discussed. A capacitance model is proposed to reflect the behaviors of the gate-source and gate-drain ca-pacitances, which shows a good agreement with the measured capacitances, and the power performance obtains good results compared with the measured data from the capacitance model.     

A simple analytical threshold voltage model of nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFETs

For the first time, a simple and accurate analytical model for the threshold voltage of nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFETs is developed by solving the two-dimensional (2-D) Poisson equation. In the proposed model, the authors have considered several important parameters: 1) the effect of strain (in terms of equivalent Ge mole fraction); 2) short-channel effects; 3) strained-silicon thin-film doping; 4) strained-silicon thin-film thickness; and 5) gate work function and other device parameters. The accuracy of the proposed analytical model is verified by comparing the model results with the 2-D device simulations. It has been demonstrated that the proposed model correctly predicts a decrease in threshold voltage with increasing strain in the silicon thin film, i.e., with increasing equivalent Ge concentration. The proposed compact model can be easily implemented in a circuit simulator.     

多层浮栅FET pH传感单元阈值电压敏感模型分析和讨论

Research into new pH sensors fabricated by the standard CMOS process is currently a hot topic. The new pH sensing multi-floating gate field effect transistor is found to have a very large threshold voltage, which is different from the normal ion-sensitive field effect transistor. After analyzing all the interface layers of the structure, a new sensitive model based on the Gauss theorem and the charge neutrality principle is created in this paper. According to the model, the charge trapped on the multi-floating gate during the process and the thickness of the sensitive layer are the main causes of the large threshold voltage. From this model, it is also found that removing the charge on the multi-floating gate is an effective way to decrease the threshold voltage. The test results for three different standard pH buffer solutions show the correctness of the model and point the way to solve the large threshold problem.     

Modeling and discussion of threshold voltage for a multi-floating gate FET pH sensor

Research into new pH sensors fabricated by the standard CMOS process is currently a hot topic. The new pH sensing multi-floating gate field effect transistor is found to have a very large threshold voltage, which is different from the normal ion-sensitive field effect transistor. After analyzing all the interface layers of the structure, a new sensitive model based on the Gauss theorem and the charge neutrality principle is created in this paper. According to the model, the charge trapped on the multi-floating gate during the process and the thickness of the sensitive layer are the main causes of the large threshold voltage. From this model, it is also found that removing the charge on the multi-floating gate is an effective way to decrease the threshold voltage. The test results for three different standard pH buffer solutions show the correctness of the model and point the way to solve the large threshold problem.     

Input voltage sensitivity of GaAs/GaAlAs HEMT latched comparator

The input voltage sensitivity represents a critical parameter for a latched comparator in high-speed and high-precision data conversion applications. An analytical prediction of this parameter is presented and has been verified to be in good agreement with the experimental results from a high performance latched comparator implemented in 0.5 mu m GaAs/GaAlAs E/D HEMT technology.<>