Implementation of perfect-magnetic-coupling ultralow-loss transformer in RFCMOS technology

In this letter, we propose a single-turn multiple-layer interlaced stacked transformer structure with nearly perfect magnetic-coupling factor (k/sub IM//spl sim/1) using standard mixed-signal/RF CMOS (or BiCMOS) technology. A single-turn six-layer interlaced stacked transformer was implemented to demonstrate the proposed structure. Temperature dependence (from -25/spl deg/C to 175/spl deg/C) of the quality-factor (Q-factor), k/sub Im/, resistive-coupling factor (k/sub Re/), maximum available power gain (G/sub Amax/), and minimum noise figure (NF/sub min/) performances of the transformer are reported. State-of-the-art G/sub Amax/ of 0.762 and 0.904 (i.e., NF/sub min/ of 1.181 dB and 0.437 dB) have been achieved at 5.2 and 8 GHz, respectively, at room temperature, mainly due to the perfect magnetic-coupling factor and the high resistive-coupling factor. The present analysis is helpful for RF engineers to design ultralow-voltage high-performance transformer-feedback low-noise amplifiers and voltage-controlled oscillators, and other radio frequency integrated circuits which include transformers.     

Temperature and Substrate Effects in Monolithic RF Inductors on Silicon With 6-$muhboxm$-Thick Top Metal for RFIC Applications

Comprehensive analyses of the effects of temperature (from$-hbox50 ^circhboxC$to 200$^circhboxC$), silicon substrate thickness, and proton implantation postprocess on the performances of a set of planar spiral inductors with 6-$muhboxm$-thick top metal are demonstrated. Quality-factor (Q-factor) and power gain$( G_ A)$decrease with increasing temperatures but show a reverse behavior within a higher frequency range. Stability-factor (K-factor) and noise figure (NF) increase with increasing temperatures but show a reverse behavior within a higher frequency range. The reverse frequencies$f_R$, which correspond to the zero temperature coefficient of$G_A$, K-factor, and NF, are almost the same. In addition, both the silicon substrate thinning and proton implantation are verified to be effective in improving the Q-factor and NF performances of inductors on silicon. The present analyses enable RF engineers to understand more deeply the Q-factor and NF behavior of inductors fabricated on a thin silicon substrate (20$muhboxm$) and hence are helpful for them to design high-performance fully on-chip low-noise-amplifiers and other RF integrated circuits.     

An ultralow-loss and broadband micromachined RF inductor for RFIC input-matching applications

In this brief, we demonstrate that ultralow-loss and broadband inductors can be obtained by using the CMOS process compatible backside inductively coupled-plasma (ICP) deep-trench technology to selectively remove the silicon underneath the inductors. The results show that a 378.5% increase in maximum Q-factor (Q/sub max/) (from 10.7 at 4.7 GHz to 51.2 at 14.9 GHz), a 22.1% increase in self-resonant frequency (f/sub SR/) (from 16.5 to 20.15 GHz), a 16.3% increase (from 0.86 to 0.9999) in maximum available power gain (G/sub Amax/) at 5 GHz, and a 0.654-dB reduction (from 0.654 dB to 4.08/spl times/10/sup -4/ dB) in minimum noise figure (NF/sub min/) at 5 GHz were achieved for a 2-nH inductor after the backside ICP dry etching. In addition, state-of-the-art ultralow-loss G/sub Amax//spl les/0.99 (i.e., NF/sub min//spl les/0.045 dB) for frequencies lower than 12.5 GHz was achieved for this 2-nH inductor after the backside inductively coupled-plasma dry etching. This means this on-chip inductor-on-air can be used to realize an ultralow-noise 3.1-10.6 GHz ultrawide-band RFIC. These results show that the CMOS process compatible backside ICP etching technique is very promising for system-on-a-chip applications.     

Low noise RF MOSFETs on flexible plastic substrates

We report a low minimum noise figure (NF/sub min/) of 1.1 dB and high associated gain (12 dB at 10 GHz) for 16 gate-finger 0.18-/spl mu/m RF MOSFETs, after thinning down the Si substrate to 30 /spl mu/m and mounting it on plastic. The device performance was improved by flexing the substrate to create stress, which produced a 25% enhancement of the saturation drain current and lowered NF/sub min/ to 0.92 dB at 10 GHz. These excellent results for mechanically strained RF MOSFETs on plastic compare well with 0.13-/spl mu/m node (L/sub g/=80 nm) devices.     

Microwave noise characteristics of AlGaN/GaN HEMTs on SiC substrates for broad-band low-noise amplifiers

This letter reports high-performance passivated AlGaN/GaN high electron-mobility transistors (HEMTs) with 0.25-/spl mu/m gate-length for low noise applications. The devices exhibited a minimum noise figure (NF/sub min/) of 0.98 dB and an associated gain (G/sub a/) of 8.97 dB at 18 GHz. The noise resistance (R/sub n/), the measure of noise sensitivity to source mismatch, is 31/spl Omega/ at 18 GHz, which is relatively low and suitable for broad-band low noise amplifiers. The noise modeling analysis shows that the minimum noise figure of the GaN HEMT can be reduced further by reducing noise contributions from parasitics. These results demonstrate the viability of AlGaN/GaN HEMTs for low-noise as well as high power amplifiers.     

CMOS-compatible surface-micromachined suspended-spiral inductors for multi-GHz silicon RF ICs

Fully CMOS-compatible, highly suspended spiral inductors have been designed and fabricated on standard silicon substrates (1/spl sim/30 /spl Omega//spl middot/cm in resistivity) by surface micromachining technology (no substrate etch involved). The RF characteristics of the fabricated inductors have been measured and their equivalent circuit parameters have been extracted using a conventional lumped-element model. We have achieved a high peak Q-factor of 70 at 6 GHz with inductance of 1.38 nH (at 1 GHz) and a self-resonant frequency of over 20 GHz. To the best of our knowledge, this is the highest Q-factor ever reported on standard silicon substrates. This work has demonstrated that the proposed microelectromechanical systems (MEMS) inductors can be a viable technology option to meet the today's strong demands on high-Q on-chip inductors for multi-GHz silicon RF ICs.     

A new lossy substrate de-embedding method for sub-100 nm RF CMOS noise extraction and modeling

A new equivalent circuit method is proposed in this paper to de-embed the lossy substrate and lossy pads' parasitics from the measured RF noise of multifinger MOSFETs with aggressive gate length scaling down to 80 nm. A new RLC network model is subsequently developed to simulate the lossy substrate and lossy pad effect. Good agreement has been realized between the measurement and simulation in terms of S-parameters and four noise parameters, NF/sub min/ (minimum noise figure), R/sub n/ (noise resistance), Re(Y/sub sopt/), and Im(Y/sub sopt/) for the sub-100-nm RF nMOS devices. The intrinsic NF/sub min/ extracted by the new de-embedding method reveal that NF/sub min/ at 10 GHz can be suppressed to below 0.8 dB for the 80-nm nMOS attributed to the advancement of f/sub T/ to 100-GHz level and the effectively reduced gate resistance by multifinger structure.     

DC, RF, and microwave noise performances of AlGaN/GaN HEMTs on sapphire substrates

High-performance AlGaN/GaN high electron-mobility transistors with 0.18-/spl mu/m gate length have been fabricated on a sapphire substrate. The devices exhibited an extrinsic transconductance of 212 mS/mm, a unity current gain cutoff frequency (f/sub T/) of 101 GHz, and a maximum oscillation frequency (f/sub MAX/) of 140 GHz. At V/sub ds/=4 V and I/sub ds/=39.4 mA/mm, the devices exhibited a minimum noise figure (NF/sub min/) of 0.48 dB and an associated gain (Ga) of 11.16 dB at 12 GHz. Also, at a fixed drain bias of 4 V with the drain current swept, the lowest NFmin of 0.48 dB at 12 GHz was obtained at I/sub ds/=40 mA/mm, and a peak G/sub a/ of 11.71 dB at 12 GHz was obtained at I/sub ds/=60 mA/mm. With the drain current held at 40 mA/mm and drain bias swept, the NF/sub min/,, increased almost linearly with the increase of drain bias. Meanwhile, the Ga values decreased linearly with the increase of drain bias. At a fixed bias condition (V/sub ds/=4 V and I/sub ds/=40 mA/mm), the NF/sub min/ values at 12 GHz increased from 0.32 dB at -55/spl deg/C to 2.78 dB at 200/spl deg/C. To our knowledge, these data represent the highest f/sub T/ and f/sub MAX/, and the best microwave noise performance of any GaN-based FETs on sapphire substrates ever reported.     

A high quality factor and low power loss micromachined RF bifilar transformer for UWB RFIC applications

In this letter, the authors demonstrate that high quality factor and low power loss transformers can be obtained by using the CMOS process-compatible backside inductively coupled plasma (ICP) deep-trench technology to selectively remove the silicon underneath the transformers. A 62.4% (from 8.99 to 14.6) and a 205.8% (from 8.6 to 26.3) increase in the Q-factor, a 10.3% (from 0.697 to 0.769) and a 30.2% (from 0.652 to 0.849) increase in the maximum available power gain (G/sub Amax/), and a 0.43- (from 1.57 to 1.14 dB) and a 1.15-dB (from 1.86 to 0.71 dB) reduction in the minimum noise figure (NF/sub min/) were achieved at 5.2 and 10 GHz, respectively, for a bifilar transformer with overall dimension of 240/spl times/240 /spl mu/m/sup 2/ after the backside ICP etching. The values of G/sub Amax/ of 0.769 and 0.849 are both state-of-the-art results among all reported on-chip bifilar transformers. These results indicate that the backside ICP deep-trench technology is very promising for high-performance radio frequency integrated circuit applications.     

Very low noise RF nMOSFETs on plastic by substrate thinning and wafer transfer

A very low minimum noise figure (NF/sub min/) of 1.2 dB and a high associated gain of 12.8 dB at 10 GHz were measured for six-finger, 0.18-/spl mu/m radio frequency (RF) metal-oxide semiconductor field-effect transistors mounted on insulating plastic following substrate-thinning (/spl sim/30 /spl mu/m) and wafer transfer. Before this process, the devices had a slightly better RF performance of 1.1-dB NF/sub min/ and a 13.7-dB associated gain. The small RF performance degradation of the active transistors transferred to plastic shows the potential of integrating electronics onto plastic.     

High microwave and noise performance of 0.17-/spl mu/m AlGaN-GaN HEMTs on high-resistivity silicon substrates

AlGaN-GaN high-electron mobility transistors (HEMTs) based on high-resistivity silicon substrate with a 0.17-/spl mu/m T-shape gate length are fabricated. The device exhibits a high drain current density of 550 mA/mm at V/sub GS/=1 V and V/sub DS/=10 V with an intrinsic transconductance (g/sub m/) of 215 mS/mm. A unity current gain cutoff frequency (f/sub t/) of 46 GHz and a maximum oscillation frequency (f/sub max/) of 92 GHz are measured at V/sub DS/=10 V and I/sub DS/=171 mA/mm. The radio-frequency microwave noise performance of the device is obtained at 10 GHz for different drain currents. At V/sub DS/=10 V and I/sub DS/=92 mA/mm, the device exhibits a minimum-noise figure (NF/sub min/) of 1.1 dB and an associated gain (G/sub ass/) of 12 dB. To our knowledge, these results are the best f/sub t/, f/sub max/ and microwave noise performance ever reported on GaN HEMT grown on Silicon substrate.     

High-performance on-chip transformers

To study the substrate effect on transformer performance, several types of spiral transformers were fabricated on p/sup +/ silicon substrate with microporous silicon (PS) regions. Our analysis shows that the use of PS significantly reduces the substrate effects including eddy current and capacitive coupling between spirals and the substrate. The reduced substrate effects lead to higher Q-factor and resonant frequency (f/sub r/), mutual reactive coupling coefficients (k/sub Im/) with larger useable band width and higher available gain (G/sub a/) mainly because of the reduction in power loss to the substrate. The use of PS can greatly increase transformer performances and broaden the parameter space for on-chip transformer layout optimization.     

High-performance inductors on plastic substrate

Wafer-transfer technology (WTT) has been applied to transfer RF inductors from a silicon wafer to an opaque plastic substrate (FR-4). By completely eliminating silicon substrate, the high performance of integrated inductors (Q-factor > 30 for inductance /spl sim/3 nH with resonant frequency /spl sim/23 GHz) has been achieved. Based on the analysis of a modified /spl pi/-network model, our results suggest that the performance limitation is switched from being a synthetic mechanism of substrate and metal-ohmic losses on low resistivity Si-substrate to merely a metal-ohmic loss on FR-4. Thus, the inductor patterns, which are optimized currently for RFICs on silicon wafer, can be further optimized to take full advantage of the WTT on new substrate from the newly obtained design freedom.     

RF HBT oscillators with low-phase noise and high-power performance utilizing a (/spl lambda//4/spl plusmn//spl delta/) open-stubs resonator

This paper presents a new type of transmission-line resonator and its application to RF (microwave and millimeter-wave) heterojunction bipolar transistor (HBT) oscillators. The resonator is a parallel combination of two open stubs having length of /spl lambda//4/spl plusmn//spl delta/(/spl delta//spl Lt//spl lambda/), where /spl lambda/ is a wavelength at a resonant frequency. The most important feature of this resonator is that the coupling coefficient (/spl beta//sub C/) can be controlled by changing /spl delta/ while maintaining unloaded Q-factor (Q/sub u/) constant. Choosing a small value of /spl delta/ allows us to reduce /spl beta//sub C/ or equivalently to increase loaded Q-factor (Q/sub L/). Since coupling elements such as capacitors or electromagnetic gaps are not needed, /spl beta//sub C/ and Q/sub L/ can be precisely controlled based on mature lithography technology. This feature of the resonator proves useful in reducing phase noise and also in enhancing output power of microwave oscillators. The proposed resonator is applied to 18-GHz and 38-GHz HBT oscillators, leading to the phase noise of -96-dBc/Hz at 100-kHz offset with 10.3-dBm output power (18-GHz oscillator) and -104-dBc/Hz at 1-MHz offset with 11.9 dBm (38-GHz oscillator). These performances are comparable to or better than state-of-the-art values for GaAs- or InP-based planar-circuit fundamental-frequency oscillators at the same frequency bands.     

A broadband and scalable model for on-chip inductors incorporating substrate and conductor loss effects

A new T-model has been developed to accurately simulate the broadband characteristics of on-Si-chip spiral inductors, up to 20 GHz. The spiral coil and substrate RLC networks built in the model play a key role responsible for conductor loss and substrate loss in the wideband regime, which cannot be accurately described by the conventional /spl pi/-model. Good match with the measured S-parameters, L(/spl omega/), Re(Z/sub in/(/spl omega/)), and Q(/spl omega/) proves the proposed T-model. Besides the broadband feature, scalability has been justified by good match with a linear function of coil numbers for all model parameters employed in the RLC networks. The satisfactory scalability manifest themselves physical parameters rather than curve fitting. A parameter extraction flow is established through equivalent circuit analysis to enable automatic parameter extraction and optimization. This scalable inductor model will facilitate optimization design of on-chip inductor and the accuracy proven up to 20 GHz can improve RF circuit simulation accuracy demanded by broadband design.     

An analysis of small-signal source-body resistance effect on RF MOSFETs for low-cost system-on-chip (SoC) applications

In this paper, we demonstrate a comprehensive analysis of small-signal source-body resistance (R/sub sb/) effect on the RF performances of RF MOSFETs for low-cost system-on-chip (SoC) applications for the first time. Our results show that for RF MOSFETs, both the kink phenomena of S/sub 11/ and S/sub 22/ become more obscure as reverse body bias (V/sub B/) increases due to the decrease of transconductance (g/sub m/). In addition, an increase of source-body spacing enhances both the kink phenomena of S/sub 11/ and S/sub 22/, but deteriorates the current-gain cut-off frequency (f/sub T/), maximum oscillation frequency (f/sub MAX/), and RF noise and power performances due to the increase of R/sub sb/ of the devices. Analytical formulas are derived to explain the kink phenomena of S/sub 11/ and S/sub 22/, and to explain why increasing R/sub sb/ leads to a reduction of equivalent substrate resistance R/sub sub/, or worse f/sub T/, f/sub MAX/, and RF noise performances of the devices. The present analyzes enable RF engineers to understand the S-parameters, noise parameters, and power performances of RF MOSFETs more deeply, and hence are helpful for them to optimize the layout of MOSFETs and to create a fully scalable RF CMOS model for SoC applications.     

Electrical-stress effects and device modeling of 0.18-/spl mu/m RF MOSFETs

In this paper, a novel microstrip-line layout is used to make accurate measurements of the minimum noise figure (NF/sub min/) of RF MOSFETs. A low NF/sub min/ of 1.05 dB at 10 GHz was directly measured for 16-finger 0.18-/spl mu/m MOSFETs, without de-embedding. Using an analytical expression for NF/sub min/, we have developed a self-consistent dc current-voltage, S-parameter, and NF/sub min/ model, where the simulated results match the measured device characteristics well, both before and after electrical stress.     

SOI technology for radio-frequency integrated-circuit applications

This paper presents a silicon-on-insulator (SOI) integration technology, including structures and processes of OFF-gate power nMOSFETs, conventional lightly doped drain (LDD) nMOSFETs, and spiral inductors for radio frequency integrated circuit (RFIC) applications. In order to improve the performance of these integrated devices, body contact under the source (to suppress floating-body effects) and salicide (to reduce series resistance) techniques were developed for transistors; additionally, locally thickened oxide (to suppress substrate coupling) and ultra-thick aluminum up to 6 /spl mu/m (to reduce spiral resistance) were also implemented for spiral inductors on high-resistivity SOI substrate. All these approaches are fully compatible with the conventional CMOS processes, demonstrating devices with excellent performance in this paper: 0.25-/spl mu/m gate-length offset-gate power nMOSFET with breakdown voltage (BV/sub DS/) /spl sim/ 22.0 V, cutoff frequency (f/sub T/)/spl sim/15.2 GHz, and maximal oscillation frequency (f/sub max/)/spl sim/8.7 GHz; 0.25-/spl mu/m gate-length LDD nMOSFET with saturation current (I/sub DS/)/spl sim/390 /spl mu/A//spl mu/m, saturation transconductance (g/sub m/)/spl sim/197 /spl mu/S//spl mu/m, cutoff frequency /spl sim/ 25.6 GHz, and maximal oscillation frequency /spl sim/ 31.4 GHz; 2/5/9/10-nH inductors with maximal quality factors (Q/sub max/) 16.3/13.1/8.95/8.59 and self-resonance frequencies (f/sub sr/) 17.2/17.7/6.5/5.8 GHz, respectively. These devices are potentially feasible for RFIC applications.     

Broadband microwave noise characteristics of high-linearity composite-channel Al/sub 0.3/Ga/sub 0.7/N/Al/sub 0.05/Ga/sub 0.95/N/GaN HEMTs

We report broadband microwave noise characteristics of a high-linearity composite-channel HEMT (CC-HEMT). Owing to the novel composite-channel design, the CC-HEMT exhibits high gain and high linearity such as an output third-order intercept point (OIP3) of 33.2 dBm at 2 GHz. The CC-HEMT also exhibits excellent microwave noise performance. For 1-/spl mu/m gate-length devices, a minimum noise figure (NF/sub min/) of 0.7 dB and an associated gain (G/sub a/) of 19 dB were observed at 1 GHz, and an (NF/sub mi/) of 3.3 dB and a G/sub a/ of 10.8 dB were observed at 10 GHz. The dependence of the noise characteristics on the physical design parameters, such as the gate-source and gate-drain spacing, is also presented.     

High-performance inductors integrated on porous silicon

To study the substrate effect on inductor performance, several types of spiral inductors were fabricated on porous silicon (PS), p/sup -/ and p/sup +/ silicon substrate. /spl pi/-network analysis results show that the use of PS effectively reduces the shunt conductance and capacitance. The analysis further shows that the use of PS significantly reduces the eddy current portion of series resistance of inductor, leading to slower increase of the apparent series resistance with increasing frequency. Higher Q-factor and resonant frequency (f/sub r/) result from the reduced shunt conductance, shunt capacitance, and frequency dependence of series resistance. Inductors fabricated on PS regions are subjected to a much less stringent set of constraints than those on bulk Si substrate, allowing for much higher inductance to be achieved without severe sacrifice in Q-factor and f/sub r/. Similarly, much higher Q-factor can be obtained for reasonable inductance and f/sub r/.