无线电罗盘导航基准算法研究

测试基准是机载电子设备试飞中性能考核的依据。以无线电罗盘为例，首先介绍了无线电罗盘导航系统的构成及作用，其次从原理上对无线电罗盘的测试基准提取方法进行阐述， 明确不同象限下方位计算的差异化。通过该算法的研究，举一反三，掌握无线电导航方位基准数据的提取方法。     

天线反射面胎膜测量坐标系的软件调整

对于双弯曲面、只有在加工基准与测量基准重合时，测量精度才最高。如果加工精度要求较高，那么工件尺寸较大时基准校准就比较困难，测量误差甚至大于工件的实际加工误差，利用计算机对测得的数据进行处理，可较好地解决这一问题。     

WARPDS基准站数据传输体制的设计与分析

WARPDS 系统可以极大的满足高精度用户的需求，其基准站观测数据的及时上报直接决定了 WARPDS 系统服务的实时性和完好性，由于 WARPDS 系统基准站数据的上报采用地面网络的方式，因此合理的网络架构对于保证数据上报时延满足 WARPDS 系统的延迟指标精度有着决定性的意义。通过对基准站布局特性的分析，设计了基于国防主干网的组网架构，对京-沈哈干线的网络传输时延进行了理论分析和实际测试，并推广到该系统中传输距离最远的喀什站， 结果表明设计的网络架构能够满足 WARPDS 系统上报数据延迟的指标要求。     

网络化靶场综合模拟试验网时间统一系统研究

为了在靶场网络化测试模拟试验网中统一多台测试设备的本地时间,以便组织网络化多台设备组网综合数据融合模拟试验,需要设计时统专用标定设备。在分析了几种常用授时方式的基础上,提出了采用单脉冲硬件驱动定标机制来统一标定各测试设备的本地时间。此硬件设备以微控制器为控制核心,通过统一启动时间基准标定信号,来对各测试设备的主机本地时间进行统一标定。在试验中,数据融合系统能够在新的统一时间基准下工作,融合后的数据具有实时驱动其他测试设备的能力。试验结果表明此时间基准设备能够达到系统测试功能要求,可用作在靶场网络化综合测试模拟试验中对多台测试设备组网的时间的统一标定。     

低功耗高精度基准源研究综述

本文介绍了基准源电路的发展脉络及研究进展.按照电路功能进行分类,基准源可以分为基准电压源和基准电流源.对于基准电压源,分别对于带隙基准源、混合基准源和CMOS基准源三个类别的发展历程及最新研究成果进行了总结和讨论;分析了这些电路在降低功耗、提高精度方面的创新之处、优点和存在的问题.对于基准电流源,主要讨论了电流直接补偿以及由电压源得到电流源两种设计方法.基于以上讨论,对于基准源未来的发展前景进行了展望.     

大数据环境下准确验证计算模型效率的方法

随着开源大数据技术的快速发展,许多新的大数据技术的得到商用,大数据计算模型更是发展迅速。传统认为,大数据具有3V特性,即Volume(海量)、Velocity(高速)和Variety(多样),同时大数据还面临Value(价值)和Veracity(精确)的挑战。如何客观地比较不同数据计算模型效率,即大数据测试基准的选择,成为一个重要的研究课题。事务性能管理委员会(TPC)是目前最知名的数据管理系统评测基准标准化组织他们发布的多款基准测试案例,在业内具有很高的认可度。Apache开源社区针对大数据架构也发布了多款性能测试用例,如Test DFSIO、Tera Sort。为了提出一种准确验证大数据计算模型效率的方法,本文将在分析总结现有成果的基础上,进一步对比现有的大数据测试基准,然后重点讨论TPC-DS测试基准和Big Bench测试。本文提出的方法,能够准确的验证大数据计算模型效率。     

MPEG家族的新成员——MPEG-7

在日常生活中，无论是军用还是民用领域，每天都可能产生海量的图像／视频数据，这些图像／视频数据中含有大量的信息。但是，如果我们不能合理地组织这些图像／视频数据，要想有效地浏览、检索这些信息     

一种以音频为基准的视频捕获丢帧补偿算法的研究

针对视音频捕获回放过程中视频超前、音频滞后的现象，提出了一种以音频为基准的视频捕获丢帧补偿算法，其利用稳定的音频数据作为同步基准，在视频帧数据写入流媒体文件时进行丢帧补偿处理，从而保证视音频捕获的同步。本算法已在西安交通大学网络教育示范系统中得到了应用。应用表明，本算法较好地解决了视音频捕获同步问题。     

广州连续运行卫星定位服务系统通过验收

日前，广州市连续运行卫星定位服务系统通过国家测绘局组织的专家验收。专家一致认为该项目建设质量达到了国内一流水平，该系统使用后，广州市将实现从传统静态测绘基准向现代动态测绘基准的提升。     

精密电压基准

查询号：１８７ 数据转换系统的设计之所以是一 个难题，原因之一是系统精度很大程度上依赖于内部或外部ＤＣ电压基准所建立的电压精度。电压基准用来产生一个精确的输出电压，以此为数据转换系统设计满量程输入。在模／数转换器（ＡＤＣ）中，ＤＣ电压基准与模拟输入信号一起用于产生数字化的输出信号。在数／模转换器（ＤＡＣ）中，ＤＡＣ根据呈现在ＤＡＣ输入端上的数字输入信号，从ＤＣ基准电压选择和产生模拟输出。在工作温度范围内基准电压的任何误差将影响ＡＤＣ／ＤＡＣ的线性度和无寄生动态范围（ＳＦＤＲ）。实际上所有电压基准随…     

基于ARM7TDMI的cache控制器电路

针对ARM7TDMI内核的特点,提出了一种高速缓存(cache)控制器的电路实现方案.主要应用Verilog硬件描述语言对cache控制器进行了行为级描述,通过了前端仿真和综合后的联合仿真,比较了嵌入式系统中有无cache的工作效率,并给出了实验结果.实验结果表明,系统中加入cache电路以后存储性能会有显著提高.     

MCM routing algorithm based on a compatibility graph approach

A new algorithm for general area multichip module routing using a multi-candidate and compatibility graph approach, which maximises routing density while minimising vias and total wire length, is presented. Experimental results using standard industrial benchmarks show improved results relative to a commercial router and other previously proposed routers while offering flexibility for future incorporation of noise and delay constraints     

A cut-based method for terminal-pair reliability

This paper assesses two categories of partition techniques for computing terminal-pair reliability (path-based and cut-based algorithms) by experimenting on published benchmarks; the criteria are the number of subproblems and the computation time. The cut-based algorithm is superior to the path-based algorithm with respect to the computation time for most benchmarks. A refinement of the cut-based algorithm (using network reduction) profoundly outperforms the path-based algorithm (with reduction) for all benchmarks     

Comparing open data benchmarks: Which metrics and methodologies determine countries’ positions in the ranking lists?

An understanding of the similar and divergent metrics and methodologies underlying open government data benchmarks can reduce the risks of the potential misinterpretation and misuse of benchmarking outcomes by policymakers, politicians, and researchers. Hence, this study aims to compare the metrics and methodologies used to measure, benchmark, and rank governments' progress in open government data initiatives. Using a critical meta-analysis approach, we compare nine benchmarks with reference to meta-data, meta-methods, and meta-theories. This study finds that both existing open government data benchmarks and academic open data progress models use a great variety of metrics and methodologies, although open data impact is not usually measured. While several benchmarks’ methods have changed over time, and variables measured have been adjusted, we did not identify a similar pattern for academic open data progress models. This study contributes to open data research in three ways: 1) it reveals the strengths and weaknesses of existing open government data benchmarks and academic open data progress models; 2) it reveals that the selected open data benchmarks employ relatively similar measures as the theoretical open data progress models; and 3) it provides an updated overview of the different approaches used to measure open government data initiatives’ progress. Finally, this study offers two practical contributions: 1) it provides the basis for combining the strengths of benchmarks to create more comprehensive approaches for measuring governments’ progress in open data initiatives; and 2) it explains why particular countries are ranked in a certain way. This information is essential for governments and researchers to identify and propose effective measures to improve their open data initiatives.     

基于与非锥的新型FPGA逻辑簇互连结构研究

该文针对新型FPGA可编程逻辑单元与非锥(And-Inverter Cone, AIC)的结构特性,提出一系列方案以得到优化的逻辑簇互连结构,包括：移除输出级交叉矩阵,单级反相交叉矩阵,低负载电路优化,将反馈和输出选择功能分开,限制AIC输出级数的基础上移除中间级交叉矩阵,与LUT架构进行混合等。通过大量的实验,得出针对面积延时积最优的AIC簇互连结构,与Altera公司的FPGA芯片Stratix-IV结构相比,该结构逻辑功能簇本身面积减小9.06%, MCNC应用电路集在基于优化的AIC FPGA架构上实现的平均面积延时积减小40.82%, VTR应用电路集平均面积延时积减小17.38%;与原有的AIC结构相比,簇面积减小23.16%, MCNC应用电路集平均面积延时减小27.15%, VTR应用电路集平均面积延时积减小15.26%。     

Wire congestion estimation in a bounded-bend model

Interconnect congestion estimation plays an important role in the physical design of integrated circuits. Fast congestion analysis prior to global routing enhances the placement quality and improves the routability for the subsequent routing phases. This article presents a novel congestion estimation method for a wire layout with bounded detours and bends. Experimental results on benchmarks demonstrate the efficiency and accuracy of our approach.     

Workstation metrics

The use of measurement methods, called benchmarks, to predict how well different classes of computers will perform various tasks is discussed, and some popular benchmarks are considered. The problems entailed in benchmarking massively parallel processors and symmetric multiprocessing systems and, even more difficult, graphics workstations are examined. Requirements for advanced applications are addressed     

Thermal-aware test scheduling using network-on-chip under multiple clock rates

The increasing trend in the number of cores on a single chip has led to scalability and bandwidth issues in bus-based communication. Network-on-chip (NoC) techniques have emerged as a solution that provides a much needed flexibility and scalability in the era of multi-cores. This article presents an optimal integer linear programming (ILP) formulation and a simulated annealing (SA) solution to thermal and power-aware test scheduling of cores in an NoC-based SoC using multiple clock rates. The methods have been implemented and results on various benchmarks are presented.     

Storage performance-metrics and benchmarks

The metrics and benchmarks used in storage performance evaluation are discussed. The technology trends taking place in storage systems, such as disk and tape evolution, disk arrays, and solid-state disks, are highlighted. The current popular I/O benchmarks are then described, reviewed, and run on three systems: a DECstation 5000/200 running the Sprite Operating System, a SPARCstation 1+ running SunOS, and an HP Series 700 (Model 730) running HP-UX. Two approaches to storage benchmarks-LADDIS and a self-scaling benchmark with predicted performance-are also described     

Custom Networks-on-Chip Architectures With Multicast Routing

In this paper, we consider the problem of synthesizing custom networks-on-chip (NoC) architectures that are optimized for a given application. We consider both unicast and multicast traffic flows in the input specification. Multicast traffic flows are used in a variety of applications, and their direct support with only replication of packets at optimal bifurcation points rather than full end-to-end replication can significantly reduce network contention and resource requirements. Our problem formulation is based on the decomposition of the problem into the inter-related steps of finding good flow partitions, deriving a good physical network topology for each group in the partition, and providing an optimized network implementation for the derived topologies. Our solutions may be comprised of multiple custom networks, each interconnecting a subset of communicating modules. We propose several algorithms that can systematically examine different flow partitions, and we propose Rectilinear–Steiner-Tree (RST)-based algorithms for generating efficient network topologies. Our design flow integrates floorplanning, and our solutions consider deadlock-free routing. Experimental results on a variety of NoC benchmarks showed that our synthesis results can on average achieve a 4.82 times reduction in power consumption over different mesh implementations on unicast benchmarks and a 1.92 times reduction in power consumption on multicast benchmarks. Significant improvements in performance were also achieved, with an average of 2.92 times reduction in hop count on unicast benchmarks and 1.82 times reduction in hop count on multicast benchmarks. To further gauge the effectiveness of our heuristic algorithms, we also implemented an exact algorithm that enumerates all distinct set partitions. For the benchmarks where exact results could be obtained, our algorithms on average can achieve results within 3% of exact results, but with much shorter execution times.