Charge pumping spectroscopy: HfSiON defect study after substrate hot electron injection

Spectroscopic charge pumping (CP) is used to study the evolution of the energy distribution of trapped electrons within HfSiON/SiO₂ gate stacks under substrate hot electron injection (SHEI). Base level CP measurements with large pulse amplitude allow an efficient charging/discharging of traps and reaching two defect bands in the HfSiON situated at 0.40 and 0.85 eV above the Si conduction band, respectively. Unlike standard constant voltage stress (CVS), SHEI enables full control of the stress by separately controlling the applied gate field, the injected electron energy, and the fluence. During CVS, HfSiON defects at 0.40 eV are generated. Conversely, during SHEI, either the shallow or the deep defects are preferentially created depending on the gate field as well as electron energy.     

Reliability of ultrathin silicon dioxide under combined substratehot-electron and constant voltage tunneling stress

An experimental investigation of breakdown and defect generation under combined substrate hot-electron and tunneling electrical stress of silicon oxide ranging in thickness from 2.0 nm to 3.5 nm is reported. Using independent control of the gate current for a given substrate and gate bias, the time-to-breakdown of ultrathin silicon dioxide under substrate hot-electron stress is observed to be inversely proportional to the gate current density. The thickness dependence (2.0 nm to 3.5 nm) of substrate hot-electron reliability is reported and shown to be similar to constant voltage tunneling stress. The build-up of defects measured using stress-induced-leakage-current and charge-pumping for both tunneling and substrate hot-electron stress is reported. Based on these and previous results, a model is proposed to explain the time-to-breakdown behavior of ultrathin oxide under simultaneous tunneling and substrate hot-electron stress. The results and model provide a coherent understanding for describing the reliability of ultrathin SiO₂ under combined substrate hot-electron injection and constant voltage tunneling stress     

Study of unipolar pulsed ramp and combined ramped/constant voltage stress on mos gate oxides

MOS gate oxide capacitors over a wide range of oxide thicknesses (10.9–28 nm) were stressed using a unipolar pulsed voltage ramp and combined ramped/constant voltage stress measurements. The reliability measurements were performed with several different bias conditions in order to assess the effects of the measurement conditions on times to breakdown and breakdown fields. In the first part it was verified that the unipolar pulsed ramp yields breakdown distributions which are identical to those of a widely used staircase ramp. In the second part the unipolar pulsed ramp was used for pre-stress prior to a constant stress and measurement results were compared to those of a ramped/constant stress with a staircase ramp. In several cases a ramp prior to a constant stress increases time to breakdown. The observations made in this study imply that the time to breakdown of a constant stress in the Fowler-Nordheim tunneling regime is strongly dependent on charge trapping and, therefore, on the stressing history of the oxide. Finally, it is shown that the combined ramped/constant voltage stress is a valuable tool for monitoring extrinsic and intrinsic breakdown properties when applying stress parameters in the correct way.     

Interrelationship of voltage and temperature dependence of oxidebreakdown for ultrathin oxides

We report that voltage acceleration of time- or charge-to-breakdown is insensitive to temperature variations over a wide range of temperature (30 to 200°C) for oxides below 3 nm, regardless of oxide process, injection polarity or device type (NFET, PFET). Based on this observation, an essentially universal, non-Arrhenius temperature dependence for ultrathin oxide is obtained by a natural normalization scheme. The consequences of these findings for reliability projection are discussed     

Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress

Device degradation modelling is more and more important for reliable circuit design. On MOSFET, the threshold voltage drift in time can lead to circuit performance degradation. In this study, V_T shift due to Hot Carrier Injection stress is accelerated on small width devices. V_T matching is also degraded during stress as a function of V_T deterioration. This width dependence allows explaining gate voltage matching behavior in the sub-threshold area used in low power analog applications.     

Experimental evidence of T/sub BD/ power-law for voltage dependence of oxide breakdown in ultrathin gate oxides

In this paper, we present experimental evidence on the voltage-dependence of the voltage acceleration factors observed on ultrathin oxides from 5 nm down to /spl sim/1 nm over a wide range of voltages from /spl sim/2 V to 6 V. Two independent experimental approaches, area scaling method and long-term stress, are used to investigate this phenomenon. We show the exponential law with a constant voltage-acceleration factor violates the widely accepted fundamental breakdown property of Poisson random statistics while the voltage-dependent voltage acceleration described by an empirical power-law relation preserves this well-known property. The apparent thickness-dependence of voltage acceleration factors measured in different voltage ranges can be nicely understood and unified with these independent experimental results in the scenario of a voltage-driven breakdown. In the framework of the critical defect density and defect generation rate for charge-to-breakdown, we explore the possible explanation of increasing voltage acceleration factors at reduced voltage by assuming a geometric model for the critical defect density.     

The effect of change of voltage acceleration on temperatureactivation of oxide breakdown for ultrathin oxides

We report the effect of change of voltage acceleration on temperature dependence of oxide breakdown for ultra-thin oxides below 6 nm. The time- or charge-to-breakdown (T_BD/Q_BD) is directly measured over a wide range of temperatures (-30°C to 200°C) for several fixed voltages using different area capacitors and long-term stress. Using extensive experimental evidence, we unequivocally demonstrate that this strong temperature dependence of oxide breakdown on ultra-thin oxides is not a thickness effect as previously suggested at least for thickness range investigated in this work. It is a consequence of two experimental facts: 1) voltage-dependent voltage acceleration and 2) temperature-independent voltage acceleration within a fixed T_BD window. These results provide a coherent picture for T_BD in both voltage and temperature domains for ultra-thin oxides     

Degradation of oxides and oxynitrides under hot hole stress

The impact of nitridation on hot hole injection and the induced degradation is quantitatively studied by comparing the behavior of a control oxide and oxynitrides. The oxynitride is prepared by either annealing the oxide in N₂O or growing directly in N₂ O. The pMOSFET's are uniformly stressed by using the substrate hot hole injection technique. The physical quantities analyzed include the hole injection current, the density of created interface states and the density of trapped holes. It is found that a 30 min annealing in N₂ O at 950°C can enhance the effective barrier for hole injection by 0.6 eV. However, the interface state generation during the injection is insensitive to nitridation. The continuing degradation post the hole injection is also investigated. This includes a poststress interface state build-up and the generation of new precursors for interface states. The nitridation reduces the poststress degradation considerably. Where it is necessary, the hole induced degradation is compared with that induced by electrons. The applicability of the models proposed for oxynitrides to the present results is examined     

Dependence of Fermi level positions at gate and substrate on thereliability of ultrathin MOS gate oxides

In this work, we demonstrate that the reliability of ultrathin (<10 nm) gate oxide in MOS devices depends on the Fermi level position at the gate, and not on its position at the substrate for constant current gate injection (υ_g^-). The oxide breakdown strength (Q_bd) is less for p⁺ poly-Si gate than for n⁺ poly-Si gate, but, it is independent of the substrate doping type. The degradation of an oxide is closely related to the electric field across it, which is influenced by the cathode Fermi level for constant current injection. P⁺ poly-Si gate has higher barrier height for tunneled electrons, therefore, the cathode electric field is higher to give the same injection current density. A higher electric field gives more high-energy electrons at the anode, and therefore the damage is more at the substrate interface. We have also shown that oxide degradation is independent of the testing methodology, i.e., constant current or constant voltage stress. It depends mainly on the electric field in the oxide     

Study of hot electron degradation in submicrometer gate length MOS transistor fabricated with selectively doped substrate engineering

Investigations are made on the performance and hot electron degradation of sub-μm MOS transistors fabricated with an improved selectively doped substrate (SDS) and with the conventional deep punch through implant (DPI) structures. The sub-μm gate length of the transistor was defined by a novel subtractive photolithography technique. The technique is described and the process details are given. The sub-μm transistor performance is characterised by electron mobility, inverse subthreshold slope, substrate sensitivity and drain induced barrier lowering (DIBL) for the two structures. The substrate current and hot electron degradation effect (HED) were measured and the results are compared for SDS and DPI techniques. It is shown that SDS structure reduces HED and surface punchthrough effects in sub-μm MOS transistors.     

Quality assessment of thin oxides using constant and ramped stress measurements

Two methods are proposed for obtaining extrinsic oxide lifetime data using fast ramped tests. It is shown that the intersection point between the extrinsic and intrinsic branches of a Weibull plot coincides for ramped and constant stress tests. This is the basis of our fast qualification approach, where intrinsic data are obtained by constant voltage stress and extrinsic data are cumulated with a fast ramped test. The correctness of our approaches is supported by constant voltage and exponentially ramped current measurements.     

The study of threshold voltage extraction of nitride spacer NMOS transistors in early stage hot carrier stress

Threshold voltage V/sub t/ extracted by g/sub m/-maximum extrapolation method under early stage hot carrier stress is proven to be an inappropriate method once electrons are trapped in a nitride spacer. The trapping of electrons in a nitride spacer increases the series drain resistance, reducing the transconductance g/sub m/ and the corresponding gate-to-source voltage V/sub gs/ at which peak g/sub m/ occurs. It ultimately decreases the threshold voltage V/sub t/ extracted by the g/sub m/-maximum extrapolation method. A novel algorithm is derived to determine the relationship between the measured data and the true threshold voltage of such a device under hot carrier stress by considering the effect of series resistance in g/sub m/-maximum extrapolation method.     

High voltage degradation of GaN High Electron Mobility Transistors on silicon substrate

We have electrically stressed GaN High Electron Mobility Transistors on Si substrate at high voltages. We observe a pattern of device degradation that differs markedly from previous reports in GaN-on-SiC HEMTs. Similarly to these devices, the gate leakage current of GaN-on-Si HEMTs increases by several orders of magnitude at a certain critical voltage and this increase is irreversible. However, in contrast with devices on SiC, the critical voltage varies substantially across the wafer, even over short distances, with values as high as 75 V being observed. In addition, for voltages below the critical voltage, we observe a prominent degradation in the drain current and the source and drain resistances, something not observed in devices on SiC. This degradation is almost completely recoverable under UV illumination. We attribute these results to the high mismatch that exists between GaN and Si that leads to a large concentration of electrically active traps and a lower and non-uniform initial strain in the AlGaN barrier. This is evidenced by observed correlations between threshold voltage and maximum drain current in fresh devices and their corresponding critical voltages.     

Weibull characteristics of n-MOSFET's with ultrathin gate oxides under FN stress and lifetime prediction

Subthreshold gate voltage shift ΔV_gw of n-MOSFET's with different oxide thicknesses aging at various stress conditions was statisticalized using Weibull distribution. Based on the statistical results, an empirical expression for the relationship between average lifetime and acceleration field was developed, and lifetime predictions were made. Results show that the shape factors (β) of intrinsic failure of the devices with 5.0, 7.0, and 9.0 nm gate oxides under 27 and 105 °C are the same, namely, the mechanisms of the intrinsic failure are the same under low and high temperatures. The proportion of the extrinsic failure increases with temperature increasing. A lifetime prediction method was developed based on the exponential relationship between lifetime and acceleration field. This method can be applied to predict the lifetime of n-MOSFET's with ultrathin gate oxides under FN stress.     

Effect of stress voltages on voltage acceleration and lifetime projections for ultra-thin gate oxides

This paper investigates the effect of NFET (N+ poly gate, N+ diffusion of FET) stress voltage conditions, for ultra-thin gate oxides, on the voltage acceleration, and lifetime projections to use conditions. This work employs the model relating the critical defect density (N^BD) to the charge-to-breakdown and the defect generation probability (P_g). The models for N^BD and P_g were adjusted for effects at voltages between 2 V and 3 V, and oxide thickness less than 2.7 nm. For N^BD, a model is proposed that is supported by published data and provides a gradual transition to a plateau for oxide thickness less than 2.7 nm. For P_g, a stronger dependency of Log(P_g) in the range of 2–3 V is employed to give a better fit to published data. This adjusted P_g is also used below 2 V to show trend of projection. In the direct tunneling range below 3 V, there is an increase of the voltage acceleration factor (AF) with decreasing voltage. Also, below 3 V, AF shows a decrease as the oxide thickness is reduced from 2.0 nm to 1.2 nm, and this trend becomes stronger as the gate voltage is reduced. Above a gate stress voltage of 3 V, in the range of 3–4 V, AF is almost constant, and there is a slight decrease of AF with decreasing oxide thickness in the range of 2.0–1.2 nm. A voltage power-law fit for the range above 3 V shows a decreasing power index with decreasing oxide thickness.     

Role of stress voltage on structural degradation of GaN high-electron-mobility transistors

In GaN high-electron-mobility transistors, electrical degradation due to high-voltage stress is characterized by a critical voltage at which irreversible degradation starts to take place. Separately, cross-sectional TEM analysis has revealed significant crystallographic damage for severely degraded devices. Furthermore, a close correlation between the degree of drain current degradation and material degradation has been reported. However, the role of the critical voltage in physical degradation has not been explored. In this work, we investigate the connection between electrical degradation that occurs around and beyond the critical voltage and the formation of crystallographic defects through detailed electrical and TEM analysis, respectively. We find that a groove in the GaN cap starts to be generated around the critical voltage. At higher voltages, a pit develops that penetrates into the AlGaN barrier. The size of the pit increases with stress voltage. We also observe a good correlation between electrical and material degradation.     

Determination of spatial surface state density distribution in MOS and SIMOS transistors after channel hot electron injection

The charge pumping technique has been adapted for the determination of the spatial distribution of the interface state density in the channel region of short channel MOS or SIMOS transistors. This spatial distribution is shown to be modified by channel hot electron injection and provides information on the location and width of the injection region.     

Hot electron and hot hole degradation of UHV/CVD SiGe HBT's

We investigate the degradation in current gain and low-frequency noise of SiGe HBT's under reverse emitter-base stress due to hot electrons (forward-collector stress) and hot holes (open-collector stress). Contrary to previous assumptions we show that hot electrons and hot holes with the same kinetic energy generate different amounts of traps and hence have a different impact on device degradation. These results suggest that the accuracy of using forward-collector stress as an acceleration tool and reliability predictor must be carefully examined. We also present, for the first time, the effect of Ge profile shape on the reliability of SiGe HBT's, as well as discuss measurements on SiGe HBT's as a function of device geometry and temperature     

Effect of long-term stress on IGFET degradations due to hot electron trapping

The threshold voltage shift through the long-term stress is measured for IGFET's. The gate bias dependence shows that the hot electron trapping is affected strongly by the electric field in the gate insulator. The threshold voltage shift versus time is well explained with the theory modified by the effect of the trapped charge on the subsequent electron trapping. The effect of transistor dimensions and temperature are also discussed.