Power efficient data path synthesis of sum-of-products computations

Techniques for the power efficient data path synthesis of sum-of-products computations between data and coefficients are presented. The proposed techniques exploit specific features of this type of computations. Efficient heuristics for the scheduling and assignment tasks, based on the concept of the Traveling Salesman's Problem, are described. Different cost functions are proposed to drive the synthesis tasks. The proposed cost functions target the power consumption either in the interconnect buses or in the functional units. Experimental results from different relevant digital signal processing algorithmic kernels prove that the proposed synthesis techniques lead to significant power savings.     

ASIC techniques for high-performance digital signal processing

We describe a high-level ASIC (application specific integrated circuit) synthesis system aimed at rapid and efficient realisation of integer arithmetic “engines” for signal processing bottleneck computations. Novel software features include bit-level scheduling which allocates numerical resources for computation, and a parameter synthesis system which maximises the use of this resource. Underlying synthesis is a generic digit-serial integer arithmetic processing architecture, with module generation capability across a wide parameter space for a useful set of primitive arithmetic operations. We outline the principal components of the tool, and briefly describe some application examples.     

A practical method of coefficient computation for a microprocessor-controlled variable recursive digital filter

The synthesis of general-type recursive digital filters from analog prototypes may require complicated computations not suitable for filter structures where the coefficients are to be evaluated by a microprocessor control unit. A general synthesis procedure suitable for the application to such structures is described and some design examples are reported.     

Computational methods for real-time Fourier synthesis

In Fourier synthesis, natural musical sounds are produced by summing time-varying sinusoids. Sounds from individual instruments are analyzed to find the amplitude and frequency characteristics for their sinusoids; interpolation between the characteristics of several sounds is used to produce intermediate timbres. An ensemble can be synthesized by summing all the sinusoids for several sounds, but in practice it is difficult to perform such computations in real time. To solve this problem on inexpensive hardware, the author takes advantage of the masking effects of the auditory system. By avoiding the computations for perceptually unimportant sinusoids, and by using other computation reduction techniques to achieve interpolation, a large ensemble can be synthesized in real time. Unlike existing computation reduction techniques, the techniques described in this correspondence do not sacrifice independent fine control over the amplitude and frequency characteristics of each sinusoid     

Synthesis of near-field patterns of a nonuniformly spaced array

A technique of synthesis of near-field patterns of a nonuniformly spaced linear array of point dipoles with identical direction of current flow for each array element, or a uniformly spaced array of point dipoles with variation in direction of current flow for each dipole is presented. Further, it is described how one should prescribe the near-field (NF) pattern and how one should sample the same, while performing the NF pattern synthesis. Also discussed is how NF pattern synthesis should be performed so that the synthesized NF amplitude pattern closely follows a prescribed far-field amplitude pattern of the same array. Numerical computations are performed to demonstrate the validity of the physical concepts made use of in the technique proposed for performing the NF pattern synthesis successfully.     

Power-Aware 3D Computer Graphics Rendering

Real-time 3D Graphics rendering consumes significant power because of its very high computation and memory access rate. Due to variation in workload and perceptual tolerance, power-awareness can optimize this power consumption significantly, thus facilitating migration to future power-constrained devices such as personal digital assistants (PDAs), tablets, wearables, phones etc. This work proposes such a low power system based on Approximate Graphics Rendering (AGR). The AGR system supports various algorithms and incremental changes to the computational mechanism based on certain pre-specified parameters. The knowledge available apriori about the signal and noise models of graphic images and Human Visual Perception (HVP) are used to select the configuration that meets the quality needs at the lowest power consumption. The power savings using the AGR system are examined for two power hungry stages of the 3D graphics rendering system, namely shading and texture mapping. Besides supporting various algorithms, two novel parameterizable computation schemes are proposed. First, iterative COordinate Rotation DIgital Computer (CORDIC) algorithm based units are incorporated for certain computations. Second, a scheme for dynamically enhancing the perceived image spatial correlation for reduced computations is presented. A hardware synthesis and estimation methodology based on realistic graphics content from the well-known 3D graphics benchmarks and the game Quake2 [1] is used for estimation of power savings. Significant power savings of 75.1%, 73.8% and 72% are demonstrated in the shading, texture mapping function blocks and CORDIC based 3D vector interpolator respectively.     

Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis

Multimedia applications such as video and image processing are often characterized by a huge number of data accesses. In many digital signal processing applications, array access patterns are regular and periodic. In these cases, optimized architectures using pipelined memory access controllers can be generated. In this paper, we focus on implementing memory interfacing modules that can be automatically generated from a high-level synthesis tool and which can efficiently handle predictable address patterns as well as random ones (i.e., dynamic address computations). The benefits of balancing dynamic address computations from datapath to dedicated computation units in the memory controller is also analyzed as well as operator bitwidth optimization and data locality to save power consumption and reduce latency.      

PC programs for engineers. Analysis and synthesis of passive filters

The program described in this column is not just another vehicle for performing the computations involved in network synthesis. Rather, it provides a multidimensional educational environment that allows interactive access to a wide range of material, including theoretical foundations, visualization of abstract concepts, and software from synthesis and analysis. All of this is packaged in an unusually sophisticated, graphics-enhanced shell that is a pleasure to use and explore.     

Quick stability test for 2-D digital filters

Many stability tests that are available for 2-D digital filters require long and tedious computations. In the automatic synthesis or optimisation of these filters, it is necessary that the stability is assessed very rapidly. In the letter two necessary conditions of stability are derived. Evaluation of these conditions indicate the stability of the filters. As these conditions are extremely easy to evaluate, they can be incorporated into a CAD programme.     

Efficient Block Scheduling to Minimize Context Switching Time for Programmable Embedded Processors

Scheduling is one of the most often addressed optimization problems in DSP compilation, behavioral synthesis, and system-level synthesis research. With the rapid pace of changes in modern DSP applications requirements and implementation technologies, however, new types of scheduling challenges arise. This paper is concerned with the problem of scheduling blocks of computations in order to optimize the efficiency of their execution on programmable embedded systems under a realistic timing model of their processors. We describe an effective scheme for scheduling the blocks of any computation on a given system architecture and with a specified algorithm implementing each block. We also present algorithmic techniques for performing optimal block scheduling simultaneously with optimal architecture and algorithm selection. Our techniques address the block scheduling problem for both single- and multiple-processor system platforms and for a variety of optimization objectives including throughput, cost, and power dissipation. We demonstrate the practical effectiveness of our techniques on numerous designs and synthetic examples.     

The combined-maximum principle in problems of estimating the motion parameters of a maneuvering aircraft

The synthesis of an optimum tracking filter for a maneuvering aircraft, a problem that is considered an inverse dynamic problem, is studied on the basis of the combined-maximum principle. The filter equations are obtained without the use of the method of invariant immersion. It is shown that the estimates of trajectory parameters that are obtained via application of the new tracking filter possess higher accuracy characteristics than the estimates of the extended Kalman filter and considerably decrease the amount of computations.     

Optimum and heuristic transformation techniques for simultaneousoptimization of latency and throughput

Although throughput alone can be arbitrarily improved for several classes of systems using previously published techniques, none of those approaches are effective when latency constraints, which are increasingly important in embedded DSP systems, are considered. After formally establishing the relationship between latency and throughput in general computation, we explore the effect of pipelining on latency, and establish necessary and sufficient conditions under which pipelining does not alter latency. Many systems are either linear, or have subsystems that are linear. For such cases we have used a state-space based approach that treats various transformations in an integrated fashion, and answers analytically whether it is possible to simultaneously meet any given combination of constraints on latency and throughput, The analytic approach is constructive in nature, and produces a complete implementation when feasibility conditions are fulfilled. We also present a suboptimal but hardware efficient heuristic approach for the special case of initially-relaxed single-input single-output linear time-invariant computations. A novel software platform consisting of a high-level synthesis system coupled to a symbolic algebra system was used to implement the proposed algorithm transformations. Instead of optimizing to improve throughput and latency, our transformations can also be used to increase the implementation efficiency while achieving the same latency and throughput as the original design     

An interpolation technique in the design of pulse-forming networks

This paper presents a new method of synthesis of low-pass filters for pulse applications. A piecewise linear model is first introduced to define the phase characteristic of the idealized minimum phase network and then approximated by interpolation technique at equidistant points. The transient response to a unit step and the attenuation characteristic are controlled by two variable parameters which are determined by iterative procedure. The necessary computations are simple, since only linear equations are involved in computational process. The transient responses of the resulting filters are superior to other known systems and compare favourably even with the Schüssler filters with equi-ripple step response.     

Clairvoyant: a synthesis system for production-based specification

This paper describes a new high-level synthesis system based on the hierarchical production based specification (PBS). Advantages of this form of specification are that the designer does not describe the control flow in terms of explicit states or control variables, and that the designer does not describe a particular form of implementation. The production-based specification also separates the specification of the control aspects and data-flow aspects of the design. The control is implicitly described via the production hierarchy, while the data-flow is described as action computations. This approach is a hardware analog of popular software engineering techniques. The Clairvoyant system automatically constructs a controlling machine from the PBS and this process is not impacted by the possibly exponentially larger deterministic state space of the designs. The encodings generated by the constructions compare favorably to encodings derived using graph-based state encoding techniques in terms of logic complexity and logic depth. These construction techniques utilize recent advances in BDD techniques     

Time-constrained scheduling during high-level synthesis offault-secure VLSI digital signal processors

Advances in VLSI technology are making it feasible to pack millions of transistors on a single chip. A consequent increase in the number of on-chip faults as well as the growing importance of quality-metrics such as reliability and fault-tolerance are making on-chip fault-tolerance mandatory. On-chip realization of a computation is fault-secure if an observable error in the computation is detected. Components used in life-critical systems should be secured against all faults. While fault-security can be realized by duplicating the computation on disjoint hardware and voting on the result(s), such straightforward strategies entail appreciable hardware overhead. This paper presents computer-aided behavioral synthesis of fault-secure microarchitectures which require less than proportional increase in hardware. The strategy selects intermediate computations for additional voting. The resulting class of fault-secure microarchitectures supplants the enormous hardware requirements of naive fault-secure strategies with enhanced hardware utilization afforded by securing the intermediate computations. Experimental results show that fault-security can be implemented at a less than proportional increase in hardware overhead     

High-speed 2-D convolution with a custom computing machine

Custom computing machines, a class of computational platforms consisting of reconfigurable functional units with reconfigurable interconnection networks, provide a middle-ground between special-purpose hardware, which provide high execution speed, and general-purpose computers, which offer flexibility. The Splash-2 system, one such custom computing machine, is an experimental platform for complex computations requiring the high speed of special-purpose hardware. The reconfigurability and modularity of Splash-2, along with automated synthesis tools, allow for rapid, staged development of applications. This paper demonstrates the applicability of Splash-2 to the image-processing area and gives an introduction to the programming environment used in developing applications. An example image-processing application based upon two-dimensional convolution is described and the operating procedures of custom computing machines are presented. Also presented are the details of directly implementing two-dimensional convolution in a straight-forward, systolic fashion in reconfigurable hardware.This research has been supported in part by the National Science Foundation (NSF) under grant MIP-9308390.     

Optimum optical limited scan antenna

An optical limited scan antenna system is considered for applications such as spot coverage of a small portion of the earth from a satellite. The optimum criterion relating aperture efficiency, number of control elements, and angular coverage is revisited briefly. The optical scheme advocated utilizes a bootlace aperture lens, a generalized Luneberg lens focused to the near field, and a small array of active elements. The operation of the system is described first in terms of geometrical optics and elementary diffraction principles. The subarray viewpoint is then developed using simplified diffraction concepts. These results form the basis of a design procedure for the synthesis of high performance limited scan systems. An accurate solution necessary for the analysis of small antennas is developed using a modal decomposition and the wave equation. Numerical computations for a case of practical interest verify the expectation of near optimum performance.     

Si1-xGex单晶用热系统改进

阐述了对原GaAs单晶拉制用LEC单晶炉热系统进行改造使其适于Si1-xGex单晶生长的过程。借助数值模拟的方法分析了晶体生长区域内的温度分布情况，并通过分析发现了原有热系统的不足。重新对原热系统进行了改造，添加了起到保温和氩气导流作用的热屏和上保温装置，使原来的敞开式热场变为密闭式热场，满足了SihGe；单晶拉制的要求。通过具体实验和数值模拟结合，分析了氩气流场及不同流场对晶体生长的影响，发现并改进了单晶炉的氩气供给装置存在的问题。     

Algebraic fields, signal processing, and error control

This survey paper is intended to integrate the subjects of digital signal processing and error control codes by studying their common dependence on the properties of the discrete Fourier transform. The two subjects are traditionally studied in different algebraic fields. Usually, the computations of digital signal processing are done using the complex number system, while the computations of error control codes are done using the arithmetic of Galois fields. We will argue that this dichotomy may be partly a historical accident. By viewing the two problems in the opposite number system, we shall find that there are parallels and that many techniques can be shared by the two subjects. The new material included within the paper is introduced in order to extend known techniques used in one algebraic field into another algebraic field where those techniques are not yet used.