An ECL-compatible GaAs MESFET 1-kbit static RAM

A fully ECL-compatible GaAs enhancement/depletion (E/D)-MESFET 1-kb static RAM was designed, fabricated, and tested. Direct-coupled FET logic is used for the memory array while buffered FET logic is utilized in the peripheral circuitry to provide an ECL 100 K interface. The memory cell area is 774 /spl mu/m/SUP 2/, and the chip size is 2.0/spl times/1.75 mm/SUP 2/. Fabrication of the 1-kb RAM involves a fully implanted two-threshold process with true double-level metal interconnection. A minimum access time of 1.3 ns has been obtained with a total power dissipation of 1.4 W (memory array power dissipation is only ~40 mW). The output voltage swing across a 50-/spl Omega/ load is 750 mV.     

GaAs E/D MESFET 1-kbit static RAM fabricated on silicon substrate

A GaAs enhancement/depletion (E/D) MESFET 1-kbit static RAM has been fabricated on a 2-in GaAs-on-Si substrate. This is the most complex GaAs circuit reported to date for GaAs-on-Si material. The GaAs layer is grown on a     

GaAs 256-bit static RAM

A GaAs 256×1-bit static RAM with 2000 FETs organised in E/D-type DCFL circuits was successfully fabricated. A planar device structure was realised by using selective ion implantation and dielectric intermediate lift-off technology. The access time and the power dissipation were 50 ns and 9.4 mW, respectively.     

A GaAs 16-kbit static RAM using dislocation-free crystal

A GaAs 16-kbit static RAM was developed using high-density integration technology and high-uniformity crystal. Highly integrated SAINT FET's with 1.0-µm gate length and 1.5-µm interconnection lines were formed by self-alignment and fine photolithography. Highly uniform crystal with less than 20-mV threshold scattering was obtained from an In-doped dislocation-free LEC with a 2-in diameter. An address access time of 4.1 ns was obtained with an associated power dissipation of 1.46 W.     

Estimation of GaAs static RAM performance

A simple and accurate GaAs MESFET model for circuit simulation has been established. Calculated static and dynamic performance have been found to coincide well with experimental results. RAM performance with various FET's was estimated adopting this model for the simulation. Reduction in series resistance by n⁺doping outside a gate and/or shortening source-drain distance is predicted to be very effective in improving not only access time, but also threshold-voltage margin. A 1-kbit static RAM with 0.8 ns at 400-mW dissipation power will be attainable by using a 0.5-µm gate length FET, with an allowable threshold-voltage standard deviation of 80 mV.     

16K CMOS/SOS asynchronous static RAM

A new CMOS/SOS `buried-contact' process allows fabrication of dense static memory cells. The technology is applied in a 16K RAM with 1150 /spl mu/m/SUP 2/ (1.78 mil/SUP 2/) cells based on 5 /spl mu/m design rules.     

A four-phase handshaking asynchronous static RAM design forself-timed systems

The motivation of designing asynchronous memory arises from the recent development of asynchronous processors. As different from the conventional design, the proposed asynchronous static RAM can: (1) communicate with other asynchronous systems based on a four-phase handshaking control protocol; and (2) generate the read/write completion signals with increased average speed by the variable bit-line load concept. The techniques investigated include (1) dual-rail voltage sensing completion detection for read operation and (2) multiple delays completion generation for write operation. In this paper, the performances of these techniques are evaluated for 1 Mb memory with four regions of bit-line segmentation. The simulated and measured results are presented and compared     

A novel low-power static GaAs MESFET logic gate

A novel GaAs MESFET logic gate is described. The gate uses depletion mode FET's and is a static one. It is about 30% faster and consumes about 30% of the power of the BFL gate. Ring oscillator circuits have been fabricated using one embodiment of the gate. For unity fan-out, an average propagation delay of 58.7 ps with a power dissipation of 18.8 mW has been achieved.     

A GaAs 1K static RAM using tungsten silicide gate self-aligned technology

This paper reports a GaAs 1K static RAM, fabricated using tungsten silicide gate self-aligned technology with full ion implantation. With 2-/spl mu/m gate length, an address access time of 3.6 ns and a minimum write-enable pulse width of 1.6 ns were achieved with a power dissipation of 68 mW. The access time compares favorably to those of currently reported high-speed Si bipolar memories, and the greatly decreased power dissipation is better by one order of magnitude. An address access time of 0.88 ns can be achieved by shortening the gate length to 1 /spl mu/m and adopting a 2-/spl mu/m design rule in the layout.     

Design of GaAs 1k bit static RAM

A 1 k bit GaAs static RAM with E/D DCFL was designed and successfully fabricated by SAINT. A bit line pull-up was introduced to the design to make higher operation speed by 25 percent and reduce cell array power consumption by 50 percent. The RAM circuit was optimized in the points of a speed, a power, and an operating margin. A minimum address access time of 1.5 ns was measured for a total power dissipation of 369 mW. This performance is the best achieved so far, for practical application in cache or buffer memories.     

The collector-coupled static RAM cell

The collector-coupled static RAM cell uses a schottky collector transistor switch with merged vertical n-p-n load. The cell is constructed with two dual Schottky collector transistors and one merged dual collector n-p-n transistor. It has been fabricated in an infant oxide isolated bipolar technology and bistability has been demonstrated over four orders of magnitude in cell current (10 nA相似文献   

GaAs 1 kbit static RAM with self-aligned FET technology

A GaAs-1 kbit RAM is demonstrated to realize high-speed switching at the LSI level. The SAINT FET is utilized to eliminate the surface depletion without an increase of excess capacitance. To lower the threshold voltage standard deviation, a one-direction gate arrangement is adopted. A pull-up circuit is also a new addition to the first reported RAM. The resulting RAM performances are 1.5 ns address access time with 369 mW power consumption. The minimum write-enable pulsewidth is less than 2 ns. The maximum number of good bits is 1001 bits/1024 bits. The problems of mass production of GaAs LSI are discussed.     

GaAs MESFET fabrication without using photoresist

MBE-grown MESFET wafers were patterned with a novel resistless approach and InAs was selectively grown in the source and drain regions. Photoresist and the associated process steps and chemicals were eliminated by utilizing gallium oxide as the masking material. Metallization for the source, drain and self aligned gate was carried out in one step, also without using any photoresist. Device structures with gate lengths ranging from submicron to 10 μm were fabricated     

An ultrahigh-speed GaAs MESFET operational amplifier

A wide-bandwidth GaAs MESFET operational amplifier is reported, with a 65-dB DC gain and a 20-GHz gain-bandwidth product at 500 MHz. The circuit uses a variety of local feedback techniques to enhance the overall gain. The use of an undoped GaAs buffer, grown at a relatively low temperature (≈300°C), eliminates backgating and light sensitivity. The circuit was fabricated in an 80-GHz f_T MESFET process, with 0.2-μm electron-beam defined gates. The high levels of 1/f noise, MESFET frequency-dependent output conductance, and large offset voltage standard deviation limit the application of the circuit to moderate precision applications     

A GaAs 1-kbit static RAM with a shallow recessed-gate structure FET

A novel GaAs FET structure, the shallow recessed-gate structure, has been proposed and applied to a 1-kbit static RAM. In order to decrease the source resistance Rsand gate capacitance Cg, the shallow n⁺implanted layer was formed between the gate and source/drain region; then the gate region was slightly recessed. This FET has a high transconductance gm, low source resistance Rs, small gate capacitance Cg, and small deviation of threshold voltagepart V_{th}, and thus is suitable for high-speed GaAs LSI's. A 1-kbit static RAM has been designed and fabricated applying this FET structure and an access time of 3.8 ns with 38- mW power dissipation has been obtained.     

A high-density MOS static RAM cell using the lambda bipolar transistor

Based upon the common-collector lambda bipolar transistor (LBT), which is built with p-well NMOS, and the parasitic n-p-n BJT in a CMOS IC, a novel MOS static RAM cell called the LBT cell is proposed. In this new cell, the LBT and two poly-Si resistors form a bistable element with a PMOS access transistor. With the minimum feature size F, the optimal cell area of 32 F/SUP 2/ can be realized by using the silicide contact and small p-well spacing. The READ-WRITE operation is simulated. Due to the need of precharging before reading and the rather slow recovery after reading, suitable peripheral circuits should be designed.     

Electrical current instability at gate breakdown in GaAs MESFET

The gate burnout (irreversible breakdown) of GaAs MESFET has been studied using two-dimensional (2-D) numerical simulation and experimental measurements of 10 ns pulsed gate-drain I-V characteristics, it is shown, that at some critical level of gate avalanche current the gate current instability appears. The instability results in formation of the negative differential conductivity (NDC) region on the S-shape gate-drain I-V characteristic, spatial instability of avalanche current and formation of high density current filaments. At some critical length of n⁺-contact regions a spatial instability results in spontaneous formation of multiple spatial-periodic filaments     

GaAs MESFET fabrication using maskless ion implantation

A 2000-Å-diameter focused-ion beam from a Au-Si liquid-metal-alloy ion source was used to implant the doped regions of GaAs metal-semiconductor gate field-effect transistors. An Al stopping layer on the wafer was used to trap the Au ions. The 140-keV Si⁺⁺beam component was deflected under computer control to implant 8 × 50 µm active channel regions and 16 × 50 µm contact regions. The devices were metallized using conventional lithography. DC electrical characteristics of the 1.5-µm-gate-length devices are comparable to those of conventionally processed devices of identical geometry.     

A new structure GaAs MESFET with a selectively recessed gate

A new structure for GaAs MESFET's has been proposed. The structure features a gate recess which is formed on the original surface of an MBE grown GaAs active layer through selective etching of the overgrownn^{+}-Ga_{1- x}Al_{x}Assource/drain layer. Because of heavy doping in theGa_{1-x}Al_{x}Aslayer, the new MESFET structure offers a low source resistance. The selective etching technique for gate recess formation holds the MBE grown active layer thickness unchanged. As a result, the FET characteristics such as IDSSand Vpof devices fabricated from one wafer are strikingly uniform.