DEPACT: delay extraction-based passive compact transmission-line macromodeling algorithm

With the continually increasing operating frequencies, signal integrity and interconnect analysis in high-speed designs is becoming increasingly important. Recently, several algorithms were proposed for macromodeling and transient analysis of distributed transmission line interconnect networks. The techniques such as method-of-characteristics (MoC) yield fast transient results for long delay lines. However, they do not guarantee the passivity of the macromodel. It has been demonstrated that preserving passivity of the macromodel is essential to guarantee a stable global transient simulation. On the other hand, methods such as matrix rational approximation (MRA) provide efficient macromodels for lossy coupled lines, while preserving the passivity. However, for long lossy delay lines this may require higher order approximations, making the macromodel inefficient. To address the above difficulties, this paper presents a new algorithm for passive and compact macromodeling of distributed transmission lines. The proposed method employs delay extraction prior to approximating the exponential stamp to generate compact macromodels, while ensuring the passivity. Validity and efficiency of the proposed algorithm is demonstrated using several benchmark examples     

Modeling and Analysis of On-Chip Single and H-tree Distributed RLC Interconnects

This paper presents novel methods for modeling and analysis of on-chip Single and H-tree distributed resistance inductance capacitance interconnects. The matrix pade-type approximation and scaling and squaring methods are employed for the numerical estimation of delay in single interconnect, and H-tree interconnects. The proposed models, which are based on these methods, provide rational function approximation for obtaining a passive interconnect model. Multiple single input single output model approximated transfer functions are developed for H-tree interconnects structure. With the equivalent reduced order lossy interconnect transfer functions, finite ramp responses are obtained, and line delay is estimated for various line lengths, input ramp rise times, source resistances, parasitic capacitances and load capacitances. In order to demonstrate the accuracy of proposed models, the estimated 50 % delay values are compared with the standard HSPICE W-element model and are found to be in good agreement. The proposed models worst case 50 % delay errors of single interconnect are 0.27 and 0.24 % respectively, while the worst case 50 % delay errors of H-tree structure are 5.73 and 3.94 % respectively.     

A clock interconnect extractor for multigigahertz frequencies incorporating inductance effect

Due to decreasing device sizes and increasing clock speed, interconnect inductance is becoming an important factor in the on-chip delay analysis of deep submicrometer technologies. This delay has been represented as an RC model in the available electric design automation tools. In this paper, we model the on-chip interconnect as a RLC for systems running at multigigahertz frequencies. A static-extraction analysis method optimized for ASICs is detailed. It considers all the lines within the vicinity of the target signal line as return paths.     

A simple method for on-chip, sub-femto Farad interconnectcapacitance measurement

In this letter, a sensitive and simple technique for parasitic interconnect capacitance measurement and extraction is presented. This on-chip technique is based upon an efficient test structure design that utilizes only two transistors in addition to the unknown interconnect capacitance to be characterized. No reference capacitor is needed. The measurement itself is also simple; only a dc current meter is required. Furthermore, the extraction methodology employs a self-checking algorithm to verify that the extracted capacitance value is consistent and accurate. The technique is demonstrated by extracting the capacitance of a single crossover between a Metal 1 line and a Metal 2 of 0.44 fF. The resolution limit is dominated by the matching of the minimum sized transistors used for the test structure. We estimate this resolution limit to be about 0.03 fF     

On the impact of on-chip inductance on signal nets under the influence of power grid noise

It has been well recognized that the impact of on-chip inductance on some critical nets, such as clock nets, is significant and cannot be ignored in delay modeling for these nets. However, the impact of on-chip inductance on signal nets in general is still not well understood. We present results of analyzing inductive effects on signal nets for ultradeep submicron technologies under the influence of power grid noise. The analysis is based on an Al-based 0.18-/spl mu/m CMOS process and a Cu-based 0.13-/spl mu/m CMOS process. The impact of on-chip inductance is shown to be insignificant if we assume a perfect power supply network around the interconnect routes. Otherwise, the impact of on-chip inductance can be significant. Furthermore, the results presented in this paper illustrate the impact of on-chip inductance one would expect from transitioning from an Al-based interconnect technology to a Cu-based interconnect technology. A heuristic method is proposed in the paper to account for the inductive coupling due to power grid noise in signal delay modeling and simulations.     

Designing fast on-chip interconnects for deep submicrometer technologies

This paper proposes a solution to the problem of improving the speed of on-chip interconnects, or wire delay, for deep submicron technologies where coupling capacitance dominates the total line capacitance. Simultaneous redundant switching is proposed to reduce interconnect delays. It is shown to reduce delay more than 25% for a 10-mm long interconnect in a 0.12-/spl mu/m CMOS process compared to using shielding and increased spacing. The paper also proposes possible design approaches to reduce the delay in local interconnects.     

Enhanced transmission characteristics of on-chip interconnects withorthogonal gridded shield

On-chip interconnects over an orthogonal grid of grounded shielding lines on the silicon substrate are characterized by full-wave electromagnetic simulation. The analysis is based on a unit cell of the periodic shielded interconnect structure. It is demonstrated that the shielding structure may help to significantly enhance the transmission characteristics of on-chip interconnects particularly in analog and mixed-signal integrated circuits with bulk substrate resistivity on the order of 10 Ω-cm. Simulation results for the extracted R, L, G, C transmission line parameters show a significant decrease in the frequency-dependence of the distributed shunt capacitance as well as decrease in shunt conductance with the shielding structure present, while the series inductance and series resistance parameters are nearly unaffected. An extension of the equivalent circuit model for the shunt admittance of unshielded on-chip interconnects to include the effects of shielding is also presented     

On-chip inductance cons and pros

Provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the undesirable effects of on-chip inductance are higher interconnect coupling noise and substrate coupling, challenges for accurate extraction, the required modifications of the infrastructure of CAD tools, and the inevitably slower CAD tools as compared to RC-based tools. Among the desirable effects is lower power consumption, less need for repeaters, faster signal rise time, and less delay uncertainty. The viability of design methodologies considering on-chip inductance is briefly discussed.     

Evaluating the effects of temperature gradients and currents nonuniformity in on-chip interconnects

The paper provides a compact but accurate electro-thermal model of a long wiring on-chip interconnect embedded in the complex layout of a ULSI digital circuit. The proposed technique takes into account both the effect of temperature gradients over the chip substrate and the interconnect self-heating due to current flow. The proposed compact model is well suited to be interfaced with commercially available CAD tools employed for interconnect parasitic extraction and signal integrity verification. The paper also investigates the electro-thermal effects that arise in a long wiring on-chip interconnect in which current flow is dominated by displacement currents and thus is not uniform along the line.     

一种基于目标延迟约束缓冲器插入的互连优化模型

基于分布式RLC传输线,提出在互连延迟满足日标延迟的条件下,利用托格朗日函数改变插入缓冲器数目与尺寸来减小互连功耗和面积的优化模型.在65nm CMOS工艺下,对两组不同类型的互连线进行计算比较,验证该模型在改善互连功耗与面积方面的优点.此模碰更适合全局瓦连线的优化,而且互连线越长,优化效果越明显,能够应用于纳米级SoC的计算机辅助设计和集成电路优化设计.     

一种基于目标延迟约束缓冲器插入的互连优化模型

基于分布式RLC传输线,提出在互连延迟满足目标延迟的条件下,利用拉格朗日函数改变插入缓冲器数目与尺寸来减小互连功耗和面积的优化模型. 在65nm CMOS工艺下,对两组不同类型的互连线进行计算比较,验证该模型在改善互连功耗与面积方面的优点. 此模型更适合全局互连线的优化,而且互连线越长,优化效果越明显,能够应用于纳米级SOC的计算机辅助设计和集成电路优化设计.     

A Parameterization Scheme for Lossy Transmission Line Macromodels With Application to High Speed Interconnects in Mobile Devices

We introduce a novel parameterization scheme based on the generalized method of characteristics (MoC) for macromodels of transmission-line structures having a cross section depending on several free geometrical and material parameters. This situation is common in early design stages, when the physical structures still have to be finalized and optimized under signal integrity and electromagnetic compatibility constraints. The topology of the adopted line macromodels has been demonstrated to guarantee excellent accuracy and efficiency. The key factors are propagation delay extraction and rational approximations, which intrinsically lead to a SPICE-compatible macromodel stamp. We introduce a scheme that parameterizes this stamp as a function of geometrical and material parameters such as conductor-width and separation, dielectric thickness, and permittivity. The parameterization is performed via multidimensional interpolation of the residue matrices in the rational approximation of characteristic admittance and propagation operators. A significant advantage of this approach consists of the possibility of efficiently utilizing the MoC methodology in an optimization scheme and eventually helping the design of interconnects. We apply the proposed scheme to flexible printed interconnects that are typically found in portable devices having moving parts. Several validations demonstrate the effectiveness of the approach     

A multiconductor transmission line methodology for global on-chip interconnect modeling and analysis

This paper describes a methodology for global on-chip interconnect modeling and analysis using frequency-dependent multiconductor transmission lines. The methodology allows designers to contain the complexity of series impedance computation by transforming the generic inductance and resistance extraction problem into one of per-unit-length parameter extraction. This methodology has been embodied in a CAD tool that is now in production use by interconnect designers and complementary metal oxide semiconductor (CMOS) process technologists.     

Modeling techniques for energy-efficient system-on-a-chip signaling

In order to tackle noise, delay, and power in the deep-submicron age, the most efficient approach is to design power-efficient and robust signaling techniques that allow for reliable communication between CMOS gates. This is referred to as energy-efficient on-chip-signaling. To design, optimize, and compare different signaling schemes, it is important to properly model on-chip wires. This article describes several techniques used in interconnect modeling. It focuses on the efficient modeling of on-chip wires, investigates the impact of inductive and capacitive coupling on the quality of the signal and the wire-load model, and contains a quantification of the impact of the wire model on the design of efficient signaling techniques.     

A multilevel parasitic interconnect capacitance modeling andextraction for reliable VLSI on-chip clock delay evaluation

This paper describes fringing and coupling interconnect capacitance models which include the nonlinear second-order effects of field interactions among multilevel parasitic interconnects for accurate circuit simulations. They are fitted well with numerical solutions by using a Poisson equation solver. A reliable parasitic distributed resistance-inductance-capacitance (RLC) extraction method is identified by using the solver with the bounded local three-dimensional (3-D) numerical analysis to reduce excessive central processing unit (CPU) time compared to full 3-D numerical simulation. We investigate the impact of input slew variations on the traversal clock delay within the slow ramp region of the driver gate as well as in the extracted parasitic interconnect networks. Input slew is found to be a dominant factor affecting clock delay sensitivity. In addition, we use indirect on-chip electron beam probing to confirm that the simulated clock delays are in reasonable agreement with the measured delays     

Measurement and modeling of on-chip transmission line effects in a400 MHz microprocessor

On-chip interconnect delays are becoming an increasingly important factor for high-performance microprocessors. Consequently, critical on-chip wiring must be carefully optimized to reduce and control interconnect delays, and accurate interconnect modeling has become more important. This paper shows the importance of including transmission line effects in interconnect modeling of the on-chip clock distribution of a 400 MHz CMOS microprocessor. Measurements of clock waveforms on the microprocessor showing 30 ps skew were made using an electron beam prober. Waveforms from a test chip are also shown to demonstrate the importance of transmission line effects     

Effects of inductance on the propagation delay and repeaterinsertion in VLSI circuits

A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 35% for current on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase. On-chip inductance is therefore expected to have a profound effect on traditional high-performance integrated circuit (IC) design methodologies. The closed-form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed-form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. RC models can create errors of up to 30% in the total propagation delay of a repeater system as compared to the optimal delay if inductance is considered. The error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling. Thus, the importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale     

非直角互连——布线技术发展的新趋势

由于集成电路制造工艺的不断提高 ,集成电路的设计规模遵循Moore定律持续向前发展 ,并出现了系统级芯片 (SOC)这一新的集成电路设计概念 .同时遇到的困难之一是互连线成为影响电路性能的决定因素 :芯片速度变慢、功耗增大、噪声干扰加剧 .若采用以往基于直角互连结构的基础模型进行互连线性能的优化 ,其能力受到限制 .于是 ,人们试图采用其他互连结构作为突破途径 ,以实现高性能的集成电路 .在这种技术需求与目前工艺支持的背景下 ,从 2 0世纪 90年代初出现的关于非直角互连的零散的、试探性的研究 ,将成为国际上布线领域新的热点研究方向 .     

On-chip characterization of interconnect parameters and time delayin 0.18 μm CMOS technology for ULSI circuit applications

A real time, on-chip characterization technique is presented for extracting the interconnect parameters and for determining the associated time delays for ULSI circuit applications. To demonstrate the method, test chips were fabricated in both 0.25 and 0.18 μm CMOS technologies, using state of the art process technologies. Results obtained in these two cases are compared and the changing trends and issues for interconnect parameters in making the transition from the 0.25 μm to the 0.18 μm technologies are discussed. A completed look-up table in conjunction with a working analytic expression of the time delay enables accurate modeling and optimization of interconnect parameters and time delays for a given specification of chip performance