VLSI与超纯硅材料

通过VLSI与超纯硅材料关系的论述，阐明了我国VLSI的发展急需解决高质量的超纯硅材料。提高大直径硅片的平整度；氧、碳含量稳定、均匀、可控；提高微区电阻率的均匀性；硅表面洁净、具有密封、屏蔽的防静电包装技术是当今硅材料发展的主攻课题。超纯硅材料的完美结晶特性和超精度加工技术水平取决于基础材料（化学试剂、高纯气体）的高纯度、小颗粒和低杂质含量的控制。     

硼离子注入退火过程对表面迁移率及薄层电阻的影响

本文利用与退火条件有关的离子注入杂质分布,得到了在硅中硼离子注入退火条件对载流子表面迁移率的影响。还得到了硼离子注入薄层电阻与注入条件及退火情况的关系。在这些关系中,注入剂量对迁移率及薄层电阻有最主要的影响。这些结果可在设计和制造VLSI中用以确定工艺条件。     

退火直拉硅中小于10nm的微缺陷

直拉硅中氧的浓度高达10~(18)at/cm~3,在器件工艺的热处理过程中,会产生氧的沉淀或形成硅氧团(SiO_x)。经过650℃下较长时间热处理所形成的与氧有关的缺陷,在表观上起施主陷阱中心的作用,引起硅片电阻率的漂移,影响器件的阈值电压,降低VLSI的成品率。近些年来,人们越来越注重研究施主陷阱的产生及其微观结构。这一方面是由于VLSI生产向低温工艺发展后,不可避免地会遇到施主陷阱问题,另一方面,新近的研究表明,在较低温度退火中形成的施主陷阱或硅氧团,在器件的后续工艺中,会成为氧进一步沉淀的核心,促进了更为复杂的沉淀物一位错络合物(PDC)的形成。因此研究在较低温度(例如650℃左右)热处理所形成的微缺陷的性质、结构及其它杂质对它生成的影响,无疑对弄清硅中与氧有关施主陷阱的本质,对改善用于VLSI器件的材料性能,都会具有十分重要意义的。     

离子探针分析锑化铟器件表面沾污

本文描述用离子探针显微分析法研究锑化铟器件表面沽污的情况。研究发现:各工艺过程中采用的容器、化学试剂、去离子水及工作环境,都是杂质沽污的主要来源。离子探针显微分析法促进了工艺的改进,使阳极氧化工序的沾污杂质由13种减少到7种,Na、K和Ca杂质的含量也大大下降。中测腐蚀工序沾污杂质由11～13种减少到4～6种。器件表面沾污的减少使器件性能得到改善,φ2mm器件的阻抗由10kΩ提高到60～70kΩ,成品率也提高一倍左右。     

高纯外延GaAs中浅施主杂质的光热电离谱研究

利用光热电离谱技术研究了4．5K下高纯n－GaAs外延材料的远红外光电导响应借．给出CPE法和VPE法生长的高纯GaAs材料残留浅施主杂质分别是S、Sn和Sn、P等杂质．实验结果表明本所高纯GaAs组采用的LPE生长技术能有效抑制杂质St和Sn的沾污．     

等离子体二氧化硅的制备及特性

<正> 一、 引言 低温能避免高温引起的杂质再分布,杂质表面耗尽,“鸟嘴”结构形成,以及硅片翘曲和热诱生缺陷等,保证高密度IC的实现。硅的低温氧化,是VLSI制作中尚未解决的重要课题,因此引起了人们很大关注。本工作采用低温等离子体技术,研究了900℃以下硅的等离子体氧化,探讨了膜的生长机理和规律,膜的性质与工艺条件的关系。     

硅片处理的新进展

仙童半导体公司的工程师们宣称,由于使用了专门的化学试剂循环处理装置,目前他们在化学试剂方面的花费下降,而且使湿法工艺中的颗粒沾污得到改善。这种装置是由加利福尼亚州Oceansi-de的Athens公司制造的。这家公司为其命名为Piranha Piranha系统。用该装置提纯之后,每毫升硫酸中0.5微米以上的颗粒还不到10个。该系统采用一种蒸馏技术对化学试剂进行提纯,并且,采用微机控制技术对痕量化学杂质和颗粒数量实施连续的监控。     

塞曼效应石墨炉原子吸收法在碲镉汞材料制备中的应用

本文用塞曼效应石墨炉原子吸收光谱分析法(ZAAS)对淬火-固态再结晶制备Hg_(1-x)Cd_xTe材料的工艺进行了研究,探讨并建立了高纯原料(Te、Cd)、制备晶体的容器(石英、玻璃)及Hg_(1-x)Cd_xTe材料中杂质分析方法。结果表明:ZAAS法是Hg_(1-x)Cd_xTe材料研究中一种重要的痕量分析手段。     

基于亚沸蒸馏的高纯溴提纯工艺改进

由于碲镉汞薄膜材料中杂质的含量对红外探测器件性能的影响很大,因此对衬底表面加工过程中使用的溴甲醇腐蚀液的纯度提出了非常高的要求.采用改进的亚沸蒸馏装置对高纯溴溶液进行了进一步的蒸馏提纯,并根据等离子质谱分析仪(ICP-MS)的杂质含量测试结果对实验条件进行了优化.结果 表明,该方法可以进一步降低提纯溴中的杂质含量,进而...     

氨水、双氧水转国产化应用

化学试剂是微电子制造工艺中清洗工艺的重要材料。由于微电子制造对化学试剂的各项要求极高,在该制造业发展初期,国内中高端生产线以进口化学试剂为主。随着国内原材料厂商工艺能力的提高,各种国产化学试剂正逐步取代进口试剂。由于微电子制造对质量的要求,化学试剂国产化需要一个较长的过程。通过国产与进口氨水及双氧水在试剂纯度、单项工艺指标及能力、使用后的产品性能等方面作对比,得到了国产试剂可以取代进口试剂的结论。     

Optimizing gettering conditions for VLSI chips using simple yieldmodel

Conditions of an effective gettering procedure for VLSI processing are investigated by means of analytical simulation. The effectiveness of a gettering procedure is judged from the VLSI yield when the density of heavy metal impurities and gettering capability are varied over a wide range. It is found that the VLSI yield is seriously degraded by the negative effects of gettering, namely, wafer warpage and dislocation propagation from a gettering site region to a device area. It is seen that gettering effects are profitable in VLSI processes only when the density of heavy metal impurity to be removed is not too high     

控制超大规模集成电路用水中的溶解氧和总有机碳浓度的研究

本文介绍了溶解氧(DO)以及总有机碳(TOC)对超大规模集成电路(ULSI)用水的污染,并列出了高纯水中TOC的浓度与栅氧化缺陷密度的关系数据.研究了影响水中DO的因素以及用各种方法降低TOC的比较,本文设计了用脱氧膜接触器,降低高纯水中的溶解氧.结合用双级反渗透(RO)及电脱盐(EDI) 再加上185nm紫外光照射高纯水,使高纯水中的溶解氧和TOC分别降至0.6μg/L和0.7μg/L,并用键能理论解释了185nm紫外降低TOC的机理.     

降低超大规模集成电路用高纯水中总有机碳的能量传递光化学模型

本文提出用185nm紫外线降低高纯水中总有机碳(TOC)的能量传递光化学模型.计算了水的流量、TOC的浓度、照射腔的尺寸与所需紫外光能量的关系,从而解决了在工程设计中185nm紫外灯的选择和计算方法.根据理论计算出的结果和实验十分一致,证实了本模型的正确性.使高纯水中的TOC由4200μg/l 降至0.3μg/l,是目前国内外高纯水中TOC浓度的最好水平.     

用两种不同的紫外光照射高纯水和废水降低总有机碳的比较

本文研究了用185nm UV和254nm UV照射方法降低高纯水中的TOC和废水中五种有机物的TOC,用185nm UV能有效地将高纯水中的TOC降低到(≤0.3μg/L),满足超大规模集成电路用水的需要.同时研究了用两种不同的紫外线185nmUV和 254nmUV,对比照射降低水中难生物降解的有毒、有害的五种有机污染物(二苯甲酮、孔雀石绿、对氯苯酚(4-CP)、对硝基苯酚(4-NP)和罗丹明B(Rh B)的TOC,结果表明185nmUV,比254nmUV,降低有机物的TOC好得多.有利于环境保护.     

Handling multimedia information with VLSI

Identifies the basic technological components of multimedia communications. Among these technologies, multimedia processing and transmission already benefit heavily from VLSI advances. in fact, these two technologies could not have matured without special-purpose VLSI chips. We have examined basic processing required in these technologies and some VLSI architectures. The focus has been on standard-compliant VLSI chips, because the eventual goal of communications is to allow everyone to reach others without constraints. There are still a number of evolving standards, which means that we might witness yet another wave of VLSI chips for multimedia communications     

Influence of initial wafer cleanliness on metal removal efficiencyin immersion SC-1 cleaning: limitation of immersion-type wet cleaning

When contaminated silicon wafers are immersed in an ultra-pure cleaning solution of an NH₄OH/H₂O₂/H ₂O mixture known as the RCA Standard Clean 1 (SC-1), in which the impurity concentration is negligibly low, the level of wafer-surface metallic contamination after the cleaning treatment depends on the amount of metallic impurities brought into the solution by the to-be-cleaned wafers themselves. Even if the chemicals are disposed of after each wafer cleaning, the surface metallic contamination is still dominated by the amount of impurities brought into the fresh solution by the wafers themselves. In the past, purer chemicals have been sought to improve metal removal efficiency, but after reasonably purer chemicals are obtained the efficiency is not governed by the initial chemical purity but by the initial wafer cleanliness. Because of this, scrubbing of dirty wafers-both the backand front-surfaces-before immersion-type wet cleaning is recommended. However, to meet future stricter wafer cleanliness requirements, new cleaning methods in which fresh chemicals are continuously supplied, such as single-wafer spin cleaning, will have to be employed     

Impurity segregation in horizontal bridgman grown cadmium zinc telluride

Segregation of impurities that cause low infrared (IR) transmission in horizontal Bridgman (HB) grown cadmium zinc telluride (CdZnTe) has been investigated. This segregation was characterized using IR transmission, glow discharge mass spectrometry (GDMS), and IR microscopy measurements. In the studied HB CdZnTe ingots, impurity segregation causes the formation of a small volume in the last-to-freeze portion of the ingot that has high impurity concentration and low IR transmission. Outside this region the concentration of impurities is low and the material shows high IR transmission. The region is visibly observable on CdZnTe slices and appears as a dark area with a sharp boundary. Free carrier absorption within the region causes a decrease in IR transmission with an increase in wavelength and correlates with the concentration of lithium and sodium impurities. Impurity segregation in HB ingots is described and explains the location of the high impurity region. The location of the visible boundary correlates with the first measurable change in IR transmission as compared to the high IR transmission of the surrounding material and supports the hypothesis that the darkening of the region is due to a reduction of the reflectivity due to free carrier absorption. With a properly controlled cool-down recipe, the impurities segregated in the last-to-freeze section of the ingots can remain localized, thereby improving the purity of the remaining bulk of the material.     

Growth and characterization of Indium-doped silicon for extrinsic IR detectors

Experimental growth and characterization studies of extrinsic indium-doped silicon for 3- to 5-µm focal-plane array applications have been carried out. Large, 2- and 3-in-diameter, -oriented indium-doped silicon crystals were prepared by Czochralski crystal pulling. The growth conditions affecting crystalline perfection, maximum dopant concentration and uniformity, and the residual shallow acceptor impurity content in grown crystals were investigated. In addition, effects of carbon content on the concentration of the 0.11-eV defect level in indium-doped silicon have been studied. The results demonstrate that near dislocation-free crystals containing indium concentrations up to 5 × 10¹⁷cm^-3can be achieved at low growth rates to delay the onset of constitutional supercooling, while unwanted boron and aluminum impurities can be maintained at levels approaching 1 × 10¹³cm^-3, when high purity synthetic-quartz crucibles are utilized to minimize melt contamination. Phosphorus-compensated indium-doped infrared (IR) detector performance and test photodetectors show peak responsivities up to 10 A/W (5.9 µm, 1000 V/cm, 50 K). Monolithic CCD test structures fabricated on Czochralski indium-doped silicon substrates show lower responsivities, however, due to detrimental effects of high-temperature CCD processing.     

Model for yield and manufacturing prediction on VLSI designs foradvanced technologies, mixed circuitry, and memories

A yield model has been developed and validated for use in optimizing VLSI floorplanning in next generation products. The model successfully predicts yields and costs on a variety of products in CMOS, bipolar, and BiCMOS process flows from low cost DIP's and QFP's to more complex PGAs and flip chip package solutions. This paper discusses how the model was developed for use in evaluating the viability of next generation VLSI solutions. The model takes into account variables such as layout sensitivity, circuit redundancy, and learning curves in wafer, assembly, and test processing in determining the total manufacturing cost