伪码测距中码跟踪环的FPGA实现

码跟踪环的设计是伪码/载波相位联合测距系统的一个关键环节.分析了伪码跟踪环路的结构,利用查表法、二阶环路分别对NCO和环路滤波器等关键部分进行了设计,并给出了相应的电路结构.系统仿真与FPAG片上测试结果表明,实现了伪码准确、实时跟踪,跟踪到的伪码相位误差小于载波相位的周期长,设计的跟踪环具有一定工程应用价值.     

扩频通信系统的伪码跟踪技术研究

同步系统是无线电导航系统中的关键部分。而伪码跟踪技术又是同步的关键技术。文中对延迟锁定环（DLL）系统理论进行深入研究,建立了延迟锁定环（DLL）的数学模型,通过仿真对伪码跟踪技术进行了定性的探讨,在仿真的基础上使用Insight公司的FPGA开发系统,用测试电路实测了伪码跟踪的性能。     

一种用于伪码测距的频域非线性估计算法

针对伪码测距领域常用的脉冲计数法所需系统工作时钟过高,以及码环抖动对测量精度影响较大的问题,提出了一种可以准确的测量出接收伪码同步误差的频域非线性估计算法。仿真结果表明,该算法可以以较低的处理时钟频率获得较小的测量误差,且测量精度对码环跟踪的抖动不敏感。     

非相干扩频接收机伪码跟踪环设计及FPGA实现

伪码跟踪环的设计是实现非相干扩频接收机的关键环节。为了实现非相干扩频接收机的伪码跟踪,设计了能量归一化的延迟锁定跟踪环,给出了环路的实现结构及环路参数的计算方法。分析了非相干扩频的特点,指出环路设计的关键点,在此基础上阐述了码环鉴别器、环路滤波器、超前滞后码发生器的设计及实现方法,并给出一套具体的实现参数。Modelsim仿真结果及FPGA实测数据表明所设计的环路能对伪码进行精确跟踪。     

基于直扩的伪码频偏估计

提出了一种基于直接序列扩频信号的伪码频偏估计方法。介绍了解扩原理,包括中频采样、数字下变频、相关累积、伪码频率估计、环路滤波和伪码跟踪等。分析了伪码频偏估计的具体方法:伪码搜索的方法实现伪码大频偏的粗略估计;用锁相环实现伪码的同步;对锁相环的相位误差的提取,环路滤波器的结构和参数给出了具体的实现方法和表达式,并对环路等效噪声带宽的选取及其影响进行了讨论。     

扩频调制的伪码跟踪技术分析

在直接序列扩频传输系统中,接收端通常利用匹配滤波器实现扩频信号的初始同步,利用伪码跟踪环实现本地码字对其相位的精确跟踪。伪码跟踪的准确性直接影响解扩的性能。伪码跟踪中采用归一化的鉴相算法,通过合理的环路参数、相干累加长度和非相干累加次数设计,可以提高伪码跟踪的准确性。针对直接序列扩频信号,通过理论和仿真分析得到了码跟踪环中的相干累加长度和非相干累加次数这2个关键参数与载波频差、扩频比以及误码率之间的关系,可以为扩频码定时跟踪的设计提供依据。     

伪噪声码产生新方法

伪噪声编码通信一直是通信技术的主流，但是同时具有良好的自相关性和互相关性的伪噪声码族并不很多。针对这一问题，提出了一种新的伪噪声码的产生方法。通过理论和仿真分析。证明了它具有良好的相关性，是一种实用性很强的伪码序列。     

数字式可编程伪码发生器

介绍一种数字式可编程伪码发生器,其速率和级数均可通过软件控制;还给出一种验证多级数伪码序列正确性的方法。     

航天测控系统中伪码测距精度分析

伪码测距以其较长的无模糊距离和较高的测量精度的显著优势,广泛应用于航天测控系统中。依据伪码测量原理,并结合工程经验数据,通过分析星地伪码测距系统的具体实现结构,研究了系统中各误差源引入的随机误差和系统误差,其中以星地伪码测距设备引入的测量误差作为重点,并对主要误差源伪码跟踪环路进行了较为深入的剖析。     

基于FPGA的伪码测距电路的设计与实现

介绍了基于伪码测距的某定位系统的设计方案，简要分析了伪码测距的原理，研究了和FPGA实现伪码的捕获与跟踪的方法。     

直扩系统PN码捕获和跟踪的FPGA实现

在数字匹配滤波器和超前滞后鉴相环路的理论基础上,采用VHDL编程,在FPGA芯片上实现PN码捕获和跟踪的电路。详细讨论了各电路模块的设计实现方法。完成电路的仿真验证,给出了仿真波形。结果表明电路工作正常可靠,系统扩展方便灵活,满足设计要求。     

Dual-channel Method for Fast Long PN-code Acquisition

Long PN-code acquisition is a difficult and time-consuming task due to long code period.To accelerate acquisition,folding methods like XFAST are widely used.In highdynamic environment however,the application of those methods are largely restricted due to nonnegligible residual frequency.This paper proposes a new dual-channel method for fast acquisition of long PN-code.In the proposed method,both non-overlapping local PNcode blocks are employed to correlate with input sample block;the detection process is eased through finding the maximum value among correlation results and verification is made with all the full and partial peaks taken into account.False alarm probabilities from analysis of the verification process are derived.Both theoretical and Monte Carlo simulations reveal that,with respect to acquisition probability and mean acquisition time under the same false alarm rate,dual-channel method has advantage over zero-padding and XFAST based folding methods under certain false alarm probabilities.     

梳形滤波器在自干扰载波下短周期伪码截获中的应用

伪码的截获是无线电侦察和导航战中的难题。针对通信侦察等领域的需要,将梳形滤波器应用于自干扰载波下短周期伪码的截获中。仿真结果表明,对于自干扰载波中结构未知的扩频伪码,仅利用其周期性,通过梳形滤波器能够快速截获伪码,计算简单,易于实现。     

Analysis of SCCL as a PN-code tracking loop

We introduce the application of SCCL that is based on sample-correlate-choose-largest procedure as a coherent baseband PN-code tracking loop applying biphase-level signals. Three adjacent estimates are formed by correlating the samples of the baseband waveform for each bit. We choose the corresponding timing (phase) of the estimate with the largest magnitude as the current correct timing (phase) and update it for each bit. Only one summation circuit is required due to the digital realization of the SCCL. The correlation properties of the samples from maximum length codes using the biphase-level signal set are investigated. Tracking performance is theoretically analyzed in both steady-state and transient conditions via a finite-state Markov chain model. The numerical results demonstrate strong PN-code tracking characteristics of SCCL     

某型伪码测距雷达的数字AGC设计

论述了某航天器伪码测距雷达接收机外部AGC的设计原理和具体实现,并重点讨论了如何根据射频前端的输出来设计全数字AGC,来扩展接收机的动态范围.该文的讨论对于DS-SS（扩展频谱数字）接收机和伪码测距雷达接收机的数字AGC设计有参考意义.     

Resynchronising delay-locked loop

The delay-locked loop (DLL) is a device that is often used for PN-code tracking to synchronise direct sequence spread spectrum (DS-SS) systems. A DLL with resynchronising capability, which is more robust against loss of lock, is presented. The new scheme has two modes: a normal tracking mode and a resynchronising mode. The structure of the new loop and its function are described     

双通道长周期伪码快速捕获方法(英文)

Long PN-code acquisition is a difficult and time-consuming task due to long code period.To accelerate acquisition,folding methods like XFAST are widely used.In highdynamic environment however,the application of those methods are largely restricted due to nonnegligible residual frequency.This paper proposes a new dual-channel method for fast acquisition of long PN-code.In the proposed method,both non-overlapping local PNcode blocks are employed to correlate with input sample block;the detection process is eased through finding the maximum value among correlation results and verification is made with all the full and partial peaks taken into account.False alarm probabilities from analysis of the verification process are derived.Both theoretical and Monte Carlo simulations reveal that,with respect to acquisition probability and mean acquisition time under the same false alarm rate,dual-channel method has advantage over zero-padding and XFAST based folding methods under certain false alarm probabilities.     

The Generalized Delay-Locked Loop

The delay-locked loop (DLL) is a synchronization device that is widely used for PN-code tracking in spread spectrum systems. The error detector characteristic (S-curve) of the DLL has a major impact on the performance. Using more than two correlators will extend the tracking range of the S-curve. The Generalized DLL (GenDLL) theory provides a concept to analyze a large class of DLL configurations including the classical DLL. The focus of the performance criteria is on tracking jitter and the mean time to lose lock (MTLL). It is shown that the MTLL can be considerably improved by using extended S-curves. However, the tracking jitter is increased by additional correlators. The tradeoff between the two criteria is explained. With the GenDLL theory loop configurations can be designed having both low tracking jitter and high loop robustness against loss of lock.     

Reduced complexity delay-locked loop

In spread spectrum synchronisation the delay-locked loop (DLL) is widely used for PN-code tracking. A new DLL configuration using only one correlator to generate the timing error signal is presented. This reduces the hardware complexity of the code synchronisation. The structure of the new loop is described and performance results are shown     

Third-order delay-locked loop: mean time to lose lock and optimalparameters

A systematic approximation for the mean time to lose lock (MTLL) of a coherent third-order PN-code tracking loop has been derived. Such loops are essential in various spread spectrum systems (Global Positioning System, for example). The computation of the MTLL is based on the singular perturbation method. The application of this method to the coherent delay-locked loop (DLL) yields an approximate expression for the MTLL. Therefore, with the proposed loop model the authors are able to analyze this third-order system at a level that gives a well understanding of the nonlinear loop behavior and the exit phenomenon. The influence of a loop offset due to an acceleration rate (jerk) between transmitter and receiver on the optimal filter parameters is described by comparing MTLL and tracking error performance. As intuitively might be expected it turns out that acceleration rate and code rate are exchangeable in the sense that a lower code rate allows a higher acceleration rate (and vice versa) for the same signal-to-noise ratio in order to maintain the same performance. In a case study, GPS code tracking for objects with high jerk is briefly discussed