金属纳米晶快闪存储器研究进展

金属纳米晶具有态密度高、费米能级选择范围广以及无多维载流子限制效应等优越性,预示着金属纳米晶快闪存储器在下一代闪存器件中具有很好的应用前景。从金属纳米晶存储器的工作原理、纳米晶的制备方法、以及新型介质材料和电荷俘获层结构等方面,对金属纳米晶存储器近年来的研究进展进行了总结。     

基于硅纳米晶的非挥发存储器制备与存储特性

硅纳米晶非挥发存储器由于其卓越的性能以及与传统工艺的高度兼容性,近来引起高度关注。采用两步低压化学气相淀积(LPCVD)生长方式制备硅纳米晶(Si-NC),该方法所制备的硅纳米晶具有密度高、可控性好的特点,且完全兼容于传统CMOS工艺。在此基础上制作四端硅纳米晶非挥发存储器,该器件展示出良好的存储特性,包括10 V操作电压下快速地擦写,数据保持特性的显著提高,以及在105次擦写周期以后阈值电压(Vt)飘移低于10%的良好耐受性。该器件在未来高性能非挥发存储器应用上极具潜质。     

包含双层半导体和金属纳米晶MOS电容的存储特性

制备了包含双层半导体和金属纳米晶的MOS电容结构,研究了其在非挥发性存储器领域的应用。利用真空电子束蒸发技术,在二氧化硅介质中得到了半导体硅纳米晶和金属镍纳米晶。与包含单层纳米晶的MOS电容相比,这种包含双层异质纳米晶的MOS电容显示出更大的存储能力,且保留性能得到改善。说明顶层的金属纳米晶作为一层额外的电荷俘获层可以通过直接隧穿机制进一步延长保留时间和提高平带电压漂移量。     

纳米晶存储特性的研究

常温下硅纳米晶构成的MOSFET存储器具有低压、低功耗、体积小、高剂量和快速读写等优良特性,在ULSI中有重要的应用前景.它是当前ULSI研究中的一项热门专题,在国外一些著名刊物上屡见报道.本文介绍了这种器件的存储特性及其机理与最新研究进展.     

硅纳米晶存储器的耐受性研究

首先介绍了硅纳米晶粒的制备工艺以及硅纳米晶存储器件的基本特性。接着重点探讨了硅纳米晶存储器耐久性退化的物理机制,发现应力引起的界面陷阱是耐受性退化的主要原因。随后,同时采用多种分析手段,如电荷泵法和CV曲线分析法对界面陷阱的退化机理进行了更深入细致的研究。从界面陷阱在禁带中的能级分布中发现,相较于未施加应力时界面陷阱的双峰分布,施加应力后产生了新的Pb1中心的双峰。最后,分别从降低擦写电压和对载流子预热的角度提出了三种新的编程方法,有效提高了硅纳米晶存储器件的耐受性。     

纳米硅单电子存储器研究进展

纳米硅单电子存储器与现有微电子存储器相比,由于具有更低的功耗、更快的开关速度、更高的存储密度以及更高的集成度,被认为是在非挥发性存储器的研究中最有可能成为未来快闪存储器的候选者之一.文章论述了纳米硅单电子存储器的工作原理、研究现状及发展趋势.     

可嵌入式应用的新型2T结构硅纳米晶存储器

本文研究了2T硅纳米晶非挥发存储器性能和可靠性。存储单元可获得良好性能,包括低压操作下快速的擦写速度,卓越的数据保持特性（保持10年）,良好的耐受性（10k次擦写周期以后小于10%的阈值电压飘移）。数据表明了此器件在未来嵌入式非挥发存储应用的可能性。     

基于锗硅异质纳米晶的非易失浮栅存储器的存储特性

利用自组织生长和选择化学刻蚀方法在超薄SiO2隧穿氧化层上制备了渐变锗硅异质纳米晶,并通过电容.电压特性和电容-时间特性研究了该纳米结构浮栅存储器的存储特性.测试结果表明,该异质纳米晶非易失浮栅存储器具有良好的空穴存储特性,这是由于渐变锗硅异质纳米晶中Ge的价带高于Si的价带形成了复合势垒,空穴有效地存储在复合势垒的Ge的一侧.     

基于锗硅异质纳米晶的非易失浮栅存储器的存储特性

利用自组织生长和选择化学刻蚀方法在超薄SiO2隧穿氧化层上制备了渐变锗硅异质纳米晶,并通过电容.电压特性和电容-时间特性研究了该纳米结构浮栅存储器的存储特性.测试结果表明,该异质纳米晶非易失浮栅存储器具有良好的空穴存储特性,这是由于渐变锗硅异质纳米晶中Ge的价带高于Si的价带形成了复合势垒,空穴有效地存储在复合势垒的Ge的一侧.     

An Ultrafast Nonvolatile Memory with Low Operation Voltage for High-Speed and Low-Power Applications

Memory plays a vital role in modern information society. High-speed and low-power nonvolatile memory is urgently demanded in the era of big data. However, ultrafast nonvolatile memory with nanosecond-timescale operation speed and long-term retention is still unavailable. Herein, an ultrafast nonvolatile memory based on van der Waals heterostructure is proposed, where a charge-trapping material, graphdiyne (GDY), serves as the charge-trapping layer. With the band-engineered heterostructure and excellent charge-trapping capability of GDY, charges are directly injected into the GDY layer and are persistently captured by the trapping sites in GDY, which result in an ultrafast writing speed (8 ns), a low operation voltage (30 mV), and a long retention time (over 10⁴ s). Moreover, a high on/off ratio of 10⁶ is demonstrated by this memory, which enables the achievement of multibit storage with 6 discrete storage levels. This device fills the blank of ultrafast nonvolatile memory technology, which makes it a promising candidate for next-generation high-speed and low-power-consumption nonvolatile memory.     

SONOS非挥发性存储器件的研究进展

随着非挥发性存储器件的尺寸持续缩小,SONOS结构存储器件又重新被重视.简单介绍超短栅长SONOS器件和2 bit SONOS器件,重点介绍改进氮化硅层和应用high-K材料,来改善SONOS器件性能的研究.认为只要解决high-K材料在非挥发性存储器件中的应用,具有好的发展前景.     

Memory characteristics of an MOS capacitor structure with double-layer semiconductor and metal heterogeneous nanocrystals

An MOS (metal oxide semiconductor) capacitor structure with double-layer heterogeneous nanocrystals consisting of semiconductor and metal embedded in a gate oxide for nonvolatile memory applications has been fabricated and characterized. By combining vacuum electron-beam co-evaporated Si nanocrystals and self-assembled Ni nanocrystals in a SiO_2 matrix, an MOS capacitor with double-layer heterogeneous nanocrystals can have larger charge storage capacity and improved retention characteristics compared to one with single-layer nanocrystals. The upper metal nanocrystals as an additional charge trap layer enable the direct tunneling mechanism to enhance the flat voltage shift and prolong the retention time.     

Au纳米晶MIS结构存储性能研究

从器件结构和能带的角度分析了提高非易失性存储器性能的可能途径,建立了纳米晶浮栅结构的存储模型,并在模型中考虑了量子限制效应对纳米晶存储性能的影响.基于模型计算,分析了纳米晶材料、高k隧穿介质材料及其厚度对纳米晶浮栅结构存储性能的影响.同时,制作了MIS结构(Si/ZrO2/Au Ncs/SiO2/Al)的存储单元,针对该存储单元的电荷存储能力和电荷保持特性进行测试,并对测试结果进行分析.     

High Performance Flexible Nonvolatile Memory Based on Vertical Organic Thin Film Transistor

Flexible floating‐gate organic transistor memory (FGOTM) is a potential candidate for emerging memory technologies. Unfortunately, conventional planar FGOTM suffers from weak driving ability and insufficient mechanical flexibility, which limits its commercial application. In this work, a novel flexible vertical FGOTM (VFGOTM) is reported. Benefitting from new vertical architecture, VFGOTM provides ultrashort channel length to afford an extremely high current density. Meanwhile, VFGOTM devices exhibit excellent memory performance and outstanding retention property. The memory properties of VFGOTM devices are comparable or even better than traditional planar FGOTM and much better than the reported organic nonvolatile memory with vertical transistor structures. More importantly, organic nonvolatile memory with vertical transistor structures is investigated for the first time on a flexible substrate. The results show that VFGOTM architecture allows vertical current flow across the channel layer to effectively eliminate the effect of mechanical bending during current transport, which significantly improves the mechanical stability of the flexible VFGOTM. Hence, with a combination of excellent driving ability, memory performance, and mechanical stability, VFGOTM devices meet the practical requirements for high performance memory applications, which have great potential for the application in a wide range of flexible and wearable electronics.     

Disk Triboelectric Nanogenerator-Based Nonvolatile Memory toward Smart Identification System

With the rapid advancement of the Internet of things (IoT), security issues of the IoT are emerging because the wireless networks for conventional IoT are easily exposed to hacking. By storing the critical data in a physically separate space, these issues can be suppressed. The nonvolatile memory (NVM) is an attractive solution because the stored data are not erased even after turning off the power. However, the NVM consumes the power for operating and remaining data are exposed to attack. Hence, NVM with high security and low power operation is highly required for IoT platforms. Herein, a disk triboelectric nanogenerator-based NVM (DTNVM) is developed. The DTNVM can be operated with low power because the reading process of stored data is conducted with triboelectricity. Since the ternary system is adopted, 23 to 119 trits can be stored at the DTNVM by changing the sampling time. The identification information is stored at the DTNVM and 91.3% of consistency of the data with a range of 10% tolerance is recorded as result of the reading. Based on the result, the DTNVM is expected to be utilized in the near future as a next-generation NVM and for safe identification systems at the IoT.     

Introducing pinMOS Memory: A Novel,Nonvolatile Organic Memory Device

In recent decades, organic memory devices have been researched intensely and they can, among other application scenarios, play an important role in the vision of an internet of things. Most studies concentrate on storing charges in electronic traps or nanoparticles while memory types where the information is stored in the local charge up of an integrated capacitance and presented by capacitance received far less attention. Here, a new type of programmable organic capacitive memory called p‐i‐n‐metal‐oxide‐semiconductor (pinMOS) memory is demonstrated with the possibility to store multiple states. Another attractive property is that this simple, diode‐based pinMOS memory can be written as well as read electrically and optically. The pinMOS memory device shows excellent repeatability, an endurance of more than 10⁴ write‐read‐erase‐read cycles, and currently already over 24 h retention time. The working mechanism of the pinMOS memory under dynamic and steady‐state operations is investigated to identify further optimization steps. The results reveal that the pinMOS memory principle is promising as a reliable capacitive memory device for future applications in electronic and photonic circuits like in neuromorphic computing or visual memory systems.     

Room‐Temperature Nonvolatile Memory Based on a Single‐Phase Multiferroic Hexaferrite

The cross‐coupling between electric polarization and magnetization in multiferroic materials provides a great potential for creating next‐generation memory devices. Current studies on magnetoelectric (ME) applications mainly focus on ferromagnetic/ferroelectric heterostructures because single‐phase multiferroics with strong magnetoelectric coupling at room temperature are still very rare. Here a type of nonvolatile memory device is presented solely based on a single‐phase multiferroic hexaferrite Sr₃Co₂Fe₂₄O₄₁ which exhibits nonlinear magnetoelectric effects at room temperature. The principle is to store binary information by employing the states (magnitude and sign) of the first‐order and the second‐order magnetoelectric coefficients (α and β), instead of using magnetization, electric polarization, and resistance. The experiments demonstrate repeatable nonvolatile switch of α and β by applying pulsed electric fields at room temperature, respectively. Such kind of memory device using single‐phase multiferroics paves a pathway toward practical applications of spin‐driven multiferroics.     

Nonvolatile Ferroelectric Memory Effect in Ultrathin α‐In2Se3

High‐density memory is integral in solid‐state electronics. 2D ferroelectrics offer a new platform for developing ultrathin electronic devices with nonvolatile functionality. Recent experiments on layered α‐In₂Se₃ confirm its room‐temperature out‐of‐plane ferroelectricity under ambient conditions. Here, a nonvolatile memory effect in a hybrid 2D ferroelectric field‐effect transistor (FeFET) made of ultrathin α‐In₂Se₃ and graphene is demonstrated. The resistance of the graphene channel in the FeFET is effectively controllable and retentive due to the electrostatic doping, which stems from the electric polarization of the ferroelectric α‐In₂Se₃. The electronic logic bit can be represented and stored with different orientations of electric dipoles in the top‐gate ferroelectric. The 2D FeFET can be randomly rewritten over more than 10⁵ cycles without losing the nonvolatility. The approach demonstrates a prototype of rewritable nonvolatile memory with ferroelectricity in van der Waals 2D materials.