二次静电放电仿真与实验研究

二次静电放电（secondary electrostatic discharge，SESD）是一种由一次静电放电引起的发生在仪器内部微小缝隙间的击穿放电现象，可对晶体管等很多元件造成破坏.文章首先搭建由静电放电模拟电路、二次放电模拟电路和电流靶电路组成的电路级仿真模型，初步探索SESD的波形，并与初始模型进行对比分析，验证已知的理论.其次基于实验研究与数据分析的方法，总结二次放电波形特点、峰值特性和时延特性.研究表明:二次放电电流峰值大于一次放电电流峰值，且受放电电压、放电时延等参数影响；二次放电的时延呈正态分布.这一研究结果符合并验证了目前对二次放电微观过程研究所得出的相关理论.     

静电放电模拟器电路建模分析

从实际的静电放电模拟器结构出发,根据接触放电时静电放电电流的主要特征,考虑到静电模拟器本身、连接线及回路电缆与地平面间产生的分布参数的影响,建立了一个新的静电放电模拟器等效电路模型,并用PSPICE软件对等效电路进行模拟分析,得到了与实测波形基本一致的电流波形.利用该模型讨论了各分布参数对放电电流的影响.结果表明:模拟器体电阻与地间的电感对电流波形影响不大,因此可以忽略,但其与地之间的分布电容对电流波形的低频段有重要影响;连接线分布参数对电流波形的第一峰值及波形光滑度都有影响;回路电缆分布参数主要影响了电流波形中第二个波峰峰值及其位置.     

电极移动速度效应的空气动力学分析

基于空气动力学原理解释了电极向靶运动过程中放电间隙形成局部低真空的机理.结合小间隙放电的双过程模型, 初步阐释了气体压强变化对放电间隙内部相关电参量的影响机理, 进而分析电极速度对放电参数的影响.基于我们团队自主研制的电极移动速度效应检测仪,进行反复实验, 对大量的试验数据进行仿真分析, 探索小间隙静电放电过程中放电参数对电极移动速度的依赖性.结果表明:电极移动速度与放电电流峰值、放电电流脉冲上升速度, 具有高度的正相关性; 与放电电流脉冲下降速度具有高度的负相关性.研究结果对于推进非接触静电放电测试标准的提出具有一定的参考意义.     

非接触静电放电测试低重复特性分析研究

基于自主研发的新型测试系统,对小间隙静电放电(Electrostatic Discharge,ESD)中电极移动速度和气体压强引起放电参数的低重复离散特性进行探讨.新型测试系统采用机电一体化设计,解决了带电体与受电体高速相向运动与避免强烈撞击损坏仪器的难题,并实现对多种影响因素的有效测量.用新型测试系统测量了气体压强变化和向放电靶移动电极速度等放电参数.静电放电模拟器移动距离控制在(10～40 cm)的范围.电极移动速度变化(v)为14 cm/s,则放电电流峰值改变(J)达到0.5A,空气压强变化对放电电流最高峰值的影响十分明显,压强变化(p)为0.06个大气压时,则峰值电流变化(D为0.5A,证明了电极移动速度和空气压强对放电参数产生的影响;对放电参数受电极移动速度和气体压强变化而出现显著差异的可能机制给出了初步分析.     

空气式静电放电的放电特性研究

利用简单的静电放电模拟测试装置对IEC标准规定的空气式静电放电的放电特性进行了研究.对放电电流的上升时间、峰值、自制金属半圆环上的耦合电压峰-峰值进行了测量,并用数字存储示波器记录了放电电流和耦合电压的波形.在较宽范围的电压电平和正负电压极性上进行了空气放电.对空气式静电放电的重复性、频谱特性和耦合特性等进行了分析.对空气式静电放电的放电特性研究可为静电放电抗扰度试验方法提供参考.     

3ctest静电发生器的等效电路建模

静电发生器的等效电路模型对相关静电抗扰度的仿真分析有直接影响。以国产的3ctest (EDS 16H)静电发生器为研究对象,提出一种基于静电发生器模块化的物理结构和阻抗参数测量结果,建立高精度电路模型的方法。介绍了静电发生器的典型物理结构,测量了各模块的阻抗特性,建立的等效电路考虑了接地电缆长短对阻抗参数的影响。根据标准2 Ω电流靶、50 Ω测试系统两种情况下测试的放电电流波形,拟合修正了等效电路参数,电路仿真结果与实测结果吻合较好。相关结果可以为实际的静电抗扰度测试提供参考。     

静电放电参数对电极速度的相关性与机理分析

同步测量了带电人体手握金属小棒电极放电电流的参数和电极运动速度.金属小棒电极与靶电极相撞时的速度对放电电流参数(放电电流峰值、放电电流时间变化率的峰值、火花放电的弧长)的影响,用统计软件SPSS进行了考察,获得了在不同人体电压情况下小棒电极运动速度与放电参数的相关系数.结果表明:充电电压为0.3kV时,放电参数与电极运动速度无关.充电电压为0.5kV及其以上电压时,电极运动速度与放电电流峰值、电流最大上升斜率有极强的正相关性;与放电火花弧长有极强的负相关性.电极向靶的快速接近改变放电间隙的空气压强,改变间隙两端的电场强度,从而引起放电参数的显著变化.     

空气静电放电的场路协同仿真研究

场路协同仿真方法可耦合场与路研究空气静电放电的非线性特征,有助于静电放电防护的进一步改进。本文基于CST仿真软件,首先通过静电放电发生器标准电流测试模型对场路协同仿真方法进行验证,然后利用该方法将静电放电发生器的3D全波模型和非线性电弧模型相结合,来探究放电电流随激励电压和放电弧长的变化关系。仿真结果表明：放电上升时间和峰值电流均随着激励电压和弧长指数变化,而小弧长情况下与接触放电类似接近线性变化;而结合实验中电弧长度随电压变化的特性,得出激励电压、电流峰值和上升时间的定量关系。仿真结果和文献中的实验结果相吻合,同时场路协同仿真可获得任一时刻的场分布信息,对电子设备的故障检测具有指导意义。     

电缆放电事件建模及其特性测试研究

参考人体行走电压的测试标准IEC 61340-4-5,搭建了电缆由线轴上绕下并在地板上拖拽积累的电压的测试系统,测量了六类非屏蔽网线的电压波形.基于实测电缆电压波形,提出了电缆电压的RC等效电路模型,并分析了模型参数对电缆电压时域波形的影响.进行了电缆充电后对金属靶的放电实验,测量了电缆放电事件的电流波形、瞬态电场和瞬态磁场波形,分析了电缆放电事件对电子设备的影响.根据测量的电缆放电事件的电流波形,对比了GJB 151B中CS 115电缆束注入脉冲激励传导敏感度的电流波形,二者电流波形有一定的相似性,但是对于较长电缆在电流的强度和宽度方面都会大于CS 115规定的限值.因此,提出了电缆放电事件的防护方法,并对相关标准的改进方面提出了初步建议.     

BP神经网络预测电极速度影响放电参数分析

文中结合小间隙放电的双过程模型,探讨电极移动引起放电场强和压强的变化对放电间隙内部相关因子的影响。文中同时利用BP神经网络预测分析电极移动速度对放电参数的影响。基于静电放电电极移动速度效应检测仪,不断改变电极移动速度,反复多次进行放电实验并统计试验数据。利用BP神经网络对已测实验数据进行训练、学习,从而预测不同速度与压强下对应的电流上升时间和峰值电流大小。实验结果表明,放电电流的上升时间与电极移动速度不存在相关性。根据新方法预测出的不同速度下的峰值电流和实际大小相比准确率更高。研究结果对探寻非接触式静电放电的规律和制定静电放电标准有一定的参考价值。     

一种3D堆叠集成电路中间绑定测试时间优化方案

中间绑定测试能够更早地检测出3D堆叠集成电路绑定过程引入的缺陷,但导致测试时间和测试功耗剧增.考虑测试TSV、测试管脚和测试功耗等约束条件,采用整数线性规划方法在不同的堆叠布局下优化中间绑定测试时间.与仅考虑绑定后测试不同,考虑中间绑定测试时,菱形结构和倒金字塔结构比金字塔结构测试时间分别减少4.39%和40.72%,测试TSV增加11.84%和52.24%,测试管脚减少10.87%和7.25%.在测试功耗约束下,金字塔结构的测试时间增加10.07%,而菱形结构和倒金字塔结构测试时间只增加4.34%和2.65%.实验结果表明,菱形结构和倒金字塔结构比金字塔结构更具优势.     

Test generation at the algorithm-level for gate-level fault coverage

We present a test generation approach that enables to construct functional test patterns at early stages of the design according to the software prototype of the circuit. The presented approach is based on an input-output pin pair and an input-input-output pin triplet fault models. The basic properties of these models are analyzed. Random test generation was implemented on the base of these fault models. ISCAS’85 and ITC’99 benchmark circuits were used for the experiments. The obtained results for the presented fault models were compared with the gate level test generation. The problem of termination of random search is explored and the solution is proposed.     

用于光电集成的InP基HBT新结构

对用于光电集成(OEIC)的InP基异质结双极性晶体管(HBT)进行了分析,提出了一种新的集电区外延结构,该结构是在单HBT(SHBT)的集电区与次集电区间加入特定厚度与掺杂浓度的p-InGaAs层和n-InP层,既适用于集成光探测器,又较好地解决了SHBT反向击穿电压低、传统双HBT(DHBT)电子堆积效应等问题,并具有外延层生长简单、集电区电子漂移速率高等优点.     

On-Line Test of Pin-Constrained Digital Microfluidic Biochips with Connect-5 Structure

Digital microfluidic biochips (DMFBs) are widely used in the field of biochemistry. Effective off-line and on-line test for the biochips are required to ensure the system reliability. For direct addressing digital microfluidic biochips (DDMFBs), each control pin corresponds to only one electrode, and that can facilitate the testing of such biochips. However, in pin-constrained digital microfluidic biochips (PDMFBs), multiple electrodes may share one control pin, and thus the testing will be more difficult. In this paper, the pin constraint formula for PDMFBs with connect-5 structure is derived. A novel pin assignment scheme is also proposed, which can conduct on-line test that rarely considered by the previous methods. Furthermore, a hybrid method combining the priority strategy and genetic algorithm is introduced for the on-line test of pin-constrained digital microfluidic biochip with connect-5 structure. The simulation results show that the shortest test path acquired by the proposed method is equal to the optimal value of Euler path, which indicates that the method can effectively implement the on-line test of PDMFBs with connect-5 structure.

     

A Versatile Mixed-Signal Pin Approach for Cost-Effective Test of Automotive ICs

Integrated circuits (ICs) intended for increasingly sophisticated automotive applications bring unique test demands. Advanced ICs for applications such as highly integrated automatic braking system (ABS) and airbag controllers combine high voltage digital channels, significant VI demands and precise timing capability. Along with continued missioncritical reliability concerns, the trend toward higher voltage operation and increased device integration requires specialized test capabilities able to extend across the wide operating ranges found in automotive applications. Among these capabilities, automotive test requirements increasingly dictate a need for a cost-effective versatile mixed-signal pin electronics with very high data rates reaching up to 50MHz with a voltage swing of-2 V to +28 V.     

基板支撑梢对TFT栅界面SiN_x和a-Si成膜特性的影响

采用等离子体增强化学气相沉积法(PECVD)制得氮化硅和氢化非晶硅薄膜,对PECVD设备中基板支撑梢区域的膜质进行了研究。结果显示基板支撑梢对氮化硅薄膜的影响是:基板支撑梢区域的膜厚(沉积速率)高于非基板支撑梢区域,氢含量及[SiH/NH]值高于非基板支撑梢;对氢化非晶硅薄膜的影响是:基板支撑梢区域的膜厚(沉积速率)小于非基板支撑梢区域,氢含量高于非基板支撑梢。并对成膜影响的机理进行了分析讨论。     

High density packaging technology ultra thin package & new tab package

As electronic devices become more highly integrated, the demand for small, high pin count packages has been increasing. We have developed two new types of IC packages in response to this demand. One is an ultra thin small outline package (TSOP) which has been reduced in size from the standard SOP and the other, which uses Tape Automated Bonding (TAB) technology, is a super thin, high pin count TAB in cap (T.I.C.) package. In this paper, we present these packages and their features along with the technologies used to improve package reliability and TAB. Thin packages are vulnerable to high humidity exposure, especially after heat shock.1 The following items were therefore investigated in order to improve humidity resistance: (1) The molding compound thermal stress, (2) Water absorption into the molding compound and its effect on package cracking during solder dipping, (3) Chip attach pad area and its affect on package cracking, (4) Adhesion between molding resin and chip attach pad and its affect on humidity resistance. With the improvements made as a result of these investigations, the reliability of the new thin packages is similar to that of the standard thicker plastic packages.     

基于双端口随机存储器IDT7133的多处理器系统中数据共享的研究

介绍了双端口随机存储器（以下简称“DPRAM”）芯片IDT7133的外部管脚功能及其芯片特点。针对多处理器系统中的数据存储与共享问题,着重阐述了基于普通单口RAM和基于DPRAM芯片IDT7133两种不同的多处理器系统应用方案。通过对两个方案的比较,认识到基于DPRAM芯片IDT7133的应用方案在数据共享及数据传输中的显著优势。最后还谈到了IDT7133芯片内部的数据存储方式,为该方案在现实中的合理运用提供了保证。     

Key performance-limiting defects in P-on-N HgCdTe LPE heterojunction infrared photodiodes

The operability of long-wavelength p-on-n double layer heterojunction arrays for 40K low-background applications has long been limited by the wide variation in pixel-to-pixel zero bias resistance (R_o) values. Diodes on test structures showing lower performance, with R_o values below 7 × 10⁶ ohm at 40K, usually contained gross metallurgical defects such as dislocation clusters and loops, pin holes, striations, Te inclusions, and heavy terracing. However, diodes with R_o values between 7 × 10⁶ and 1× 10⁹ ohm at 40K contained no visible defects. To study the “invisible” performance-limiting defects (i.e. defects that cannot be revealed by etching), a good correlation between the dynamic resistance at 50 mV reverse bias (R50) value at 77K and the R_o value at 40K was first established, and then used as a tool. The correlation allowed measurements of a large number of devices at 77K, rather than relying exclusively on time-consuming measurements at 40K. Interesting results regarding R_o values at 40K, such as insensitivity to low-density dislocations, mild degradation from Hg vacancies, severe degradation from Hg interstitials, and correlation with junction positioning, were obtained from specially designed experiments.     

短路针加载微带天线反射损耗的神经网络模型

短路针加载的微带贴片天线具有较低的谐振频率,特别适用于便携式通信设备中.作者采用多层感知器建立了短路针加载圆形贴片天线的神经网络模型,把短路针位置作为输入样本,天线的反射损耗S11参数作为输出样本,采用BP算法对多层感知器进行训练.当多层感知器训练完成,在学习范围内将短路针位置输入到多层感知器,从输出端立即得到准确的S11参数.