基于帧间差分法的目标检测研究与FPGA实现

针对以往帧间差分算法的硬件实现架构中数据同步信号设计复杂,调试周期较长的特点,设计了一种新型的硬件算法架构。整个系统基于Altera的Cyclone Ⅳ E系列进行开发,采用镁光的SDRAM作为高速储存器件,豪威科技的OV5640作为图像采集器件。该系统对采集到的原始图像数据进行灰度化处理,利用硬件差分算法模块对灰度图像进行差分处理与二值化,实现对视频图像中动态目标的捕捉。基于Quratus Ⅱ与Modelsim联合开发平台对系统进行硬件设计和功能模块仿真。硬件测试结果表明,系统能够清晰地检测出视频中的动态目标,且具备较好的实时性。     

视频缩放在FPGA中的应用和实现

针对某显示系统中监控视频控制器的实际需求,设计了一种可实现四路视频信号实时缩放的电路架构。通过权衡几种常用图像缩放算法的显示质量和硬件可行性,选择用双线性插值算法实现视频的缩放,并在FPGA平台上以双口RAM资源构建的线缓存作为算法硬件实现,该算法主要由视频数据缓冲模块、插值系数产生模块以及整体控制模块构成。本设计在满足视频缩放质量要求的基础上,避免了采用过于复杂算法而消耗过多的FPGA资源,有效地解决了视频缩放时原始图像信息量丢失导致图像失真的问题。结果表明,该设计能够实现任意比例的视频缩放,实时性高,应用灵活,缩放后显示效果良好,能够满足实际工程的要求。     

基于OpenCL与FPGA异构模式的Sobel算法研究

随着计算机科学技术的迅速发展,嵌入式领域实时图像处理应用越来越广泛,然而传统硬件因为自身架构导致并行化程度不高,针对在视频监控、机器视觉、视频压缩、医疗影像分析等领域需要对图像进行高性能计算的问题,提出一种以OpenCL软件模型和FPGA异构模式的高性能图像处理解决方案,实现了图像显示和OpenCL加速功能,以Sobel边缘检测算法为研究对象,进行了算法并行性分析,并在系统中运用OpenCL加速内核算法,与基本的ARM平台和OpenCL共享内存加速机制相比较,展开性能测试,对加速效果进行了研究。实验数据表明,使用该系统处理不同分辨率的图像,OpenCL加速子系统的处理较基于片上ARM硬核的软件处理,实现相同功能上有100倍左右的性能提升。     

基于FPGA高速实时图像数据处理系统的研究

本文对在FPGA中嵌入Powerpc(hard IP Core),引入linux嵌入式操作系统用来开发嵌入式系统进行了研究,系统实现了高速数据采集、高速视频数据压缩、实时视频数据的网络传输和实时压缩图像数据存储功能,该方法采用linux嵌入式操作系统加FPGA中嵌入的Powerpc硬核处理器进行系统控制层面的处理,还根据FPGA的特点将视频处理等功能用高速硬件实时处理。系统适合于系统空间要求小且视频数据处理量大的应用。     

PowerPC在车辆显控系统中的应用

车辆显控系统的控制主板选用高性能PowerPC MPC8548E处理器,扩展了显示器、内存、Flash存储器和接口设备.以此主板为平台,实现了车辆数据和视频的实时显示和控制.本文重点阐述了在PowerPC上用软件实现I2C控制以及通过PCI总线实现设备间通信的方法.     

运用FPGA进行实时视频数据预处理

针对基于DSP实现的实时视频信号处理系统中原始视频数据与视频编码算法不兼容问题，本文阐述了用FPGA解决该类问题的优势，并举例用FPGA实现某种MPEG4编码算法前数据预处理的实例。该设计已通过硬件实现，结果表明是正确有效的。     

基于FPGA的嵌入式语音识别控制系统

介绍了一款针对特定人、孤立词的嵌入式语音识别系统的设计与实现.该系统的硬件核心部件是Virtex-II Pro50 FPGA芯片,其硬核处理器是PowerPC405.本系统对预处理、端点检测、LPCC特征提取部分进行了定点化处理;DTW算法采用硬件IP核实现;整体调度采用中断方式实现.将该系统用于语音控制玩具机器狗AIBO进行实验,识别率达到98.3%.本系统设计性能满足玩具、游戏等消费娱乐电子设备对识别率和实时性的性能要求,具有广阔的市场应用前景.     

基于ZYNQ的高清图像显示及检测系统设计

针对当前基于ARM和DSP的嵌入式图像处理系统前端采集速度慢和图像处理算法不易加速的缺点,设计了一种基于HDMI接口的全高清(分辨率1920×1080)实时视频采集与图像处理系统;采用500万像素级别CMOS摄像头作为前端数据源,主芯片内部采用ARM+FPGA的异构架构,兼备FPGA的并行处理能力与ARM处理器任务调度功能;基于AXI协议设计了自定义数据存储传输的IP核,实现了处理速度与带宽最大化;利用HLS工具将图像预处理算法快速打包生成IP核,在FPGA中实现图像算法的硬件加速,完成图像处理系统平台原型机的设计;与传统的PC机和相机的机器视觉平台相比,该系统运行平均耗时在10 ms以内,实时检测效果令人满意,有效解决了低功耗与高数据带宽和处理速度之间的矛盾,为后端结果分析和边缘加速提供了良好支持。     

基于DSP的实时人脸检测系统

阐述了硬件设计思想、软件开发流程及人脸检测算法的实现.首先以TMS320DM642建立实时图像处理的硬件系统,通过CCD获取视频序列,对当前图像进行降噪、图像增强以及边缘检测的预处理,再利用基于肤色和差分帧相结合的算法对视频序列进行检测、跟踪人脸.本系统所有算法均使用C和汇编语言混合编程并在TI DM642EVM上开发实现.实验结果表明,本系统的算法简单、快速、鲁棒性强.     

基于DSP的实时人脸检测系统

阐述了硬件设计思想、软件开发流程及人脸检测算法的实现。首先以TMS320DM642建立实时图像处理的硬件系统,通过CCD获取视频序列,对当前图像进行降噪、图像增强以及边缘检测的预处理,再利用基于肤色和差分帧相结合的算法对视频序列进行检测、跟踪人脸。本系统所有算法均使用C和汇编语言混合编程并在TIDM642EVM上开发实现。实验结果表明,本系统的算法简单、快速、鲁棒性强。     

Efficient hardware architecture of 2D-scan-based wavelet watermarking for image and video

This paper describes an efficient hardware architecture of 2D-Scan-based-Wavelet watermarking for image and video. The potential application for this architecture includes broadcast monitoring of video sequences for High Definition Television (HDTV) and DVD protection and access control. The proposed 2D design allows even distribution of the processing load onto a set of filters, with each set performing the calculation for one dimension according to the scan-based process. The video protection is achieved by the insertion of watermarks bank within the middle frequency of wavelet coefficients related to video frames by their selective quantization. The 2-D DWT is applied for both video stream and watermark in order to make the watermarking scheme robust and perceptually invisible. The proposed architecture has a very simple control part, since the data are operated in a row-column-slice fashion. This organization reduces the requirement of on-chip memory. In addition, the control unit selects which coefficient to pass to the low-pass and high-pass filters. The on-chip memory will be small as compared to the input size since it depends solely on the filter sizes. Due to the pipelining, all filters are utilized for 100% of the time except during the start-up and wind-down times. The major contribution of this research is towards the selection of appropriate real time watermarking scheme and performing a trade-off between the algorithmic aspects of our proposed watermarking scheme and the hardware implementation technique. The hardware architecture is designed, as a watermarking based IP core with the Avalon interface related to NIOS embedded processor, and tested in order to evaluate the performance of our proposed watermarking algorithm. This architecture has been implemented on the Altera Stratix-II Field Programmable Gate Array (FPGA) prototyping board. Experimental results are presented to demonstrate the capability of the proposed watermarking system for real time applications and its robustness against malicious attacks.     

Embedding of a real time image stabilization algorithm on a parameterizable SoPC architecture a chip multi-processor approach

Highly regular multi-processor architectures are suitable for inherently highly parallelizable applications such as most of the image processing domain. Systems embedded in a single programmable chip platform (SoPC) allow hardware designers to tailor every aspect of the architecture in order to match the specific application needs. These platforms are now large enough to embed an increasing number of cores, allowing implementation of a multi-processor architecture with an embedded communication network. In this paper we present the parallelization and the embedding of a real time image stabilization algorithm on a SoPC platform. Our overall hardware implementation method is based upon meeting algorithm processing power requirements and communication needs with refinement of a generic parallel architecture model. Actual implementation is done by the choice and parameterization of readily available reconfigurable hardware modules and customizable commercially available IPs (Intellectual Property). We present both software and hardware implementation with performance results on a Xilinx SoPC target.     

A real-time versatile roadway path extraction and tracking on an FPGA platform

This paper presents an algorithm for roadway path extraction and tracking and its implementation in a Field Programmable Gate Array (FPGA) device. The implementation is particularly suitable for use as a core component of a Lane Departure Warning (LDW) system, which requires high-performance digital image processing as well as low-cost semiconductor devices, appropriate for the high volume production of the automotive market. The FPGA technology proved to be a proper platform to meet these two contrasting requirements. The proposed algorithm is specifically designed to be completely embedded in FPGA hardware to process wide VGA resolution video sequences at 30 frames per second. The main contributions of this work lie in (i) the proper selection, customization and integration of the main functions for road extraction and tracking to cope with the addressed application, and (ii) the subsequent FPGA hardware implementation as a modular architecture of specialized blocks. Experiments on real road scenario video sequences running on the FPGA device illustrate the good performance of the proposed system prototype and its ability to adapt to varying common roadway conditions, without the need for a per-installation calibration procedure.     

基于TMS320DM6467的监控视频去雾算法实现

有雾天气情况下拍摄的视频成像质量退化严重,极大地影响了安防监控、视觉导航等系统的整体性能.面向DSP嵌入式平台,提出一种实时监控视频去雾系统实现方案.首先在暗通道先验单幅图像去雾的基础上,提出了一种监控视频去雾算法;其次,基于TMS320DM6467处理器的硬件资源,对视频格式转换、除法运算、透射率计算、数据搬移等环节进行代码优化,最终在硬件平台上实现了整体系统.实测结果表明,对于D1格式的视频,在兼顾去雾质量的同时,达到了实时处理要求.     

弹性体工件在线检测系统中视频预处理IP核设计

为了能够实时地检测弹性体工件的缺陷和尺寸,设计并实现了一种基于处理器局部总线(PLB)的视频预处理IP核。对IP核所采用的结构、卷积运算的硬件实现进行研究。用System Generator工具设计LOG滤波器,最终在现场可编程门阵列(FPGA)上实现边缘检测算法。实验结果表明:与传统用软件实现边缘检测算法的方法相比,用IP核实现时间大幅减少,仅为40ms,满足弹性体工件在线检测系统中实时预处理视频的要求。     

三维扫描仪中人头轮廓线提取方法及实现

为解决三维扫描仪的实时性,文章提出了以FPGA处理器与PC主机交互式共同完成提取轮廓线的快速算法。该算法由两个阶段组成:第一阶段由主机计算背景与目标的分割阈值。第二阶段由FPGA处理器实时检测轮廓线位置信息。该快速算法具有计算简单、实现速度快等优点,并且减少了传输与存储的数据量,减轻了后面主机计算工作量。同时,省掉了昂贵的图像采集压缩卡与高速硬盘,降低了成本。可重构FPGA处理器设计成流水线结构,对每个像素的平均处理时间控制在70ns以内。仿真与综合结果表明:从一帧720576标准PAL制视频图像中提取轮廓线信息可在40ms内实时完成。     

面向FT-M7002的高斯滤波算法优化实现

国产自主研发的飞腾系列高性能DSP处理器在图像处理领域的应用,对面向该平台的高性能图像处理算法提出了强烈需求.高斯滤波作为图像处理的基础算法,能有效滤除图像中的高斯噪声,在图像处理领域具有广泛应用.针对飞腾高性能DSP的体系结构特点与高斯滤波算法特性,实现了面向飞腾高性能DSP的高斯滤波算法优化.通过手工向量化、控制流消除和循环展开等优化手段充分利用数据级与指令级并行性,从而减少数据访存次数,提高指令执行效率.针对FT-M T2内核中的DM A硬件及向量存储器结构特点,进行了"乒-乓"缓存、DM A数组转置等优化,以减少数据传输时间,提高数据局部性.多种滤波核大小及图像矩阵规模下的测试结果表明,相对于高斯滤波算法的串行实现,该并行优化实现获得了1.3～1.41倍的加速比.在开启Cache的情况下,相较于dsplib库中高斯滤波算法在T M S320C6678平台上的运行性能,获得了1.15～1.71倍的加速效果.