Smile: a computer program for partitioning of programmed logic arrays

This paper presents a new approach to optimal topological design of PLAs (programmed logic arrays). In particular we address the array partitioning problem and the implementation of partitioned arrays as block folded or parallel connected PLAs. We present a graph theoretic interpretation of the problem and an efficient heuristic algorithm. A computer program, Smile, is described and experimental results are reported.     

Designing with programmable logic arrays

Programmable logic arrays (PLAs) are characterized by the ability to replace discrete logic components and their equivalent functions in a variety of system designs. With the advent of new technologies and computer software tools such as Amaze, the exercise of designing with PLAs has been simplified. This paper provides a tutorial overview of various aspects of designing with PLAs, and discusses their uses and basic variations to their structures. A design example involving a single-board computer is presented; the control logic in this design can easily be adapted to other single-board computers.     

Built-in test for folded programmable logic arrays

Implementing a function using a programmable logic array (PLA) can often be very expensive in terms of area. Folding rows and/or columns of a PLA usually leads to a reduction in area. In this paper the problem of fault detection in folded PLAs is considered. A new fault, the ‘cutpoint’ fault, is described and universal test sets for the detection of this fault are presented. Modifications to existing built-in universally testable design techniques for nonfolded PLAs are presented; the new designs are now applicable to folded PLAs.     

Analysis of testable PLA designs

A framework is presented for evaluating methods of testing programmable logic arrays (PLAs), and the attributes of 25 test design methodologies are tabulated. PLA testing problems are first examined, and several test-generation algorithms are briefly described. Techniques for designing testable designs are examined, namely, special coding, parity checking, signature analysis, divide and conquer, and fully testable PLAs. The attributes that make a good testable design are then discussed. They fall into four categories: (1) testability characteristics; (2) effect on original design; (3) requirements of the application environment; and (4) design costs, i.e. how difficult it is to implement the technique     

输入端加译码器的可编程逻辑阵列的复杂性分析

输入端加译码器的可编程逻辑阵列比普通的可编程逻辑阵列具有更大的实现能力。这种阵列表现为三级或－与－或电路。本文提出了与该电路相关的一系列基本概念和理论，并且还进行了复杂性分析，结论是使用该阵列实现一个任意Ｎ变量逻辑函数所需的最大存储单元数为：（２ｎ＋１）２＾ｎ－２．     

LORES-2: A Logic Reorganization System

LORES-2 is a logic reorganization system which greatly contributes to the effective automation of logic design. LORES-2 uses a macro-expansion technique to help designers transform printed-circuit assembly logic composed of SSI and MSI circuits into master-slice LSI logic circuits. The number of gates of the most reorganized LSI circuit falls within ± 20 percent of the number of gates of the original circuit. When ROMS and/or PLAs are not-allowed on the target LSI circuit, those elements are converted into optimized, multilevel random logic using logic minimization, factoring and macro-expansion techniques.     

FSL: a fast structured logic design methodology for high speed GaAs digital integrated circuits

FSL (fast structured logic) is an automated design methodology concept, directed toward the rapid design of III–V integrated circuits and based on the use of small PC orientated workstations. The FSL approach is a flexible and hierarchical design method which offers high levels of integration and performance, and reduced design time while ensuring ‘first pass’ success. Control of onchip high speed interconnects and automatic design verification by construction are important attributes of FSL. This unique chip design approach is technology independent, in that the chip design and functional logic simulation is completed before the semiconductor technology is selected. The chip performance characteristics and topological layout are automatically defined when the GaAs (Gallium arsenide) fabrication process is selected. FSL is a structured logic design approach which allows control of critical parameters through high speed interconnect constraints and significantly shortens the IC development cycle.The design, fabrication and evaluation testing of a 4-bit up/down counter circuit and a 16 stage PN code generator designed with FSL and implemented in GaAs semiconductor technology are described. GaAs chips implemented with FSL have been compared with other design methods. These comparisons indicate packing densities comparable to standard cell approaches, with design cycle times in the order of those required for gate array implementations, while approaching performance levels achieved with handcrafted designs.     

Top-Down Layout for Hierarchical Custom Design

Champ, a chip floor-plan program, and Alpha, an automatic cell placement and routing system, provide a method for hierarchical custom VLSI design that is highly automated and completely top-down. The system can handle standard cell blocks as well as macro cells such as RAMs, ROMs, PLAs. Champ consists of initial block placement and block packing Designers can execute initial block placement either manually or automatically using a method based on attractive-repulsive forces. Block packing is performed automatically or interactively through the moving and reshaping of blocks, which is done as the chip boundaries are being shrunk. Following the floor-plan design, Alpha automatically executes cell placement and routing. Using Champ/Alpha, only seven mandays are needed to design a 20,000-gate VLSI layout, using a predesigned standard cell library and predesigned macro cells.     

Seven strategies for tolerating highly defective fabrication

This article we present an architecture that supports fine-grained sparing and resource matching. The base logic structure is a set of interconnected PLAs. The PLAs and their interconnections consist of large arrays of interchangeable nanowires, which serve as programmable product and sum terms and as programmable interconnect links. Each nanowire can have several defective programmable junctions. We can test nanowires for functionality and use only the subset that provides appropriate conductivity and electrical characteristics. We then perform a matching between nanowire junction programmability and application logic needs to use almost all the nanowires even though most of them have defective junctions. We employ seven high-level strategies to achieve this level of defect tolerance.     

Icon: A Tool for Design at Schematic, Virtual Grid, and Layout Levels

The design of a custom VLSI chip requires work at several levels of abstraction. For example, random logic is naturally described as schematics, hand-entered layouts are naturally entered on a virtual grid, and machine-generated or compacted layouts are edited on an accurate, geometrically fixed grid. Icon is a new computer-aided design tool that allows these aspects of design to be handled simultaneously. It provides a schematics entry and simulation system, a virtual-grid compacter, and a layout editor. The user interface is consistent across these functions, and it is possible to mix them on the screen. In particular, Icon allows the user to insert pieces of layout, such as PLAs, directly into a schematic. This eliminates the effort of developing a logic diagram for them and provides accurate simulation with both interactive graphics and program level capabilities. Several dozen full-custom NMOS and CMOS chips have been designed with Icon, including a number of local area network support chips, a high-speed RAM, and high bandwidth data switches.     

A graph theory-based approach to route location in railway interlocking

The location and verification of routes is an important component of railway interlocking logic design. The interlocking routes are typically listed manually by experienced signaling engineers, and this task is both time consuming and expensive. In this paper, an automatic, graph theory-based approach to route location and verification is presented. In this new approach, a component-based model is used to represent the topology of the station layout, and a modified matrix algorithm based on graph theory is used to locate all of the routes in a given station. This algorithm exhibits superior performance in the location and verification of routes and is universally applicable, irrespective of the station layout. When a station is modified, the designers can simply update the topological data for the station, and the new route information can be obtained automatically.     

A method for consistent fault coverage reporting

Procedure 5012 of Mil-Std-883, which describes requirements for the logic model, the assumed fault model and universe, fault classing, fault simulation and reporting of test results for digital microcircuits is described. The procedure provides a consistent means of measuring fault coverage regardless of the specific logic and fault simulator used. Procedure 5012 addresses complex, embedded structures such as random-access memories (RAMs), read-only memories (ROMs), and programmable logic arrays (PLAs) weighting gate-level and non-gate-level structures by transistor counts to arrive at overall fault coverage     

Product design logic for an intelligent product modelling system

Recent research in CAD systems has been conducted to realize intelligent processing. Several CAD systems and product modelling systems have been developed using AI techniques. However, in order to develop more intelligent CAD systems, the design logic which connects the functional requirement to the geometric and the technological information of the designed product must be evaluated.

A product model used in such intelligent CAD systems has to include not only the geometric and the technological information of the product but also the designer's thought process which explains the design logic.

Design logic is generally divided into two parts. One is the generalized design logic which is commonly used in the conceptual design of mechanical products. The other is the product specified design logic which is used in the fundamental and detailed design phase. Different logic is applied to each product. This type of design logic is often used in modification design and compilation design, where the dimensions of parts have to be modified according to different functional requirements. When the dimensions and accuracies of the products are defined in connection with the functional requirements through design logic, the CAD system can automatically make decisions according to the given requirements. In this paper, suitable presentation formats and processing functions for these two types of design logic are discussed.

The importance of design logic in product modelling is proven through several case studies in this paper. As a conclusion, the intelligent product modelling system is developed, which should expedite the progress of design automation in the near future. In conceptual design, the design logic is processed in the modelling system and the product structure, with the technological information decided automatically from the functional requirement. Automation in the detailed design phase is also facilitated by the modelling system using the product specified design logic in the product model.     

Multiple-valued logic and optimization of programmable logic arrays

Shows a method of designing programmable logic arrays (PLAs) using multiple-valued input, two-valued output functions (MVITVOFs). A MVITVOF is an extension of the two-valued logic function. An expression for a MVITVOF directly represents a multiple-output PLA with decoders. Each product of the expression corresponds to each column of the PLA, so the number of products; in the expression equals the number of columns of the PLA. The array size of the PLA is proportional to the number of products; the PLA can thus be minimized by minimizing the expression     

Non-Discriminatory Automatic Registration of Knock-On Train Delays

Incidents and waiting for train connections are registered by dispatchers as sources of train delays, but route and headway conflicts are not always clearly recognized. Moreover, traffic management and route setting are the primary task of dispatchers and signallers, whilst monitoring and incident registration is not allowed to take up too much of their time. This paper describes a tool that automatically and without discrimination identifies route conflicts and the train numbers involved. It is based on standard train describer and infrastructure messages recorded on the Dutch railway network. The logic of these messages is captured in a coloured Petri net (CPN) model on which a prototype tool for route conflict identification and estimation of knock-on delay has been developed.     

采用新的DNA进化算法自动设计Takagi-Sugeno模糊控制器

提出一种新颖的基于DNA的进化算法(DNA-EA)来自动设计一类Trakagi-Sugeno (TS)模糊控制器.TS模糊控制器采用带有线性规则后项的TS模糊规则,连续输 入模糊集,Zadeh模糊逻辑和常用的重心反模糊器.TS模糊控制器被证明是带有可变增 益的非线性PI控制器.DNA-EA被用于自动获取TS模糊规则,并同时优化模糊规则前 项和后项中的设计参数.DNA-EA采用由生物DNA结构启发得到的DNA编码方法来编 码模糊控制器的设计参数.在DNA-EA中,引入了受微生物进化现象启发的基因转移和细 菌变异操作.另外,也引入了基于DNA遗传操作的框构变异操作.DNA编码方法非常适 合于复杂知识的表达,基于基因水平的遗传操作也很容易引入到DNA-EA中.染色体的长 度是可变的,且可插入或删除部分碱基序列.作为示例,给出了采用DNA-EA来自动设计 TS模糊控制器用于控制一类非线性系统的方法.DNA-EA能自动地构造模糊控制器.计 算机仿真结果表明,DNA-EA是有效的,且优化得到的模糊控制器是满意的.     

Agile product-line architecting in practice: A case study in smart grids

ContextSoftware Product Line Engineering implies the upfront design of a Product-Line Architecture (PLA) from which individual product applications can be engineered. The big upfront design associated with PLAs is in conflict with the current need of “being open to change”. To make the development of product-lines more flexible and adaptable to changes, several companies are adopting Agile Product Line Engineering. However, to put Agile Product Line Engineering into practice it is still necessary to make mechanisms available to assist and guide the agile construction and evolution of PLAs.ObjectiveThis paper presents the validation of a process for “the agile construction and evolution of product-line architectures”, called Agile Product-Line Architecting (APLA). The contribution of the APLA process is the integration of a set of models for describing, documenting, and tracing PLAs, as well as an algorithm for guiding the change decision-making process of PLAs. The APLA process is assessed to prove that assists Agile Product Line Engineering practitioners in the construction and evolution of PLAs.MethodValidation is performed through a case study by using both quantitative and qualitative analysis. Quantitative analysis was performed using statistics, whereas qualitative analysis was performed through interviews using constant comparison, triangulation, and supporting tools. This case study was conducted according to the guidelines of Runeson and Höst in a software factory where three projects in the domain of Smart Grids were involved.ResultsAPLA is deployed through the Flexible-PLA modeling framework. This framework supported the successful development and evolution of the PLA of a family of power metering management applications for Smart Grids.ConclusionsAPLA is a well-supported solution for the agile construction and evolution of PLAs. This case study illustrates that the proposed solution for the agile construction of PLAs is viable in an industry project on Smart Grids.     

Design and implementation of the tree-based fuzzy logic controller

In this paper, a tree-based approach is proposed to design the fuzzy logic controller. Based on the proposed methodology, the fuzzy logic controller has the following merits: the fuzzy control rule can be extracted automatically from the input-output data of the system and the extraction process can be done in one-pass; owing to the fuzzy tree inference structure, the search spaces of the fuzzy inference process are largely reduced; the operation of the inference process can be simplified as a one-dimensional matrix operation because of the fuzzy tree approach; and the controller has regular and modular properties, so it is easy to be implemented by hardware. Furthermore, the proposed fuzzy tree approach has been applied to design the color reproduction system for verifying the proposed methodology. The color reproduction system is mainly used to obtain a color image through the printer that is identical to the original one. In addition to the software simulation, an FPGA is used to implement the prototype hardware system for real-time application. Experimental results show that the effect of color correction is quite good and that the prototype hardware system can operate correctly under the condition of 30 MHz clock rate.     

Performance evaluation of fuzzy-based decision system for pool

An important step in any machine intelligence is to automatically and reliably decide on a solution/outcome based on the inputs given. The mapping of the inputs to an output decision often follows a set of critical rules that mimic the decision that would often be decided by a human being. In this paper, the performance of a fuzzy-based decision system for playing a game of pool is presented by comparing the results involving direct hit with two known systems. The performance is also compared to the decision that would be made by the human players. The design steps for the fuzzy-based decision system are presented using the fuzzy logic approach by employing a three-input one-output fuzzy inference system based on a set of 24 rules. The results have shown that fuzzy logic is able to accurately decide on the best move, which is as good as the human players themselves.     

A fast partitioning method for PLA-based FPGAs

A method for automatic multipartitioning of a multiple-output logic function into the smallest number of subfunctions for mapping to fixed-size PLAs of a field-programmable gate array (FPGA) chip is described. A detailed example to demonstrate the procedure is presented. It is shown that, for this example, the method produced almost optimum partitions in a fast and efficient manner