A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems

We present a methodology for the exploration of signal processing architectures at the system level. The methodology, named SPADE, provides a means to quickly build models of architectures at an abstract level, to easily map applications, modeled as Kahn Process Networks, onto these architecture models, and to analyze the performance of the resulting system by simulation. The methodology distinguishes between applications and architectures, and uses a trace-driven simulation technique for co-simulation of application models and architecture models. As a consequence, architecture models need not be functionally complete to be used for performance analysis while data dependent behavior is still handled correctly. We have used the methodology for the exploration of architectures and mappings of an MPEG-2 video decoder application.     

可重构结构设计空间快速搜索方法

在可重构结构评估模型的基础上,研究了在算法级估计可重构结构的面积、性能和功耗的方法。根据面积、性能和功耗,分两步搜索可重构结构的设计空间。首先,搜索结构域中每个结构实现所有算法时的最小代价,其次,在结构设计空间中搜索最优结构。该方法不依赖任何具体的架构,全面评价可重构结构的优劣,能快速获得全局最优的搜索结果。应用实例表明,在可重构结构设计初期,该方法能有效地指导可重构结构的设计。     

A Mapping Framework Based on Packing for Design Space Exploration of Heterogeneous MPSoCs

The computational demand of signal processing algorithms is rising continuously. Heterogeneous embedded multiprocessor systems-on-chips are one solution to satisfy this demand. But to be able to take advantage of these systems, new strategies are required to map applications to such a system and to evaluate the systems performance at a very early design stage. We will present a framework for static, analytical, bottom-up temporal and spatial mapping of applications to MPSoCs based on packing. This mapping framework allows easy performance evaluation and design space exploration of heterogeneous systems on chip.

Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip

The exploration of the design space for heterogeneous Systems on Chip (SoC) becomes more and more important. As modern SoCs include a variety of different architecture blocks ensuring flexibility as well as highest performance, it is mandatory to prune the design space in an early stage of the design process in order to achieve short innovation cycles for new products. Thus, the goal of this work is to provide estimations of implementation specific parameters like throughput rate, power dissipation and silicon area by means of cost functions featuring reasonable accuracy at low modeling effort. A model based exploration strategy supporting the design flow for heterogeneous SoCs is presented. In order to demonstrate the feasibility of this exploration strategy, in a first step implementation cost parameters are provided for a variety of basic operations frequently required in digital signal processing which were implemented on discrete components like DSPs, FPGAs or dedicated ASICs. These implementation parameters serve as a basis for deriving cost models for the design space exploration concept.Holger Blume received his Dipl.-Ing. degree in electrical engineering from the University of Dortmund, Germany in 1992. From 1993 to 1998 he worked as a research assistant with the Working group on Circuits and Systems for Information Processing of Prof. Dr. H. Schröder in Dortmund. There he finished his PhD on Nonlinear fault tolerant interpolation of intermediate images in 1997. In 1998 he joined the Chair of Electrical Engineering and Computer Systems of Prof. Dr. T. G. Noll at the University of Technology RWTH Aachen as a senior engineer. His main research interests are in the field of heterogeneous reconfigurable Systems on Chip for multimedia applications. Dr. Blume is chairman of the German chapter of the IEEE Solid State Circuits Society.Hendrik T. Feldkaemper received the Dipl.-Ing. degree from the University of Technology RWTH Aachen, Germany, in 1997. After half a year of employment in an industrial project at Infineon Technologies in Munich he joined the Chair of Electrical Engineering and Computer Systems (Prof. Dr. T. G. Noll), University of Technology RWTH Aachen as a research assistant. His current research interest include design space exploration for digital signal processing in ultrasound, heterogeneous reconfigurable Systems-on-Chip and VLSI CMOS design.Tobias G. Noll received the Ing. (grad.) degree in Electrical Engineering from the Fachhochschule Koblenz, Germany in 1974, the Dipl-Ing. degree in Electrical Engineering from the Technical University of Munich in 1982, and the Dr.-Ing. degree from the Ruhr-University of Bochum in 1989.From 1974 to 1976, he was with the Max-Planck-Institute of Radio Astronomy, Bonn, Germany, being active in the development of microwave waveguide and antenna components. From 1976 to 1982, he was with the MOS Integrated Circuits Department and from 1982 to 1984, the MOS-Design Team trainee program of Siemens AG, Munich. In 1984, he joined the Corporate Research and Development Department of Siemens, and since 1987, he has headed a group of laboratories concerned with the design of algorithm-specific integrated CMOS circuits for high speed digital signal processing.Since 1992, he has been a Professor for Electrical Engineering and Computer Systems with the University of Technology (RWTH), Aachen, Germany. In addition to teaching, he is involved in research activities on VLSI architectural strategies for high-speed digital signal processing, circuit concepts, and design methodologies, as well as on digital signal processing for medicine electronics.     

Memory Design and Exploration for Low Power, Embedded Systems

In this paper, we describe a procedure for memory design and exploration for low power embedded systems. Our system consists of an instruction cache and a data cache on-chip, and a large memory off-chip. In the first step, we try to reduce the power consumption due to memory traffic by applying memory-optimizing transformations such as loop transformations. Next we use a memory exploration procedure to choose a cache configuration (cache size and line size) that satisfies the system requirements of area, number of cycles and energy consumption. We include energy in the performance metrics, since for different cache configurations, the variation in energy consumption is quite different from the variation in the number of cycles. The memory exploration procedure is very efficient since it exploits the trends in the cycles and energy characteristics to reduce the search space significantly.     

Model-Driven Approach for Early Power-Aware Design Space Exploration of Embedded Systems

Due to the growing complexity of Systems-on-Chip (SoC) and the increasing cost of their redesign and fabrication, industrials are urgently looking for design methodologies allowing them to identify issues early in the design flow and to explore the largest possible space of solutions. Several aspects should be taken into account in this context, among which power consumption is considered as a major concern. In this paper, we present a Model Driven Engineering (MDE) approach for early power-aware Design Space Exploration (DSE). This approach facilitates designers work by abstracting the energetic behavior of embedded systems through high-level models targeting an automatic generation of power-aware simulation code. It offers also the possibility to model dynamic power management aspects in order to use the corresponding generated code for DSE. This approach was implemented in the DSE toolkit TTool by integrating power concepts in its DIPLODOCUS UML profile and its simulator. This paper illustrates the proposed approach through a Software-Defined Radio (SDR) case study integrating the Dynamic Slack Reclamation (DSR) policy for dynamic power management. The processor power estimates obtained by the generated simulation code were compared to those obtained from physical implementation on the Xilinx Zynq-7000 platform. This comparison showed that our MDE approach allows to take efficient design decisions early in the design flow.     

IMPACCT: Methodology and Tools for Power-Aware Embedded Systems

Power-aware systems are those that must exploit a widerange of power/performance trade-offs in order to adapt to the power availabilityand application requirements. They require the integration of many novel powermanagement techniques, ranging from voltage scaling to subsystem shutdown.However, those techniques do not always compose synergistically with eachother; in fact, they can combine subtractively and often yield counterintuitive,and sometimes incorrect, results in the context of a complete system. Thiscan become a serious problem as more of these power aware systems are beingdeployed in mission critical applications.To address the problem of technique integration for power-aware embedded systems, we propose a new design tool framework called IMPACCT and the associated design methodology. The system modeling methodology includes application model for capturing timing/powerconstraints and mode dependencies at the system level. The tool performs power-awarescheduling and mode selection to ensure that all timing/power constraintsare satisfied and that all overhead is taken into account. IMPACCT then synthesizesthe implementation targeting a symmetric multiprocessor platform. Experimentalresults show that the increased dynamic range of power/performance settingsenabled a Mars rover to achieve significant acceleration while using lessenergy. More importantly, our tool correctly combines the state-of-the-arttechniques at the system level, thereby saving even experienced designersfrom many pitfalls of system-level power management.     

Methodology for Refinement and Optimisation of Dynamic Memory Management for Embedded Systems in Multimedia Applications

In multimedia applications, run-time memory management support has to allow real-time memory de/allocation, retrieving and processing of data. Thus, its implementation must be designed to combine high speed, low power, large data storage capacity and a high memory bandwidth. In this paper, we assess the performance of our new system-level exploration methodology to optimise the memory management of typical multimedia applications in an extensively used 3D reconstruction image system [1, 2]. This methodology is based on an analysis of the number of memory accesses, normalised memory footprint¹ and energy estimations for the system studied. This results in an improvement of normalised memory footprint up to 44.2% and the estimated energy dissipation up to 22.6% over conventional static memory implementations in an optimised version of the driver application. Finally, our final version is able to scale perfectly the memory consumed in the system for a wide range of input parameters whereas the statically optimised version is unable to do this.The original version of this paper first appeared in the Proceedings of Signal Processing Systems 2003.Marc Leeman has as professional research interests hardware/software co-design, code optimisation in general and optimisation of dynamic data types and dynamic memory management for low power embedded systems in particular. Personal interests include Open and Free software development, software configuration and GNU/Debian package maintenance. He received an engineering degree, a master in artificial intelligence and a Ph.D. in electrical engineering in 1997, 1998 and 2004 respectively, all at the K.U. Leuven. He is a member of the IEEE Computer Society. Currently, he works as an R&D Engineer for Barco Control-rooms Division (BCD) on hardware/software co-design for streaming video products.David Atienza received the M.Sc. degree in Computer Sciences from the Complutense University of Madrid (UCM), Spain in 2001. Since then he has joined the Department of Computer Architecture and Automation of Complutense University of Madrid as a sandwich Ph.D. student half-time at the Inter-university Micro-Electronics Centre (IMEC), Heverlee, Belgium. His research interests include optimisation of dynamic memory management on multimedia and wireless network applications for low power and high performance embedded systems, computer architecture and high-level design automation.Geert Deconinck is Associate Professor (hoofddocent) at the K.U. Leuven (Belgium) since 2003 and staff member of the research group ELECTA (Electrical Energy and Computing Architectures). His research interests include the design and assessment of software-based solutions to meet dependability, real-time, and cost constraints for embedded systems. In this field, he has authored and co-authored more than 120 publications in international journals and conference proceedings. He received his M.Sc. in Electrical Engineering and his Ph.D. in Applied Sciences from the K.U. Leuven, Belgium in 1991 and 1996 respectively. He was a visiting professor (bijzonder gastdocent) at the K.U. Leuven in 1999–2003. - Flanders (Belgium) in the period 1997–2003.Vincenzo De Florio received his MSc degree in computer science in 1987 and his PhD degree in engineering in 2000, respectively from the University of Bari, Italy, and the University of Leuven, Belgium. He is currently post-doctoral researcher at the University of Antwerp, where he is doing research on adaptive and dependable mobile applications. Previously he had been researcher and lecturer with Tecnopolis/SASIAM (ECMI School for Advanced Studies in Industrial and Applied Mathematics) and member of Tecnopolis/Robotic lab, where he was responsible for design of parallel robotic vision applications. Currently he is also a reviewer for several conferences and for the Journal of System Architectures.José M. Mendías received the M.Sc. and Ph.D. degrees in physics from the Complutense University of Madrid in 1992 and 1998, respectively. He joined the Department of Computer Architecture and Systems Engineering, Complutense University in 1992 as a lecturer, and became an associate professor in 2001. Since 2002, he is Vice-dean of the Computer Science Faculty at the same University. His current research interests include design automation, computer architecture and formal methods.Chantal Ykman-Couvreur is born in 1956. She received the mathematics degree from the Facultes Universitaires Notre-Dame de la Paix of Namur in 1979. She first worked at PHILIPS Research Laboratory of Belgium, from 1979 until 1991. Her main activities were concentrated on information theory and coding, cryptography and multi-level logic synthesis for VLSI circuits. Then, she joined IMEC, where she was responsible at IMEC for the dynamic memory management and the system-level design flow in the Matisse compiler for network protocol components (ATM, Internet Protocol, etc). Currently, she works on the task concurrency management design flow in the Matador project.Francky Catthoor received the engineering degree and a Ph.D. in electrical engineering from the Katholieke Universiteit Leuven, Belgium in 1982 and 1987 respectively. Since 1987, he has headed several research domains in the area of high-level and system synthesis techniques and architectural methodologies, all within the Design Technology for Integrated Information and Telecom Systems (DESICS—formerly VSDM) division at the Inter-university Micro-Electronics Centre (IMEC), Heverlee, Belgium. Currently he is an IMEC fellow. He is part-time full professor at the EE department of the K.U. Leuven.In 1986 he received the Young Scientist Award from the Marconi International Fellowship Council. He has been associate editor for several IEEE and ACM journals, like Transactions on VLSI Signal Processing, Transactions on Multi-media, and ACM TODAES. He was the program chair of several conferences including ISSS97 and SIPS01.Rudy Lauwereins is vice-president of IMEC, Belgiums Interuniversity Micro-Electronic Centre, which performs research and development, ahead of industrial needs by 3 to 10 years, in microelectronics, nano-technology, enabling design methods and technologies for ICT systems. He leads the DESICS division of 185 researchers, currently focused on the development of re-configurable architectures, design methods and tools for wireless and multimedia applications. He is also a part-time Professor at the Katholieke Universiteit Leuven, Belgium. He had obtained a Ph.D. in Electrical Engineering in 1989. Rudy Lauwereins served in numerous international program committees and organisational committees, and gave many invited and keynote speeches. He is vice-chair of the board of DSP Valley and member of the board of several spin-off companies. He is a senior member of the IEEE.     

Calibration of Abstract Performance Models for System-Level Design Space Exploration

High-level performance modeling and simulation have become a key ingredient of system-level design as they facilitate early architectural design space exploration. An important precondition for such high-level modeling and simulation methods is that they should yield trustworthy performance estimations. This requires validation (if possible) and calibration of the simulation models, which are two aspects that have not yet been widely addressed in the system-level community. This article presents a number of mechanisms for both calibrating isolated model components as well as a system-level performance model as a whole. We discuss these model calibration mechanisms in the context of our Sesame system-level simulation framework. Two illustrative case studies will also be presented to indicate the merits of model calibration.

面向航天嵌入式电子系统的测试语言研究

测试语言主要分2类:面向仪器的测试语言和面向信号的测试语言。通过分析2种测试语言的优缺点,结合我国航天嵌入式电子系统测试系统的特点,提出一种基于虚拟仪器的面向航天嵌入式电子系统的测试语言,该语言主要借鉴ATLAS的关键语句,将其解释为测试框架配置文件和测试文档;同时还描述该测试语言的程序格式和执行机制。     

Design Space Exploration of Distributed Loop Buffer Architectures with Incompatible Loop-Nest Organisations in Embedded Systems

The use of distributed loop buffer architectures with incompatible loop-nest organisations allows the execution of incompatible loops in parallel with minimal hardware overhead. Due to this fact, the utilisation of these distributed and scalable architectures in embedded systems is a promising option to improve the energy efficiency of the instruction memory organisations that exist in these systems. This paper proposes and analyses non-overlapping and complementary implementation options for distinct partitions of the design space that is related to distributed loop buffer architectures. The high-level trade-off analysis of the proposed implementations is crucial to present the correct process design that an embedded systems designer has to follow in order to have an efficient distributed loop buffer architecture for a certain application. Results show that, with an increase of about 6.5 % in the energy consumption of the control logic that exists in the instruction memory organisation, the overall energy consumption of the instruction memory organisation can be reduced by 6 % to 22 %, when distributed loop buffer architectures with incompatible loop-nest organisations are used instead of clustered loop buffer architectures with shared loop-nest organisations architectures.     

深空地基探测雷达的发展现状与建议

深空地基探测雷达是研究天体物理和深空探测的重要技术途径。文中介绍了它在深空探测研究中的起源和主要应用、国外发展的历史和现状、现存深空地基探测雷达的典型代表及其相应参数、研究成果等;简述了我国目前的能力条件和技术基础;分析了深空地基探测雷达的工作特点和其自身的特殊性,指出了深空地基探测雷达在发展中的一些关键技术和解决途径;最后,阐述了深空地基探测雷达未来的技术发展趋势,并结合目前的能力基础,提出了对我国未来发展深空地基探测雷达的意见或建议。     

深空探测与测控通信技术

本文简述了深空探测的重要意义,深空探测对测控通信的挑战以及人类在近30年来为解决矛盾而研究应用的各项措施和所达到的水平。提出了我们应当跟踪研究的深空测控通信领域的新体制、新技术和新设备。     

同位素电池在探月及深空探测工程中应用的战略研究

放射性同位素温差电池(RTG)不受太阳光和其他环境条件的影响,可以同时为航天器提供电能和热能,是较理想的月球和深空探测电源.在介绍了RTG的工作原理,回顾了国外RTG的应用历史,评述了RTG的发展趋势之后,讨论了应用于深空探测的RTG在优化配置过程中应当考虑的一些问题,评述了深空探测RTG的技术关键,包括RTG设计、温差电换能器技术、同位素热源及其安全技术、热管理技术和电源管理技术.最后,提出了关于RTG发展战略的建议.     

新型高收敛隐式空间映射算法设计微波滤波器

该文介绍了一种高收敛隐式空间映射算法,改进了隐式空间映射算法中粗糙模型到精细模型之间参数映射。它加入粗糙模型参数选择过程,避免了粗糙模型优化中的假收敛情况,加快精细模型与设计目标的逼近速度。参数选择过程不需要增加精细模型的计算次数,提高了优化效率。该文通过设计一个发卡形滤波器,并与以前的隐式空间映射算法计算结果进行比较,优化得到了比指标性能更优越的结果。同时证明了新算法比旧算法具有更快的逼近速度和更高的优化效率的优点。     

SOC设计方法学和可测试性设计研究进展

随着微电子工艺技术和设计方法的发展，系统级芯片(SOC)设计成为解决日益增长的设计复杂度的主要方法。文章概述了SOC设计方法学和SOC可测试性设计的发展现状，阐述了目前SOC测试存在的和需要解决的问题，描述了目前开发的各种SOC测试结构和测试策略。最后，提出了今后进一步研究的方向。