高性能16位微处理器IP软核设计

在对标准Intel8086微处理器进行分析的基础上,本文介绍了一种与其指令集兼容、性能大幅提高的可重用16位微处理器IP软核的设计。从处理器体系结构的划分,到指令集的设计以及处理器内部各单元的设计,进行了比较详尽的阐述,并对该设计进行了软件仿真和硬件验证。该处理器采用缩短指令执行时钟周期、增加指令预取队列、改进总线接口时序和减少有效地址计算时间等系统架构的优化,使性能得到大幅度的提高;通过扩展指令集实现与标准8086、8088、80186和80188系列微处理器完全软件兼容。     

高性能16位徽处理器IP软核设计

在对标准Intel 8086微处理器进行分析的基础上,本文介绍了一种与其指令集兼容、性能大幅提高的可重用16位微处理器IP软核的设计.从处理器体系结构的划分,到指令集的设计以及处理器内部各单元的设计,进行了比较详尽的阐述,并对该设计进行了软件仿真和硬件验证.该处理器采用缩短指令执行时钟周期、增加指令预取队列、改进总线接口时序和减少有效地址计算时间等系统架构的优化,使性能得到大幅度的提高;通过扩展指令集实现与标准8086、8088、80186和80188系列微处理器完全软件兼容.     

图形处理器中顶点染色仿真器的设计

为了验证图形处理器(graphic processing unit,GPU)中硬件仿真结果的正确性,采用文中设计的仿真器,将需要的指令集翻译成二进制并模拟硬件流水线进行功能仿真,经过对比,结果表明,翻译出的二进制正确,并且按照硬件流水线写出的汇编程序在仿真时能够快速检测硬件中出现的问题,让其快速修改。     

一种基于ISS的软硬件协同验证环境

讨论了一种面向SOC设计的基于指令级仿真器(ISS)的软硬件协同验证环境。在该环境中,硬件用硬件描述语言来建模,软件用编程语言来编写,使用指令集仿真器和事件驱动逻辑仿真器分别完成对软硬件的仿真,两个仿真过程使用不同的进程并行进行,并通过进程间通信(IPC)实现两个仿真器之间的信息交互。     

MPSOC中的ISS与SYSTEMC模型集成

目前在SOC设计中基于C/C 的硬件设计方法已经比较普遍,特别是使用SYSTEMC作为硬件建模语言,指令集仿真器(ISS)作为处理器模型的方式,对SOC的开发非常有效。但随着应用程序规模的增加,我们需要在系统中嵌入多个核,构成多核系统(MPSOC),以满足性能的要求。本文首先对单核系统中的ISS和硬件模块的集成方法进行分析,然后将其引入到MPSOC的开发平台的设计中,并对其效果进行验证。     

32位嵌入式RISC处理器的VLSI实现

本文实现了一个低功耗,高速度的32位RISC处理器。芯片采用了ARM V4的指令集,哈佛结构和五级流水线。同时利用了改进的流水冲突检测控制和异常处理使得流水线能以较高的速度顺序流动。与商用的ARM7TDMI相比,在0.6mm的工艺上达到了与商用0.35mm工艺制造相同的速度,同时CPI降低了26%,MIPS上升了36%。整个系统在APTIX公司提供的MP3CF硬件仿真器上完成了硬件验证,现已完成了版图设计并提交流片。     

Imperas宣布与Tensilica合作发布处理器模型

Tensilica宣布与Imperas签署合作协议,双方结成战略伙伴关系,授权在Imperas开放虚拟平台（OVP）加入Tensilica广受欢迎的Xtensa及Diamond标准处理器的快速功能仿真模型。可在OVPworld．org网站上免费下载集成的Tensilica处理器模型。所有模型将运行在Tensilica公司TurboXim快速功能仿真器上,其运行速度比传统指令集仿真器快40到80倍。     

Xtensa可配置处理器及其自动化开发工具

可配置处理器标志着第四代微处理器设计的开始,这种技术更加适合片上系统SoC的设计。每一代处理器持续大约十年时间,每个时代的处理器适合当时的需要。大约在20世纪70年代出现了第一代处理器,这个时期的处理器设计只是简单地追求性能,从4位处理器到早期的16位和32位微处理器。这种性能的提升奠定了20世纪80年代PC和工作站的基础。PCI和工作站的增长使得微处理器设计进入了20世纪80年代的第二代微处理器研制时期。精简指令集RISC设计时代发生在20世纪90年代。在这个时期,即使像X86这样坚定的复杂指令集CISC处理器也假装成精简指令集RISC体系结构。在最初的这三代处理器的成长和发展过程中,微处理器设计专家将处理器设计成固定的、单个的和可重用的模块。     

基于TTA技术的专用处理器设计

描述了一种基于传输触发体系架构(TTA)的处理器.对其指令集的设计和体系结构的优化进行了讨论,并给出了H.264帧内预测算法的ASIP处理器设计实例,有效的克服了当前专用处理器和微处理器的局限性.实验表明:基于TTA体系结构的H.264帧内预测ASIP处理器较之通用处理器运行周期快4倍以上.     

可配置处理器技术优势详解

微处理器技术发展历史 在介绍可配置处理器开发原理之前,我们先回顾一下处理器发展的历史.大约在20世纪70年代出现了第一代处理器,这个时期的处理器设计只是简单地追求性能,从4位处理器到早期的16位和32位微处理器.这种性能的提升奠定了20世纪80年代个人计算机PC和工作站的基础.个人计算机和工作站的增长使得微处理器设计进入了20世纪80年代的第2代微处理器研制时期.精简指令集RISC设计时代发生在20世纪90年代.在这个时期,即使像X86这样坚定的复杂指令集CISC处理器也假装成精简指令集RISC体系结构.在最初的这3代处理器的成长和发展过程中,微处理器设计专家将处理器设计成固定的、单个的和可重用的模块.但是在20世纪90年代随着专用集成电路ASIC和片上系统SOC制造技术的发展为微处理器设计进入第4代(即后RISC、可配置处理器)打下了坚实的基础.     

A Machine State Transition Approach to Instruction Retargeting for Embedded Microprocessors

This paper presents an interesting approach to retargeting existing software at the assembly (or binary) level from one instruction set to another instruction set. The approach is based on abstracting the instruction set behaviors as symbolic transitions of the machine states. The retargeting process is modeled as a planning process, an AI technique, that finds a plan (a sequence of operations) which brings the target processor from the same initial state to the same final state as the original software does on the source processor. The approach has been successfully applied in a design project of an x86 compatible microprocessor with an embedded internal RISC core for efficient execution. The proposed approach produced optimal x86-to-RISC mapping. In addition, the approach made it easy to keep up with microarchitecture revision during the design exploration phase since the mapping table can be automatically re-generated and re-evaluated promptly, which is difficult to achieve manually.     

一款DSP指令集模拟器性能优化技术研究

文中研究和设计的指令集模拟器(Instruction Set Simulator,ISS)仿真了"中微一号"(ZW100)DSP指令系统和存储器系统行为。在现代嵌入式系统设计过程中,ISS能够在硬件原型构造出来之前,完成对处理器设计的正确性验证和性能分析工作;同时,其还可用于验证操作系统、编译器、汇编器、连接器等系统软件的正确性和各项性能指标。目前,国内外对ISS的研究主要集中在保证ISS灵活性的前提下,应用各种优化技术,提升它的指令仿真执行速度。文章在吸收借鉴目前国际上关于ISS性能优化技术的基础上,通过对仿真策略、仿真内存管理、二进制指令译码算法进一步优化,提高了ISS的整体性能。实验证明,文中提出的优化技术能够有效提升ISS的性能。     

SDRAM功耗模型及指令FIFO优化

在嵌入式系统中,存储子系统通常是系统性能的关键,同时由于其访问频繁功耗也通常占据了功耗的大部分。本文从一个嵌入式RISC处理器的指令FIFO设计出发,提出了SDRAM的功耗模型,基于该功耗模型,提出了最优化的指令FI-FO设计。实验结果表明FIFO深度为4或者5时性能最高且消耗能量最少。     

基于Nios嵌入式处理器的片上可编程系统设计

Nios嵌入式处理器是用户可配置的通用RISC嵌入式处理器,是一个非常灵活和强大的处理器.随着PLD(可编程逻辑器件)性能的不断提高,SOPC(可编程片上系统)的设计和实现非常方便,用户可以灵活地进行系统硬件和软件设计,还可以现场进行系统级修改.文中结合实例,给出了基于Nios嵌入式处理器的SOPC软、硬件设计与实现方法.     

The Architecture and Development Flow of the S5 Software Configurable Processor

A software configurable processor (SCP) is a hybrid device that couples a conventional processor datapath with programmable logic to allow application programs to dynamically customize the instruction set. SCP architectures can offer significant performance gains by exploiting data parallelism, operator specialization and deep pipelines. The S5000 is a family of high performance software configurable processors for embedded applications. The S5000 consists of a conventional 32-bit RISC processor coupled with a programmable Instruction Set Extension Fabric (ISEF). To develop an application for the S5 the programmer identifies critical sections to be accelerated, writes one or more extension instructions as functions in a variant of the C programming language, and accesses those functions from the application program. Performance gains of more than an order of magnitude over the unaccelerated processor can be achieved.

随机测试程序发生器的设计与实现

随机测试程序生成技术是当前处理器功能验证中一项重要的支撑技术.本设计面向一种专用指令集处理器FlexEngine,在指令集模型建立时,按功能分类,实现对处理器关键单元的选择性测试;引入ISS对指令执行的动态数据分析,增加了寄存器数据范围监控、死循环预警等指令约束.实验结果表明,本设计的选择性测试功能,能够在3000条程序的测试长度下,对关键模块达到超过90%的覆盖率,有效提高了测试效率.     

基于ARM和DSP的微机线路保护装置

在微机线路保护中,利用数字信号处理器（DSP）高效快速的数字信号处理能力和嵌入式先进的精简指令集芯片机器（ARM）处理器强大的以太网通信功能,采用DSP＋ARM9的双中央处理器（CPU）的硬件结构,两者之间采用双口随机存储器（RAM）进行数据交换。软件设计基于嵌入式Linux操作系统,移植了Bootloader、内核,构建了Ramdisk的根文件系统,并移植了应用程序。     

SCSI处理器FAS466的通用软件解决方案及应用

FAS466是Qlogic公司的一款Fast结构的SCSI处理器。而FAS466处理器的开发难点之一是软件设计。文中通过对FAS466处理器内部结构和操作原理的深入分析，给出了基于FAS466的系统的通用软件解决方案和应用实例。     

基于软件模型的SDRAM指令FIFO的性能评估

针对SDRAM的读写操作具有一定的流水特性,“Garfield”的EMI(外部存储接口)设计中加入了指令缓冲(先入先出,FIFO),充分利用SDRAM的Burst模式．在处理器进行指令预取时,减少指令读取的平均等待时间。但这种方法的关键问题在于．如何选择恰当的指令缓冲深度．从而最大可能地提高整个芯片的执行效率。本文提出了一种基于软件模型来评估。首先介绍了为什么要在基于ARM7TDMI的外部存储器接口中插入指令FIFO,及如何通过软件建模的方法,用指令集模拟器和存储子系统模型模拟真实硬件环境。然后探讨了采用什么标准去评估指令执行效率的提高,最后通过实验数据得到对SDRAM指令FIFO的性能的评估。     

PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing

PLX is a concise instruction set architecture (ISA) that combines the most useful features from previous generations of multimedia instruction sets with newer ISA features for high-performance, low-cost multimedia information processing. Unlike previous multimedia instruction sets, PLX is not added onto a base processor ISA, but designed from the beginning as a standalone processor architecture optimized for media processing. Its design goals are high performance multimedia processing, general-purpose programmability to support an ever-growing range of applications, simplicity for constrained environments where low power and low cost are paramount, and scalability for higher performance in less constrained multimedia systems. Another design goal of PLX is to facilitate exploration and evaluation of novel techniques in instruction set architecture, microarchitecture, arithmetic, VLSI implementations, compiler optimizations, and parallel algorithm design for new computing paradigms.Key characteristics of PLX are a fully subword-parallel architecture with novel features like wordsize scalability from 32-bit to 128-bit words, a new definition of predication, and an innovative set of subword permutation instructions. We demonstrate the use and high performance of PLX on some frequently-used code kernels selected from image, video, and graphics processing applications: discrete cosine transform, pixel padding, clip test, and median filter. Our results show that a 64-bit PLX processor achieves significant speedups over a basic 64-bit RISC processor and over IA-32 processors with MMX and SSE multimedia extensions. Using PLXs wordsize scalability feature, PLX-128 often provides an additional 2× speedup over PLX-64 in a cost-effective way. Superscalar or VLIW (Very Long Instruction Word) PLX implementations can also add additional performance through inter-instruction, rather than intra-instruction parallelism. We also describe the PLX testbed and its software tools for architecture and related research.Ruby B. Lee is the Forrest G. Hamrick Professor of Engineering and Professor of Electrical Engineering at Princeton University, with an affiliated appointment in the Computer Science department. She is the founder and director of the Princeton Architecture Laboratory for Multimedia and Security (PALMS). Her current research is in rethinking computer architecture for high-performance but low-cost security and multimedia processing. Prior to joining the Princeton faculty in 1998, Dr. Lee served as chief architect at Hewlett-Packard, responsible at different times for processor architecture, multimedia architecture, and security architecture for e-commerce and extended enterprises. She was a key architect in the initial definition and the evolution of the PA-RISC processor architecture used in HP servers and workstations. As chief architect for HPs multimedia architecture team, Dr. Lee led an inter-disciplinary team focused on architecture to facilitate pervasive multimedia information processing using general-purpose computers. She introduced innovative multimedia instruction set architecture (MAX and MAX-2) in microprocessors, resulting in the industrys first real-time, high-fidelity MPEG video and audio player implemented in software on low-end desktop computers. Dr. Lee also co-led an HP-Intel multimedia architecture team for IA-64, released in Intels Itanium microprocessors. Concurrent with full-time employment at HP, Dr. Lee also served as Consulting Professor of Electrical Engineering at Stanford University. Dr. Lee has a Ph.D. in Electrical Engineering and a M.S. in Computer Science, both from Stanford University, and an A.B. from Cornell University, where she was a College Scholar. She is a Fellow of ACM, a Fellow of IEEE, and a member of IS&T, Phi Beta Kappa, and Alpha Lambda Delta. She has been granted 115 U.S. and international patents, with several patent applications pending.A. Murat Fiskiran is a Ph. D. student at the Department of Electrical Engineering at Princeton University. He is a member of the Princeton Architecture Laboratory for Multimedia and Security (PALMS) and a Kodak Fellow. His research interests include computer architecture and computer security.