整数5/3小波变换的VLSI结构设计

在JPEG 2000中,无损图像压缩是采用整数5/3小波变换实现的.JPEG 2000也给出了5/3小波基于提升方法的算法.对提升方法的整数5/3小波变换算法进行了研究,针对二维的变换提出一种VLSI结构.该结构由4个模块构成,模块之间并行运行,模块内部采用流水线技术.对多级变换,级间的运算还可交叉,体现了提升方法的优势,较大地提高了硬件效率.其主要优点是消耗资源少且运算速度高,同时也适用于其他整数小波变换.     

A Pipeline Architecture for Processing of DNA Microarrays Images

In this paper we present a pipeline architecture specifically designed for processing of DNA microarray images. Many of the pixilated image generation methods produce one row of the image at a time. This property is fully exploited by a pipeline which takes in one row of the produced image at each clock pulse and performs the necessary image processing steps on it. This will remove the present need for sluggish software routines that are considered a major bottleneck in the microarray technology. The size of the proposed structure is a function of the width of the image and not its length. The proposed architecture is proved to be highly modular, scalable and suited for a Standard Cell VLSI implementation.     

High performance VLSI architecture for block based visible image watermarking

In this article, a novel block-based visible image watermark VLSI architecture design and its hardware implementation in field programmable gate array (FPGA) is proposed. In this watermarking process, 1D-DCT is introduced to facilitate hardware implementation. Mathematical model is developed to reduce the computational complexity for the calculation of embedding and scaling factors, which are used to make the resultant image of best quality with uniform watermark visibility. The proposed architecture has a 12–stage pipeline. Parallelism techniques are employed in block level in order to achieve high performance. A single 8-point fast 1D-DCT is used to calculate the DCT coefficient values of the host image and the watermark image to minimize the resource utilization and power consumption. The hardware implementation of this algorithm leads to numerous advantages including reduced power, area and higher pipeline throughput. The performance of the architecture is studied by implementing Xilinx Virtex V technology based FPGA with DSP 48E. Throughput achieved based on this VLSI architecture is 5.21 Gbits/s with a total resource utilization of 4058BELs.     

Real-time processing and compression of DNA microarray images.

In this paper, we present a pipeline architecture specifically designed to process and compress DNA microarray images. Many of the pixilated image generation methods produce one row of the image at a time. This property is fully exploited by the proposed pipeline that takes in one row of the produced image at each clock pulse and performs the necessary image processing steps on it. This will remove the present need for sluggish software routines that are considered a major bottleneck in the microarray technology. Moreover, two different structures are proposed for compressing DNA microarray images. The proposed architecture is proved to be highly modular, scalable, and suited for a standard cell VLSI implementation.     

MULTI-LEVEL FILTER FOR INFRARED IMAGE PROCESSING

This paper presents a new multi-level filter algorithm and its corresponding VLSI architecture for infrared image processing. The algorithm eliminates the phenomena of splitting targets by inserting Gaussian pyramid processing. Owning three filter paths, the proposed filter VLSI architecture can enhance small targets with different size in infrared images. This architecture has been implemented using SMIC 0.35μm 4-layer CMOS technology. The test result shows that the filter chip not only effectively suppresses background, eliminates noise and enhances small targets in an infrared image, but also meets infrared image real-time processing requirement(5M ～ 10M pixels/s). The implemented filter chip consists of 60,284 gates and 8K SRAM, operates at 50MHz.     

Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Packet Transform

This brief presents a novel very large-scale integration (VLSI) architecture for discrete wavelet packet transform (DWPT). By exploiting the in-place nature of the DWPT algorithm, this architecture has an efficient pipeline structure to implement high-throughput processing without any on-chip memory/first-in first out access. A folded architecture for lifting-based wavelet filters is proposed to compute the wavelet butterflies in different groups simultaneously at each decomposition level. According to the comparison results, the proposed VLSI architecture is more efficient than the previous proposed architectures in terms of memory access, hardware regularity and simplicity, and throughput. The folded architecture not only achieves a significant reduction in hardware cost but also maintains both the hardware utilization and high-throughput processing with comparison to the direct mapped tree-structured architecture     

An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV

Fractional Motion Estimation (FME) in high-definition H.264 presents a significant design challenge in terms of memory bandwidth, latency and area cost as there are various modes and complex mode decision flow, which require over 45% of the computation complexity in the H.264 encoding process. In this paper, a new high-performance VLSI architecture for Fractional Motion Estimation (FME) in H.264/AVC based on the full-search algorithm is presented. This architecture is made up of three different pipeline processors to establish a trade-off between processing time and hardware utilization. The computing scheme based on a 4-pixel interpolation unit with a 10-pixel input bandwidth is capable of processing a macroblock (MB) in 870 clock cycles. The final VLSI implementation only requires 11.4 k gates and 4.4kBytes of RAM in a standard 180 nm CMOS technology operating at 290 MHz. Our design generates the residual image and the best MVs and mode in a high throughput and low area cost architecture while achieving enough processing capacity for 1080HD (1920 × 1088@30fps) real-time video streams.     

Enhanced multi-level filter algorithm and its VLSI architecture

This paper presents an enhanced multi-level filter algorithm and its Very Large Scale Integration (VLSI) architecture for infrared image processing. The modified multi-level filter algorithm resolves the splitting targets problem using Gaussian pyramid processing. Owning three filtering paths, the proposed VLSI architecture of the filter can simultaneously enhance small targets with different sizes in infrared images. Some design techniques in implementing hardwired multiplication, subsample and asynchronous FIFO have been presented. This VLSI architecture has been implemented using Semiconductor Manufacturing International Corporation (SMIC) 0.35?µm 4-layer CMOS technology. The simulation results show that it not only effectively suppresses background, eliminates noise and enhances small targets in an infrared image comparing with other small target detective methods, but also meets infrared image real-time processing requirements (5?M?～?10?M pixels/s). The implemented filter chip consists of 60,284 gates and 8?K Static Random Access Memory (SRAM), operates at 50?MHz.     

MQ编码算法优化及高速VLSI结构设计与实现

传统的JPEG2000MQ编码器串行编码效率低下,同时现有的多上下文并行编码的MQ编码器占用资源过大.本文对MQ编码算法中的运算流程,索引值和概率估计值的求解函数,条件交换和重归一化算法等四个方面进行了优化,减弱了上下文之间的依赖性,简化了条件交换和重归一化算法的复杂度.依据该算法,本文提出了一种高速的MQ编码器VLSI结构,实验结果表明,本文提出的MQ编码器VLSI结构能够工作在532.91MHz,吞吐率为532.91 Msymbols/sec,相比Dyer提出的Brute force with modified结构,工作频率提高1倍,吞吐量提高近27%,且面积仅为其四分之一.     

二维离散5/3小波变换并行VLSI结构设计

提出了一种基于提升算法的二维离散5/3小波变换(DWT)高效并行VLSI结构设计方法。该方法使得行和列滤波器同时进行滤波,采用流水线设计方法处理,在保证同样的精度下,大大减少了运算量,提高了变换速度,节约了硬件资源。该方法已通过了VerilogHDL行为级仿真验证,可作为单独的IP核应用在JPEG2000图像编、解码芯片中。该结构可推广到9/7小波提升结构。     

应用于JPEG2000的5/3提升小波的VLSI结构设计

提出一种基于提升算法（lifting scheme）实现JPEG2000编码系统中的二维离散小波变换（Discrete Wavelet Transform）的并行阵列式的VLSI结构设计方法.该结构由一个行处理器和一个列处理器组成,行、列处理器通过时分复用同时进行滤波,用优化的移位加操作替代乘法操作,采用嵌入式数据延拓算法处理边界延拓.整个结构采用流水线设计方法,减少了运算量,提高了硬件资源利用率,该结构可应用于JPEG2000图像编码芯片中.     

高性能全流水线可控参数JPEG-LS编码器实现

提出了一种高性能的JPEG-LS无损/近无损图像压缩算法VLSI实现结构.通过对JPEG-LS算法瓶颈的分析,针对算法中不利于流水线实现的场景缓存部分,采用了一种信号量集机制避免流水线等待.全流水线结构保证了算法实现可以满足高速图像传感器系统的吞吐量需求.同时通过高度参数化的设计,系统可以动态调整和优化算法参数,使压缩效果和效率适应不同的运行环境.算法在FPGA平台通过验证,并得到了接近甚至超过其他ASIC实现的性能.     

JPEG2000并行阵列式小波滤波器的VLSI结构设计

提出一种基于提升算法实现JPEG2000编码系统中的二维离散小波变换(Discrete Wavelet Transform)的并行阵列式的VLSI结构设计方法.利用该方法所得结构由两个行处理器,一个列处理器以及少量行缓存组成;行列处理器内部是由并行阵列式的处理单元组成;能使行和列滤波器同时进行滤波,用优化的移位加操作替代乘法操作.整个结构采用流水线的设计方法处理,在保证同样的精度下,大大减少了运算量和提高了硬件资源利用率,几乎达到100％,加快了变换速度,也减少了电路的规模.该结构对于N×N大小的图像,处理速度达到O(N²/2)个时钟周期.二维离散小波滤波器结构已经过FPGA验证,并可作为单独的IP核应用于正在开发的JPEG2000图像编解码芯片中.     

高精度二维DCT的结构优化算法研究及FPGA实现

提出了一种基于5级流水线的高精度向量乘法器的二维DCT VLSI结构.采用一维DCT行处理,转置RAM存储器,一维DCT列处理的流水线结构代替复用一维DCT算法以提高速度,并且在一维DCT算法模块中,对于系数乘法,采用并行乘法的结构,可以进一步提高运算速度.在高精度方面,采用移位的方案,精度精确到小数点后5位,满足高精...     

基于DSP的嵌入式汉语文语转换系统及其VLSI设计方案

简要讨论了嵌入式文语转换(ETTS)系统的概念.介绍了一个基于DSP实时实现的嵌入式汉语文语转换(ECTTS)系统.基于DSP实现的结果,分析了ECTTS系统的VLSI实现方案,提出了基于动态内存管理的ECTTS系统前端处理VLSI实现方案,基于解码语音帧的ECTTS系统后端合成VLSI实现框架并对ECTTS系统的VLSI实现中的存储器及总线结构进行了讨论.     

Evaluation architecturale VLSI de systèmes standard de codage ďimages

Image coding systems currently undergoing standardisation within ISO and CCITT are the final outcome of a process of incremental improvements to classical hybrid (transform-predictive) algorithms. The task of VLSI architecture synthesis for these complete systems is made somewhat awkward due to the unstructured, irregular and non-modular nature of these algorithms. An ad hoc methodology for pruning the architectural search space, directed by the goal of minimizing the overall internal memory, leads to a strongly control-flow solution, using a pipeline scheme more efficient than with the original signal-flow graph. A generic image coding processor using a parallel programmable architecture is another solution. It may be inferred that second generation image coding techniques should be designed with massive fine-grain parallelism in view, if they are to take advantage of the full potential of dedicated VLSI implementations.     

FPGA based multi-channel variable-length FFT implementation

High-speed real-time digital frequency analysis is one major field of Fast Fourier Transform (FFT) application, such as Synthetic Aperture Radar(SAR) processing and medical imaging. In SAR processing, the image size could be 4 k×4 k in normal and it has become larger over the years. In the view of real-time, extensibility and reusable characteristics, an Field Programmable Gate Array(FPGA) based multi-channel variable-length FFT architecture which adopts radix-2 butterfly algorithm is proposed in this paper. The hardware implementation of FFT is partially reconfigurable architecture. Firstly, the proposed architecture in the paper has flexibility in terms of chip area, speed, resource utilization and power consumption. Secondly, the proposed architecture combines serial and parallel methods in its butterfly computations. Furthermore, on system-level issue, the proposed architecture takes advantage of state processing in serial mode and data processing in parallel mode. In case of sufficient FPGA resources, state processing of serial mode mentioned above is converted to pipeline mode. State processing of pipeline mode achieves high throughput.     

Edge‐Preserving Algorithm for Block Artifact Reduction and Its Pipelined Architecture

This paper presents a new edge‐protection algorithm and its very large scale integration (VLSI) architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge‐protection maps. Based on these maps, a two‐step adaptive filter which includes offset filtering and edge‐preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory‐reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is verified on FPGA Cyclone II and implemented using the ANAM 0.25 µm CMOS cell library. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details. The PSNR performance of our algorithm using pixel classification is better than that of previous algorithms using block classification.     

VLSI for high-performance graphic control utilizing multiprocessor architecture

This paper describes the VLSI for high-performance graphic control which utilizes two-level multiprocessor architecture. The VLSI chip is constructed of multiprocessor modules processing in parallel, and each processor module is constructed of multiexecutors using pipeline processing. This dedicated VLSI chip, designated as advanced CRT controller (ACRTC), has three processor modules, each independently controlling drawing, display, and timing. The graphic architecture of the drawing processor, which controls graphic drawing, is described. A high-level graphic language based on anX-Ycoordinate system is adopted. High-speed drawing is realized (drawing rate is 500 ns/pixel for drawing a line) by pipeline processing with three executors, the logical address executor, physical address executor, and color data executor.     

Architectures for finite radon transform

Two VLSI architectures for the finite Radon transform are presented. The first is a reference architecture using memory blocks and the second is a memoryless architecture. The proposed architectures use 7/spl times/7 size image blocks and are prototyped for processing the CIF image sequence. The simulation and synthesis results show that the core speeds of the two proposed architectures are around 100 and 82 MHz, respectively.