共查询到20条相似文献,搜索用时 31 毫秒
1.
Mohammad Hossein Zarifi Shahin Farshchi Javad Frounchi 《Analog Integrated Circuits and Signal Processing》2011,68(3):349-355
High-fidelity recording of neural signals requires varying levels of signal gain to capture low-amplitude single-unit activity
in the presence of high-amplitude population activity. A floating-point approach has been used to widen the dynamic range
of analog-to-digital converters (ADC) designed for this application. In this paper we present an ADC, designed for multi-channel,
portable neural signal recording systems. To achieve low power consumption, small die area and wide dynamic range, an ADC
based on a time-based algorithm, combined with a floating-point pipelined structure has been designed and simulated. A conventional
variable-gain amplifier (VGA) stage has been eliminated in favor of a reference-current in a time-based ADC architecture.
The 12-b pipelined time-based floating-point ADC has been designed with a 7-b mantissa and an exponent that provides an additional
5 bits of dynamic range. The mantissa is determined by a uniform 7-b pipelined time-based analog to digital converter. The
ADC chip was designed and simulated in a 90 nm CMOS process, which occupies an active area of 360 μm × 550 μm, and consumes
7.8 μW at 1.2 V in full-scale conversion. 相似文献
2.
Daisuke Miyazaki Shoji Kawahito 《Analog Integrated Circuits and Signal Processing》2000,25(3):235-244
This paper presents a new scheme of a low-power area-efficient pipelined A/D converter using a single-ended amplifier. The proposed multiply-by-two single-ended amplifier using switched capacitor circuits has smaller DC bias current compared to the conventional fully-differential scheme, and has a small capacitor mismatch sensitivity, allowing us to use a smaller capacitance. The simple high-gain dynamic-biased regulated cascode amplifier also has an excellent switching response. These properties lead to the low-power area-efficient design of high-speed A/D converters. The estimated power dissipation of the 10-b pipelined A/D converter is less than 12 mW at 20 MSample/s. 相似文献
3.
A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC 总被引:3,自引:0,他引:3
Limotyrakis S. Kulchycki S.D. Su D.K. Wooley B.A. 《Solid-State Circuits, IEEE Journal of》2005,40(5):1057-1067
A pipelined analog-to-digital converter (ADC) architecture suitable for high-speed (150 MHz), Nyquist-rate A/D conversion is presented. At the input of the converter, two parallel track-and-hold circuits are used to separately drive the sub-ADC of a 2.8-b first pipeline stage and the input to two time-interleaved residue generation paths. Beyond the first pipeline stage, each residue path includes a cascade of two 1.5-b pipeline stages followed by a 4-b "backend" folding ADC. The full-scale residue range at the output of the pipeline stages is half that of the converter input range in order to conserve power in the operational amplifiers used in each residue path. An experimental prototype of the proposed ADC has been integrated in a 0.18-/spl mu/m CMOS technology and operates from a 1.8-V supply. At a sampling rate of 150 MSample/s, it achieves a peak SNDR of 45.4 dB for an input frequency of 80 MHz. The power dissipation is 71 mW. 相似文献
4.
This paper presents a 10-bit 100-MSample/s analog-to-digital(A/D) converter with pipelined folding architecture.The linearity is improved by using an offset cancellation technique and a resistive averaging interpolation network.Cascading alleviates the wide bandwidth requirement of the folding amplifier and distributed interstage track/hold amplifiers are used to realize the pipeline technique for obtaining high resolution.In SMIC 0.18μm CMOS,the A/D converter is measured as follows:the peak integral nonlinearity and differential nonlinearity are±0.48 LSB and±0.33 LSB,respectively.Input range is 1.0 VP-P with a 2.29 mm2 active area.At 20 MHz input @ 100 MHz sample clock,9.59 effective number of bits,59.5 dB of the signal-to-noise-and-distortion ratio and 82.49 dB of the spurious-free dynamic range are achieved.The dissipation power is only 95 mW with a 1.8 V power supply. 相似文献
5.
A modified RSD algorithm has been implemented in a switched-current pipelined A/D converter. The offset insensitivity of the RSD Converter reduces the effect of several nonidealities proper to current copier cells. Moreover, the benefits resulting from the large tolerances inherent to the RSD algorithm and the pipelined architecture result in an improved conversion rate. Measurements on a first prototype give an integral nonlinearity error less than 0.8 LSB for 10-bit accuracy. Power dissipation is 20 mW and silicon area is 2.5 mm2 . The measured sampling rate is 550 kS/s. It is an improvement by a factor of twenty compared to known equivalent CMOS switched-current converters. It is nevertheless still well below the predicted conversion rate of 4.5 MHz, which should be obtained once this A/D converter is integrated into an analog front-end. Full compatibility with standard digital technologies makes this kind of converter attractive for low power, medium-fast converters with 10-bit accuracy 相似文献
6.
A 10-b 100-Msample/s pipelined subranging analog-digital converter (ADC) has been achieved. Such technologies as a pipelined subranging scheme, a track-and-hold amplifier (THA) with current-switching sampling gates, a 94-dB dc open-loop gain, a 335-MHz unity-gain frequency op amp, and a carry-look-ahead adder for digital error correction are presented. The 3.4-mm×5.6-mm ADC chip was fabricated using a 0.8-μm BiCMOS process and operates with 950-mW power dissipation from a single -5-V power supply 相似文献
7.
Real P. Robertson D.H. Mangelsdorf C.W. Tewksbury T.L. 《Solid-State Circuits, IEEE Journal of》1991,26(8):1103-1109
A 10-b pipelined analog-to-digital converter (ADC) is presented which makes extensive use of differential current-mode signals. The converter samples at 20 MHz and has an analog bandwidth exceeding 100 MHz. The architecture incorporates the design of a wide-bandwidth, fully differential current-in, current-out track-and-hold (T/H) amplifier differential flash A/D converters, and fully segmented D/A converters. A unique reference distribution technique allows precise trimming of the gains of the DACs and flash converters. The converter is built on a 2-μm BiCMOS process with thin film resistors 相似文献
8.
A 13-b 5-MHz pipelined analog-to-digital converter (ADC) was designed with the goal of minimizing power dissipation. Power was reduced by using a high swing residue amplifier and by optimizing the per stage resolution. The prototype device fabricated in a 1.2 μm CMOS process displayed 80.1 dB peak signal-to-noise plus distortion ratio (SNDR) and 82.9 dB dynamic range. Integral nonlinearity (INL) is 0.8 least significant bits (LSB), and differential nonlinearity (DNL) is 0.3 LSB for a 100 kHz input. The circuit dissipates 166 mW on a 5 V supply 相似文献
9.
A fully-differential, 10-b, 40-Msample/s pipelined analog-to-digital converter (ADC) has been developed and tested. The converter exhibits a signal-to-(noise+distortion) ratio (SNDR) of 57.1 dB and consumes <400 mW of power from a single 5 V supply. The converter can digitize not only a fully-differential but also a single-ended input signal over a wide input range with little variation in converter performance. In addition, a full-power bandwidth (FPBW) of >250 MHz is made possible with the open-loop sampling scheme 相似文献
10.
Dobberpuhl D.W. Witek R.T. Allmon R. Anglin R. Bertucci D. Britton S. Chao L. Conrad R.A. Dever D.E. Gieseke B. Hassoun S.M.N. Hoeppner G.W. Kuchler K. Ladd M. Leary B.M. Madden L. McLellan E.J. Meyer D.R. Montanaro J. Priore D.A. Rajagopalan V. Samudrala S. Santhanam S. 《Solid-State Circuits, IEEE Journal of》1992,27(11):1555-1567
A 400-MIPS/200-MFLOPS (peak) custom 64-b VLSI CPU is described. The chip is fabricated in a 0.75-μm CMOS technology utilizing three levels of metalization and optimized for 3.3-V operation. The die size is 16.8 mm×13.9 mm and contains 1.68 M transistors. The chip includes separate 8-kbyte instruction and data caches and a fully pipelined floating-point unit (FPU) that can handle both IEEE and VAX standard floating-point data types. It is designed to execute two instructions per cycle among scoreboarded integer, floating-point, address, and branch execution units. Power dissipation is 30 W at 200-MHz operation 相似文献
11.
A 14-bit digital-to-analog converter based on a fourth-order multibit sigma-delta modulator is described. The digital modulator is pipelined to minimize both its power dissipation and design complexity. The 6-bit output of this modulator is converted to analog using 64 current-steering cells that are continuously calibrated to a reference current. This converter achieves 85-dB dynamic range at 5-MHz signal bandwidth, with an oversampling ratio of 12. The chip was fabricated in a 0.5-/spl mu/m CMOS technology and operates from a single 2.5-V supply. 相似文献
12.
A power and area efficient technique to reduce metastability errors in high-speed flash A/D converters is described. Pipelining to reduce error rates in an n-bit flash converter is accomplished with a bit pipeline scheme requiring n latches per pipeline stage instead of 2 n-1. A 7-b, 80 MHz prototype converter is implemented in 1.2-μm CMOS with measured metastability error rates of less than 10 -12 errors/cycle. The measured power is 307.2 mW with an 80-MHz sampling frequency. Without metastability error reduction circuitry, the estimated metastability error rate for the converter is 10-4 errors/cycle. Achieving an equivalent error rate with two pipeline stages of 2n-1 latches would require 3.48 times the power for the metastability error reduction circuitry. This corresponds to a reduction in total power by a factor of 1.24 compared with the comparator pipelined converter for Nyquist frequency inputs 相似文献
13.
This paper describes a 10-bit,50-MS/s pipelined A/D converter(ADC) with proposed area- and power-efficient architecture.The conventional dedicated sample-hold-amplifier(SHA) is eliminated and the matching requirement between the first multiplying digital-to-analog converter(MDAC) and sub-ADC is also avoided by using the SHA merged with the first MDAC(SMDAC) architecture,which features low power and stabilization.Further reduction of power and area is achieved by sharing an opamp between two successive pi... 相似文献
14.
Dyer K.C. Daihong Fu Lewis S.H. Hurst P.J. 《Solid-State Circuits, IEEE Journal of》1998,33(12):1912-1919
Analog background calibration using adaptive signal processing, an extra channel, and mixed signal integrators matches the offsets and gains of time-interleaved channels in a 10-b 40-Msample/s pipelined analog-to-digital converter. With monolithic background calibration, the peak signal-to-noise-and-distortion ratio is 58 dR, and power dissipation is 650 mW from 5 V. The active area is 47 mm2 in 1 μm CMOS 相似文献
15.
16.
Hae-Seung Lee 《Solid-State Circuits, IEEE Journal of》1994,29(4):509-515
This paper discusses fully digital error correction and self-calibration which correct errors due to capacitor mismatch, charge injection, and comparator offsets in algorithmic A/D converters. The calibration is performed without any additional analog circuitry, and the conversion does not need extra clock cycles. This technique can be applied to algorithmic converter configurations including pipelined, cyclic, or pipelined cyclic configurations. To demonstrate the concept, an experimental 2-stage pipelined cyclic A/D converter is implemented in a standard 1.6-μm CMOS process. The ADC operates at 600 ks/s using 45 mW of power at ±2.5 V supplies. The active die area excluding the external logic circuit is 1 mm2. Maximum DNL of ±0.6 LSB and INL of ±1 LSB at a 12-b resolution have been achieved 相似文献
17.
Brooks T.L. Robertson D.H. Kelly D.F. Del Muro A. Harston S.W. 《Solid-State Circuits, IEEE Journal of》1997,32(12):1896-1906
A low-noise multibit sigma-delta analog-to-digital converter (ADC) architecture suitable for operation at low oversampling ratios is presented. The ADC architecture uses an efficient high-resolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency. A 16-b implementation of the architecture, fabricated in a 0.6-μm CMOS process, cascades a second-order 5-b sigma-delta modulator with a four-stage 12-b pipelined ADC and operates at a low 8X oversampling ratio. Static and dynamic linearity of the integrated ADC are improved through the use of dynamic element matching techniques and the use of bootstrapped and clock-boosted input switches. The ADC operates at a 20 MHz clock rate and dissipates 550 mW with a 5 V/3 V analog/digital supply. It achieves an SNR of 89 dB over a 1.25-MHz signal bandwidth and a total harmonic distortion (THD) of -98 dB with a 100-kHz input signal 相似文献
18.
A 6-bit 800-MS/s pipelined A/D converter (ADC) achieves SNDR and SFDR of 33.7 dB and 47.5 dB, respectively. Employing voltage-mode open-loop amplifiers in gain stages, global gain control techniques, and two-bank-interleaved architecture, the proposed pipelined A/D converter relaxes stringent design tradeoffs between speed and power. Fabricated in a 0.18-mum CMOS technology, the ADC consumes 105 mW from a 1.8-V power supply while the active area is only 0.5 mm2 相似文献
19.
20.
Jarvinen J.A.M. Saukoski M. Halonen K.A.I. 《IEEE transactions on circuits and systems. I, Regular papers》2008,55(3):730-740
This paper describes a ratio-independent algorithmic analog-digital (A/D) converter architecture that is insensitive to capacitance ratio, amplifier offset voltage, amplifier input parasitics, and flicker noise. It requires only one differential amplifier, a dynamic latch, six capacitors, 36 switches, and some digital logic. The prototype 12-bit, 40-kS/s A/D converter (ADC) with an active die area of 0.041 mm2 is implemented in a 0.13-mum CMOS. The power dissipation is minimized using a dynamically biased operational amplifier. With a 68.4-muW power dissipation, the ADC achieves 80.2-dB spurious-free dynamic range and 63.3-dB signal-to-noise and distortion ratio. 相似文献