用于光学向量矩阵乘法器的光源阵列系统

对用于光学向量矩阵乘法器的16路阵列光源和驱动电路进行了系统的研究。提出了采用商用分布式反馈激光器（DFB）和16路光纤阵列耦合的方式构造阵列光源模块,并且在驱动电路中设计了功率反馈自校正调节算法, 解决了由于当前激光器制造工艺条件的限制而造成的各路激光器之间的阈值电流和P-I转换效率等参数差异问题。实现了光源系统各个通道间的输入向量数据和输出光强之间的一致性映射。实验结果证明,所研究开发的光源阵列不仅成本低,而且数据源信号的高频响应性能良好,保证了光学向量矩阵乘法器运算性能的稳定性和准确性。     

数字阵列乘法器的算法及结构分析

对数字阵列乘法器的移位加算法、Pezaris算法、Baugh-Wooley算法的性能进行了分析,讨论其各自的特点;指出进一步提高并行快速乘法器性能的研究重点。     

光学多比特矩阵乘法器

本文提出并实现了一种利用改进的符号数(MSD)算法和多窗口解码光学符号代换法则(MW-OSSR)实现多比特矩阵相乘的光学方法,它具有精度高和速度快的特点。实验中的计算速度为每秒实现两个2×2阶32比特的MSD矩阵相乘。     

换能器阵列的传输线矩阵方法分析

介绍将传输线矩阵方法应用于声光换能器阵列的辐射特性分析，给出了与解析方法一致的数值结果。表明传输线矩阵方法可以用于对声学器件的工作过程进行时域数值模拟。     

光学并行矩阵乘法器的实验研究

本文介绍全并行矩阵乘法的实验研究过程和结果,运算充分利用光的并行性,做一次三个矩阵乘法或二维变换只要一个系统时钟周期。文中讨论了误差的来源和误差的消除方法,给出了两个和三个(正实数)矩阵乘法的实验结果(模拟运算),两个矩阵相乘的精度为1.2％,三个矩阵相乘的精度为1.23％。     

流水线阵列乘法器的功耗分析和优化

针对流水线结构阵列乘法器，分别采用寄存器翻转统计和门级翻转率统计的方法进行了功耗分析，创新地提出了一种通过增加判断逻辑进行数据预分流以实现功耗优化的方法。实验结果证明，这种优化方法能够带来明显的功耗节省。类似方法也可普遍用于逻辑行为对称但实现结构不对称的数据通路单元的低功耗设计实现中。     

基于压电阵列的结构状态探测模块软件开发

压电传感器由于线性范围大、响应快、能量转换率高、稳定可靠,在用于结构状态探测上具有明显的优越性。采用压电片阵列对结构的机械振动进行监测,通过测得的结构动态应变信息来反映结构的损伤程度和损伤位置,将结构健康数据及时传输、处理,对结构健康监测具有重要研究意义与实际价值。文章在实现压电阵列探测模块的基础上,通过单片机程序软件开发实现数据通信。     

阵列乘法器通路时延故障的内建自测试

阵列乘法器因高度集成和高速运行,容易受到时延故障的困扰.该文对阵列乘法器的通路时延故障提出了一种用累加器实现的以单跳变序列作为测试序列的内建自测试方案.已有的理论和实践表明采用单跳变测试序列比多跳变序列具有更高的测试鲁棒性.同时,该文的测试方案在测试通路覆盖率和测试向量数之间做到了兼顾.仿真结果表明这种单跳变测试序列具有高测试通路覆盖率.此外,测试生成通过系统已有累加器的复用可节省硬件成本开销.     

基于半导体光放大器的光学向量矩阵乘法器的实现方法

提出了一种基于半导体光放大器(SOA)的光学向量矩阵乘法器(OVMM)的实现方法。与传统的向量矩阵乘法器相比,本文方法采用的是非空间光的实现方案,且SOA的增益补偿作用可对计算所得的光功率进行校正,从而提高计算精度。对提出的方法进行了1×2向量与2×2矩阵乘法运算的实验验证,结果表明可以实现向量矩阵乘法器的运算功能。利用SOA的大范围增益可调特性,可有效提高信号动态范围,利于多路信号间均匀性的改善,且易于集成。     

指纹识别专用集成电路中乘法器模块的设计

介绍了一种用于指纹识别专用集成电路(ASIC)的乘法器模块的设计.该乘法器模块能够处理32位的有符号数、无符号数的乘法和乘加运算.电路采用基-4的Booth编码以及改进型压缩器阵列结构.采用提出的迭代和阵列结合的结构算法,可节省芯片面积30%,提高工作频率24%.模块电路在TSMC 0.25 μm工艺上实现.该乘法器模块易于移植到其他数字处理系统.     

CSSA-低功耗Montgomery模乘的环形脉动阵列

文章提出了一种环形脉动阵列CSSA（Circular Structured Systolic Array），用于实现Montgomery模乘算法MMM（Montgomery Modular Multiplication）。该阵列采用循环结构，迭代计算。仿真结果表明，与基于一维脉动阵列的MMM硬件实现相比，该结构牺牲了运算时间，但是降低了功耗和芯片面积（本文实现的两个例子，功耗和芯片面积均减少了约97％）。并且，处理单元的数量可配置，以平衡速度和功耗。     

大数模乘脉动阵列的FPGA细粒度映射实现

通过分析FPGA可配置逻辑块的细致结构,提出了一种基于FPGA的细粒度映射方法,并使用该方法高效实现了大数模乘脉动阵列.在保持高速计算特点的同时,将模乘脉动阵列的资源消耗降低为原来的三分之一.在低成本的20万门级FPGA器件中即可实现1024位模乘器.该实现每秒可进行20次RSA签名.如果换用高性能FPGA,签名速度更可提高至每秒40次.     

A Fault Tolerant Approach for FPGA Embedded Processors Based on Runtime Partial Reconfiguration

The ever increasing adoption of field programmable devices in various application domains for building complex embedded systems based on FPGA processors along with the reliability issues having emerged for FPGA devices built with the latest nanometer technologies, have raised the need for new fault tolerant techniques in order to improve dependability and extend system lifetime. In addition, the runtime partial reconfiguration technology highly mature in the modern FPGA families along with the availability of unused programmable resources in most FPGA designs provide new and interesting opportunities to build advanced fault tolerance mechanisms. In this paper, we exploit the dynamic reconfiguration potential of today’s FPGA architectures and the advances in the related design support tools and we propose a fault-tolerant approach for FPGA embedded processors based on runtime partial reconfiguration. According to the proposed methodology, the processor core is partitioned into reconfigurable modules and each module is duplicated to implement a concurrent error detection mechanism. Precompiled configurations containing spare resources are generated for each duplicated module and are used to repair at runtime the defective modules. Also, a fault tolerance scheme for the proxy logic of the reconfigurable modules, which cannot move in the alternative configurations along with the rest logic, is proposed. Moreover, a compression method for the alternative partial bitstreams, which significantly reduces the high storage space requirements of the proposed approach, is presented. Two different hardware decompression schemes have been implemented in a Virtex-5 device and compared in terms of area overhead and decompression latency. Furthermore, a thorough examination has been performed, regarding how the percentage of the spare resources and their allocation in the reconfigurable regions affect the compression efficiency and the processor performance. Finally, the proposed approach has been demonstrated in three different components – ALU, multiplier-accumulator, and instruction-fetch unit – of an open-source embedded processor.     

Power Consumption of Fault Tolerant Busses

On-chip interconnects in very deep submicrometer technology are becoming more sensitive and prone to errors caused by power supply noise, crosstalk, delay variations and transient faults. Error-correcting codes (ECCs) can be employed in order to provide signal transmission with the necessary data integrity. In this paper, the impact of ECCs to encode the information on a very deep submicrometer bus on bus power consumption is analyzed. To fulfill this purpose, both the bus wires (with mutual capacitances, drivers, repeaters and receivers) and the encoding-decoding circuitry are accounted for. After a detailed analysis of power dissipation in deep submicrometer fault-tolerant busses using Hamming single ECCs, it is shown that no power saving is possible by choosing among different Hamming codes. A novel scheme, called dual rail, is then proposed. It is shown that dual rail, combined with a proper bus layout, can provide a reduction of energy consumption. In particular, it is shown how the passive elements of the bus (bottom and mutual wire capacitances), active elements of the bus (buffers) and error-correcting circuits contribute to power consumption, and how different tradeoffs can be achieved. The analysis presented in this paper has been performed considering a realistic bus structure, implemented in a standard 0.13-mum CMOS technology.     

计算机系统容错技术研究

在现代计算机快速发展并且对人们的工作和生活影响越来越大的前提下,人们对于计算机系统容错的需求就越来越强烈,要求计算机系统有良好的容错性能,进而保障计算机系统的正常运行。因此,需要对计算机系统软硬件的容错方法进行分析,进而探索出几种较为实用的计算机容错系统的体系结构,希望能够促进计算机系统容错性能的大幅提升。     

Performance-Scalable Array Architectures for Modular Multiplication

Modular multiplication is a fundamental operation in numerous public-key cryptosystems including the RSA method. Increasing popularity of internet e-commerce and other security applications translate into a demand for a scalable performance hardware design framework. Previous scalable hardware methodologies either were not systolic and thus involved performance-degrading, full-word-length broadcasts or were not scalable beyond linear array size. In this paper, these limitations are overcome with the introduction of three classes of scalable-performance modular multiplication architectures based on systolic arrays. Very high clock rates are feasible, since the cells composing the architectures are of bit-level complexity. Architectural methods based on both binary and high-radix modular multiplication are derived. All techniques are constructed to allow additional flexibility for the impact of interconnect delay within the design environment.     

容错的并行多重网格算法

高性能计算机上并行程序用到的结点越来越多,而在程序运行期间中发生结点失效的概率也随之增大.对于计算时间很长的程序,容忍结点失效的容错能力显得尤为重要.并行多重网格算法(MG)被广泛用于求解大型工程和物理问题中的偏微分方程组的数值解.为了实现MG算法的容错能力,提出了一种基于容错MPI的容错并行多重网格算法FT-MG.实验结果表明:FT-MG算法在引入少许开销的条件下实现了MG算法的容错能力.     

A Fault Tolerant Technique for FPGAs

In this paper we present a fault tolerant (FT) technique for field programmable gate arrays (FPGAs) that is based on incrementally reconfiguring circuits and applications that have been previously placed and routed. Our technique targets both logic faults and interconnect faults, and our algorithms can be applied to either static or run-time reconfigurable FPGAs. The algorithm for reconfiguring designs in the presence of logic faults uses a matching technique. The matching technique requires no preplaced, spare logic resources and is capable of handling groups of faults. Experimental results indicate there is little or no impact on circuit performance for low numbers of reconfigured logic blocks. For interconnect faults, we present a rip-up and reroute strategy. Our strategy is based on reading back the FPGA configuration memory, so no netlist is required for rerouting around faulty resources. Experimental results indicate high incremental routability for low numbers of interconnect faults. We also lay the foundation for applying our approach to yield enhancement.     

Fault Tolerant Single Error Correction Encoders

Soft errors are an important issue for circuit reliability. To mitigate their effects on the system functionality, different techniques are used. In many cases Error Correcting Codes (ECC) are used to protect circuits. Single Error Correction (SEC) codes are commonly used in memories and can effectively remove errors as long as there is only one error per word. Soft errors however may also affect the circuits that implement the Error Correcting Codes: the encoder and the decoder. In this paper, the protection against soft errors in the ECC encoder is studied and an efficient fault tolerant implementation is proposed.     

Petri网矩阵法用于数字电路故障诊断

本文介绍数字电路的Ｐｅｔｒｉ网络模型,Ｐｅｔｒｉ网的矩阵能压缩存禽数字电路的拓扑,Ｐｅｔｒｉ网的矩阵法在数字电路故障诊断中的应用。