一种新型仿生硬件容错系统——胚胎电子系统

本文介绍了一种从自然界获取灵感的新型容错设计方法--胚胎电子系统设计.它的容错原理是根据在生物细胞内部冗余结构里发现的自修复机制来实现的.胚胎电子系统,就是基于构造一个具有自检测和自修复能力的处理单元阵列的仿生硬件容错系统.本文阐述了这种容错方法的设计原理,介绍了该系统的基本结构,并通过一个设计实例的介绍来验证该方法的有效性.     

基于二维网孔互连网络的并行矩阵乘算法

矩阵乘法是数值分析领域中一种十分常用的基本运算，被广泛应用于模式识别、图像和信号处理。由于矩阵运算具有局部性、一致性的特点，特别适合用二维网孔并行计算机来实现。文章讨论了基于二维网孔互连网络的矩阵乘并行算法的实现，首先给出了一种正方网孔处理机阵列的并行算法，然后将其推广到长方网孔处理机阵列中。最后通过在LSMPP计算机的应用，证明算法是可行的、有效的。     

光学空间图形偏振编码器和数据寄存器——基于BSO电-光晶体的新型设计和应用

图形编码阵列逻辑是数字光计算中关键的结构的一种。这种结构把非线性逻辑运算分解成非线性编码和线性运算两部份。我们已经证实这种方法对二变量输入的二值图形,通过光学三重积,可以一次实现16种阵     

普遍故障下神经网络隐层冗余容错的分析与应用

隐层神经元冗余是提高神经网络容错性的一个有效的方法,在神经网络分类器的容错设计中,这一方法得到了良好的效果,对单故障可以做到完全容错.但是这一应用仅仅只能应用于输出层为硬限幅函数的前向网络,并且只证明了对网络中单故障有效.在实际应用中,网络中的各个节点和权值的故障往往是普遍存在的,因此本文提出了一种隐层冗余结构,对普遍故障存在下隐层神经元冗余容错方法做以评估,得出的结论是应用这种隐层神经元冗余结构可以减小网络的全局故障率;并提出了针对一般前向神经网络的实用的隐层神经元容错方法,这种方法可以有效地提高网络在普遍故障下的容错能力.     

一种稀疏表示的二维DOA降维估计新算法

提出了一种基于空间锥角降维的二维DOA稀疏分解估计新方法,解决了利用稀疏表示方法进行二维DOA估计时计算复杂度大的问题.根据L阵列的结构特性,引入空间锥角表示信号的二维DOA信息,构造空间锥角冗余字典,通过稀疏正则化求解实现空间锥角的估计,然后利用求解得到功率实现L阵列中两个子阵之间的空间锥角配对,从而达到对多来波的二维DOA估计的目的,其避免了方位角和俯仰角组合而造成冗余字典庞大的问题,极大地减少了稀疏分解的计算量.仿真和实测数据结果均验证了该方法的有效性和优越性,为进一步的工程应用奠定了基础.     

3D-IC中基于时分复用的TSV蜂窝容错设计

三维芯片(3D-IC)通过硅通孔(TSV)技术来实现电路的垂直互连,延续了摩尔定律,但在制造、绑定等过程中,TSV容易引入各类缺陷。添加冗余TSV是解决该问题的有效方法之一,但TSV面积开销大、制造成本高。提出一种基于时分复用(TDMA)的TSV蜂窝结构容错设计方案,它基于时间对信号TSV进行复用。实验结果表明,与一维链式TDMA结构相比,蜂窝TDMA结构提高了30%的故障覆盖率,并且故障覆盖率随着蜂窝阵列的扩展持续提升。在64TSV阵列中,与一维TDMA结构相比,蜂窝拓扑结构的面积开销降低了10.4%。     

时空DOA矩阵方法

本文提出了一种新的基于信号空时特征结构的高分辨二维DOA估计方法-时空DOA矩阵方法.该方法在保持原DOA矩阵方法无需二维谱峰搜索和参数配对等优点的基础上,利用阵元输出之间的互相关关系将空域的阵列观测数据变换到时空域,通过空时二维处理在时空域中衍生出大量虚拟阵元,从而大大减弱了传统方法中对阵列结构、排布方式和阵元一致性的约束,不需要匹配子阵,无冗余阵元与孔径损失,并适用于阵元排列不规则的阵列.仿真结果证明了该方法的有效性.     

一种改进的奇偶阵列结构运动估计器设计

提出了一种改进的奇偶阵列计算结构的运动估计器架构,该运动估计器利用了二维数据复用并能够实现全搜索法。设计了运动估计器的状态机控制逻辑,在其控制下,运动估计器的处理单元达到了100%的利用率。本运动估计器实现了高速、并行的运算,从而可以应用在高清视频的实时后处理等场合。     

方向依赖的阵元复增益条件下宽带chirp信号二维角估计

在方向依赖的阵元复增益条件下,该文提出一种宽带chirp信号二维角估计新方法。该方法基于信号时变阵列流形结构分析,构造出一种阵列流形时频变换,无需估计和补偿即可消除阵元幅相不一致误差的影响,实现宽带chirp信号二维角闭式解析估计。仿真实验表明了新方法的有效性。     

一种低冗余二维综合孔径辐射计天线阵列布局

干涉综合孔径微波辐射计是利用孔径合成技术实现高分辨率的无源微波雷达成像系统,天线阵的优化设计是系统设计中的一个关键问题.文章提出了一种利用一维低冗余线性阵列构造低冗余二维天线阵列的方法,并将其设计阵列的冗余度与常规'U'形、'T'形阵列的冗余度进行了分析比较.分析结果表明,当天线单元数目足够多时,文中提出的阵列布局方式比常规的'U'形、'T'形阵列布局方式可节省11%～19%的通道数目.     

FPGA-Based Real-Time Power Converter Failure Diagnosis for Wind Energy Conversion Systems

This paper discusses the design, implementation, experimental validation, and performances of a field-programmable gate array (FPGA)-based real-time power converter failure diagnosis for three-leg fault tolerant converter topologies used in wind energy conversion systems (WECSs). The developed approach minimizes the time interval between the fault occurrence and its diagnosis. We demonstrated the possibility to detect a faulty switch in less than 10 $muhbox{s}$ by using a diagnosis simultaneously based on a “time criterion” and a “voltage criterion.” To attain such a short detection time, an FPGA fully digital implementation is used. The performances of the proposed FPGA-based fault detection method are evaluated for a new fault tolerant back-to-back converter topology suited for WECS with doubly fed induction generator (DFIG). We examine the failure diagnosis method and the response of the WECS when one of the power switches of the fault tolerant back-to-back converter is faulty. The experimental failure diagnosis implementation based on “FPGA in the loop” hardware prototyping verifies the performances of the fault tolerant WECS with DFIG.      

Nucleus Plus容错功能扩充研究

Nucleus Plus是为实时嵌入式应用而设计的一个抢先式多任务操作系统，其95％的代码使用ANSIC写成，非常便于移植并能够支持大多数类型的处理器。本文根据容错管理软件的设计思想，提出了一种Nucleus Plus实时操作系统容错功能扩充方法，并在某航天三模冗余计算机平台上进行了验证。     

Fault tolerance in Clos–Knockout multicast ATM switch

In this paper, we propose a new architecture for multicast ATM switches with fault tolerant capability based on the Clos–Knockout switch. In the new architecture, each stage has one more redundant switch module. If one switch module is faulty, the redundant module would replace the faulty one. On the other hand, under the fault‐free condition, the redundant modules in the second and third stages will provide additional alternative internal paths, and hence improve the performance. The performance analysis shows that the cell loss probability is lower than the original architecture when all modules are fault free, and the reliability of the original architecture is improved. Copyright © 2002 John Wiley & Sons, Ltd.     

Clos-based fault tolerant multicast ATM switch

A Clos-based fault tolerant multicast ATM switch is proposed in which each stage has one more redundant switch module. If one switch module is faulty, the redundant module replaces the faulty module. On the other hand, even under fault-free conditions, the redundant modules in the second and third stages will provide additional alternative internal paths, and hence improve the performance     

下一代网络核心业务平台的可靠性分析

基于随机Petri网,提出了一种计算NGN核心业务平台可靠性的方法。对双机热备份容错系统和N 1互备份容错系统的硬件环境分别进行了可靠性建模与分析。提出了软件模块容错方法,并得到了该方法的软件模块可靠性表示方法;然后从软件模块的角度,对业务软件的可靠性进行了建模与分析。最后给出了一个实例,分析了NGN核心业务平台的硬件系统和业务软件是如何协作满足业务可靠性要求。     

Concurrent error detection in array multipliers forGF(2m) fields

Based on Lee-Lu-Lee's array multipliers and the RESO method, a concurrent error detection scheme in array multipliers for GF(2^m ) fields is presented and only one clock cycle is added. The fault tolerant capability in such array multipliers is also included and only two extra clock cycles are required     

Yield enhancement of bit level systolic array chips using fault tolerant techniques

Methods by which bit level systolic array chips can be made fault tolerant are discussed briefly. Using a simple analysis based on both Poisson and Bose-Einstein statistics we demonstrate that such techniques can be used to obtain significant yield enhancement. Alternatively, the dimensions of an array can be increased considerably for the same initial (nonfault tolerant) chip yield.     

Maintainability Considerations in a Fault Tolerant/Faultproof Systems Design

The maintainability, reliability, and availability of a computer system are closely bonded to insure continuing service of a system. The ability of a system to tolerate failures or faults while operating is a principal requirement of a fault tolerant system. A fault tolerant system's design must incorporate considerations for maintenance and reliability in order to provide its ultimate requirement-available operation. These factors are considered in the design philosophy presented in this paper, identified as FAULTPROOF. FAULTPROOF design incorporates redundancy, reliability, maintainability, and adaptability to augment normally accepted fault tolerant design. The design approach described utilizes a hierarchical interconnection mechanism, Intelligent Networked Partitioning, to isolate faulted components.     

Algorithm transformation methods to reduce the overhead of software-based fault tolerance techniques

This paper introduces a framework that tackles the costs in area and energy consumed by methodologies like spatial or temporal redundancy with a different approach: given an algorithm, we find a transformation in which part of the computation involved is transformed into memory accesses. The precomputed data stored in memory can be protected then by applying traditional and well established ECC algorithms to provide fault tolerant hardware designs. At the same time, the transformation increases the performance of the system by reducing its execution time, which is then used by customized software-based fault tolerant techniques to protect the system without any degradation when compared to its original form. Application of this technique to key algorithms in a MP3 player, combined with a fault injection campaign, show that this approach increases fault tolerance up to 92%, without any performance degradation.     

Distributed fault detection for modular and reconfigurable robots with joint torque sensing: A prediction error based approach

A distributed fault detection scheme for modular and reconfigurable robots (MRRs) with joint torque sensing is proposed in this paper. With the proposed scheme, the joint torque command is filtered and compared with a filtered torque estimate derived from the nonlinear dynamic model of MRR with joint torque sensing. Common joint actuator faults are considered with fault detection being performed independently for each joint module. The proposed fault detection scheme for each module does not require motion states of any other module making it an ideal modular approach for fault detection of modular robots. Experimental results have confirmed the effectiveness of the proposed fault detection scheme.