基于复用的SOC测试技术

复用不仅是SOC设计思想的核心,也是解决SOC测试的基础.本文在分析SOC的基本概念和特点的基础上,从复用的角度对现有的SOC测试方案进行分析和综述,并探讨了亟待解决的问题.     

基于复用的SOC测试集成和IEEE P1500标准

以复用核测试为目标的测试策略是解决SOC测试问题的基础.IEEE P1500标准是国际上正在制订的嵌入式核测试标准,该标准旨在简化核测试信息的复用,提高SOC级测试集成的效率.文章介绍了截至目前为止P1500标准的制订情况,包括嵌入式核测试的体系结构、P1500的标准化目标,以及P1500的两级服从认证等.     

SOC设计方法学和可测试性设计研究进展

随着微电子工艺技术和设计方法的发展，系统级芯片(SOC)设计成为解决日益增长的设计复杂度的主要方法。文章概述了SOC设计方法学和SOC可测试性设计的发展现状，阐述了目前SOC测试存在的和需要解决的问题，描述了目前开发的各种SOC测试结构和测试策略。最后，提出了今后进一步研究的方向。     

最新SOC测试的发展趋势

随着SOC芯片结构的复杂化，功能模块的多样化，SoC芯片的测试也面对诸多挑战，诸如测试资源和成本的兼顾。本文简单描述了现今SOC芯片的发展和趋势，以及相对应ATE测试系统的应对。     

一种基于JTAG的SOC测试电路设计及实现

提出了一种基于JTAG的新的测试电路设计思路.通过扩展JTAG指令,可以利用JTAG通信协议向SOC芯片中下载自定义的测试指令,并读回测试的最终结果.该方法可以对SOC内部的IP及存储器进行充分的功能测试,测试过程可灵活配置,可以快速定位测试中出现的问题.     

SOC测试结构优化研究

结合SOC测试结构的特点,采用量子进化算法对SOC测试结构进行优化.通过对量子进化算法中群体尺寸、旋转角度的合适设定,达到减少SOC测试所用时间的目的.针对国际SOC标准电路验证表明,与同类算法相比,该算法能够获得较短的测试时间.     

模块结构的SOC集成电路测试系统

根据不完全的统计,从1980年代开始集成电路的工艺快速更新换代,集成度按摩尔定律每18个月增加一倍,此增长势头将会延续至2010年。相应生产每晶体管成本从0.5美分下降至200年的0.001美分,而测试每个晶体管成本只从0.4     

SOC设计中的硬核复用及其工艺移植

IP复用已成为SOC(system-on-chip)芯片设计的主要手段之一.以一款0.18 μm工艺下的温度控制芯片设计为例,具体介绍硬核复用设计的工艺移植问题,并给出了一种基于工艺设计工具包的设计流程及其关键技术解决方案.该设计流程在保证电路功能正确性的同时,又可以减少版图设计的设计周期,可以为其他类似硬核的复用设计提供参考.     

基于SPI高速分时复用/解复用的方法实现数据传输及其FPGA实现

本文讨论数字信号传输技术,其是一种基于FPGA的通过SPI总线高速复用、解复用的方法实现数据传输的技术.主要以两块Kintex-7系列芯片之间的数据传输为例,其在节省硬件资源上具有传输可靠、延时小的优势.实验数据表明,该方法不仅结构简单、实用性高,并且能有效地减少硬件资源的开销,更容易满足实际设计的需求.     

SOC的低功耗快速测试

SOC由多个芯核组成,它的测试可以分为系统级和芯核级来解决,也可以从电路结构和测试算法两个方面来进行.测试时间长,测试数据量大,测试功耗高是系统芯片测试的难题.解决这些问题的途径主要有:基于软件和硬件协同测试的方法;对测试向量进行处理的方法;在测试电路中使用翻转较少的触发器的DFT结构;合理的划分片上的可测试资源.还给出了尚需进行的研究工作.     

On Concurrent Test of Core-Based SOC Design

In this paper, a method to solve the resource allocation and test scheduling problems together in order to achieve concurrent test for core-based System-On-Chip (SOC) designs is presented. The primary objective for concurrent SOC test is to reduce test application time under the constraints of SOC pins and peak power consumption. The methodology used in this paper is not limited to any specific Test Access Mechanism (TAM). Additionally, it can also be applied to SOC budgeting at design phase to predict a tradeoff between test application time and SOC pins needed. The contribution of this paper is the formulation of the problem as a well-known 2-dimensional bin-packing problem. A best-fit heuristic algorithm is adopted to achieve optimal solution.     

A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips

This paper deals with the design of SOC test architectures which are efficient with respect to required ATE vector memory depth and test application time. We advocate the usage of a TestRail Architecture, as this architecture, unlike others, allows not only for efficient core-internal testing, but also for efficient testing of the circuitry external to the cores. We present a novel heuristic algorithm that effectively optimizes the TestRail Architecture for a given SOC by efficiently determining the number of TestRails and their widths, the assignment of cores to the TestRails, and the wrapper design per core. Experimental results for four benchmark SOCs show that, compared to previously published algorithms, we obtain comparable or better test times at negligible compute time.     

测试重用是SOC设计的重要成份

本文主要论述了设计重使用的重要性、标准,以及测试存取结构.     

An Integrated Framework for the Design and Optimization of SOC Test Solutions

We propose an integrated framework for the design of SOC test solutions, which includes a set of algorithms for early design space exploration as well as extensive optimization for the final solution. The framework deals with test scheduling, test access mechanism design, test sets selection, and test resource placement. Our approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests and power consumption. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. We have made an implementation of the proposed heuristic used for the early design space exploration and an implementation based on Simulated Annealing for the extensive optimization. Experiments on several benchmarks and industrial designs show the usefulness and efficiency of our approach.     

一种适合于SOC系统的JTAG扩展化可测性设计

随着集成电路系统复杂性的提高及基于 IP核的 SOC系统的出现 ,电路测试的难度不断增大 ,对电路可测性设计提出了更高的要求。文中在研究了现有各种可测性设计方法优劣后提出了扩展化的 JTAG可测性设计电路 ,它在稍增加电路复杂度的情况下融合各测试方法 ,并提出了利用这种测试电路的 IC系统测试方案。它克服了测试基于 IP核的 SOC系统的一些难点。     

基于核的信息安全处理芯片可测性设计

从可测性设计角度讨论了信息安全处理芯片的芯片级测试控制器的设计以及相应核的可测性设计.综合结果显示,所设计的芯片级测试控制器所占用的面积代价非常小.     

基于测试项抽取的测试用例复用方法

针对测试用例复用过程中测试用例与被测模块相关性较高的现状,提出了一种测试用例复用的方法.通过抽取测试用例步骤序列的测试项,生成一个测试项集合,然后在新测试工作时检索该集合以实现测试用例的复用.另外,为了便于测试用例的管理,文中采用XML描述测试用例.实例表明,该方法能够有效降低测试用例与被测模块相关性,提高测试效率.     

A Graph-Based Approach to Power-Constrained SOC Test Scheduling

The test scheduling problem is one of the major issues in the test integration of system-on-chip (SOC), and a test schedule is usually influenced by the test access mechanism (TAM). In this paper we propose a graph-based approach to power-constrained test scheduling, with TAM assignment and test conflicts also considered. By mapping a test schedule to a subgraph of the test compatibility graph, an interval graph recognition method can be used to determine the order of the core tests. We then present a heuristic algorithm that can effectively assign TAM wires to the cores, given the test order. With the help of the tabu search method and the test compatibility graph, the proposed algorithm allows rapid exploration of the solution space. Experimental results for the ITC02 benchmarks show that short test length is achieved within reasonable computation time.