AES加密设备的差分能量攻击原理与仿真

旁路攻击是目前信息安全技术领域一个备受瞩目的热点,绕过传统的密码分析方法,利用加密解密设备在进行数据处理时泄露出来的信息比,如运行时间、功耗等对密码系统进行分析和攻击.而DPA（differential power analysis）攻击是较为常见的一种旁路攻击.文中对DPA攻击和AES加密算法进行简单介绍,并在此基础上进行标准DPA攻击的仿真,为能量攻击分析提供一定的理论依据和实验数据.     

新的抵抗鬼峰的关联矩阵差分能量分析

差分能量分析（DPA）是对芯片中分组密码实现安全性的最主要威胁之一，当采集的能量迹不足时，DPA容易受到错误密钥产生的差分均值影响产生鬼峰。基于DPA，提出了一种可以有效抵抗鬼峰的关联矩阵差分能量分析（IMDPA）。通过构造预测差分均值矩阵，利用猜测密钥在非泄露区间的弱相关性，避免非泄露区间对泄露区间内密钥猜测的影响。对IMDPA在AES-128算法的不同泄露区间进行了实验验证，结果表明，与传统的DPA相比，IMDPA需要更少（达到85%）的能量迹来猜测正确的密钥。同时IMDPA在实施防护措施下的AES-128的密钥猜测效率仍然存在显著的优势。为了进一步验证IMDPA在分组密码中的通用性，在SM4算法上进行了实验验证，与传统的DPA相比，IMDPA需要更少（达到87.5%）的能量迹来猜测正确的密钥。     

分组密码算法芯片的模块保护设计

为了降低简单能量算法、差分能量分析对分组密码攻击的可能性,针对分组密码芯片能量消耗情况,实施了对密码芯片的模块保护设计。通过对密码芯片中算法的线性部分与非线性部分进行抗能量攻击的模块保护设计,提高了密码芯片抗能量攻击性能。     

芯片密码引擎抗能量攻击的几种设计措施

随着能量攻击技术已经日渐成熟,其对密码安全芯片威胁也越来越大,抗能量攻击设计也成为密码芯片设计不可或缺的一部分。论文介绍了密码芯片所面临的能量攻击的理论原理,并基于目前芯片密码引擎设计,提出了几种常用的抗能量攻击设计措施。     

基于FPGA平台的抗DPA攻击电路级防护技术研究

随着现场可编程门阵列（FPGA）芯片在安全领域上的广泛应用,有关FPGA密码芯片的抗（DPA）研究也越来越受关注,但目前的研究成果大多针对智能卡的安全防护。在研究各种电路级安全防护技术的基础上,采用硬件宏的方法将双轨和预充电技术应用于FPGA芯片的数据加密标准算法（DES）硬件结构,通过DPA攻击实验后发现,未加防护措施的DES加密系统难以抵御DPA攻击,而加防护措施的加密系统具有抗DPA攻击的能力。     

基于AES密码芯片的DPA攻击技术分析

关于AES密码芯片相应的DPA攻击技术实现方法,而且基于Atmel—AES平台应用DPA攻击技术可以分析获得AES相应的密钥,从而能够证明AES算法对于DPA攻击时体现出来的薄弱环节,同时也可以证明对AES芯片抵抗DPA攻击进行相关研究的必要性。     

分组密码DPA汉明重量区分函数选择方法

为了解决分组密码差分能量分析攻击(DPA)汉明重量区分函数选择问题,提出了一种基于相对非线性度的选择方法.该方法利用分组密码算法S盒输出相对非线性度与DPA之间的关系,通过比较相对非线性度的大小来选择汉明重量区分函数.通过仿真验证和实测验证,证明采用该方法能够正确地选择攻击效果较好的汉明重量区分函数.     

防御差分功耗分析攻击技术研究

差分功耗分析(DPA)攻击依赖于密码芯片在执行加密/解密过程中功耗与数据及指令的相关性,利用统计学等方法对收集到的功耗曲线进行分析,盗取关键信息,对密码芯片的安全性构成极大威胁。防御DPA攻击技术的开发与研究,已经成为信息安全领域的迫切需求。该文在归纳DPA攻击原理的基础上,对主流防御DPA攻击技术的理论与设计方法进行概述与分析,指出防御DPA前沿技术的研究进展。重点讨论防御DPA攻击技术的原理、算法流程和电路实现,包括随机掩码技术、功耗隐藏技术、功耗扰乱技术等等,并详细分析这些技术存在的优缺点。最后,对该领域潜在的研究方向与研究热点进行探讨。     

FPGA密码芯片改进掩码防护方法研究

功耗攻击已对密码芯片物理安全性构成严峻威胁,对其攻击和防御的研究是密码旁路分析的热点问题。文中给出了一种DES伪随机掩码算法的设计和实现方法,分析了算法抗功耗攻击的安全性。结果表明:一般的DES伪随机掩码算法只能抵抗一阶差分功耗攻击,不能有效防御二阶差分功耗攻击。为抵御二阶DPA攻击,采用掩码方法对DES掩码算法结构进行了改进,在理论上具有抗DPA攻击的能力。     

半导体与微电子技术 印制电路与集成电路

062595045nm节点在悄悄行动〔刊,中〕/翁寿松//中国集成电路.—2006,15(5).—51-54(C2)0625951分组密码算法芯片的模块保护设计〔刊,中〕/罗岚//信息安全与通信保密.—2006,(7).—21-22(L)为了降低简单能量算法、差分能量分析对分组密码攻击的可能性,针对分组密码芯片能量消耗情况,实施了对密码芯片的模块保护设计。通过对密码芯片中算法的线性部分与非线性部分进行抗能量攻击的模块保护设计,提高了密码芯片抗能量攻击性能。参30625952IP核的可重用验证方案研究〔刊,中〕/温国忠//深圳职业技术学院学报.—2006,5(2).—10-12(C)在IP产品开…     

The research of DPA attacks against AES implementations

This article examines vulnerabilities to power analysis attacks between software and hardware implementations of cryptographic algorithms. Representative platforms including an Atmel 89S8252 8-bit processor and a 0.25 um 1.8 v standard cell circuit are proposed to implement the advance encryption standard （AES）. A simulation-based experimental environment is built to acquire power data, and single-bit differential power analysis （DPA）, and multi-bit DPA and correlation power analysis （CPA） attacks are conducted on two implementations respectively. The experimental results show that the hardware implementation has less data-dependent power leakages to resist power attacks. Furthermore, an improved DPA approach is proposed. It adopts hamming distance of intermediate results as power model and arranges plaintext inputs to differentiate power traces to the maximal probability. Compared with the original power attacks, our improved DPA performs a successful attack on AES hardware implementations with acceptable power measurements and fewer computations.     

Improving power analysis attack resistance using intrinsic noise in 3D ICs

Three-dimensional (3D) integration is envisioned as a natural defense to thwart side-channel analysis (SCA) attacks on the hardware implementation of cryptographic algorithms. However, neither physical experiments nor quantitative analysis is available in existing works to study the impact of power distribution network (PDN) on the SCA attacks. Through quantitative analyses and experiments with realistic 3D models, this work demonstrates the impact of noise in PDN on the 3D chip's resilience against correlation power analysis (CPA) attack, which is one of SCA attacks. The characteristic of PDN noise is extracted from our experiments. To expand the natural defense originated from the 3D integration, this work proposes to exploit the PDN noise inherently existing in 3D chips to thwart CPA attacks. Instead of introducing external noise or flattening the power profile, the proposed method utilizes the spatially and temporally varied supply voltages from other 3D planes to blur the power correlation of the crypto unit. Both theoretical analysis and experimental validation prove that the proposed method can effectively enhance the resilience of a crypto unit embedded in the 3D chip against CPA attacks. Simulation results show the proposed method improves the average guessing entropy by 9× over the baseline. Emulation on an FPGA platform demonstrates that the proposed method successfully slows down the key retrieval speed of CPA attack, with significantly less power overhead than representable power equalization techniques. Test vector leakage assessment (TVLA) shows that the proposed method improves the confidence to accept null hypothesis 201× over the baseline.     

Practical Second‐Order Correlation Power Analysis on the Message Blinding Method and Its Novel Countermeasure for RSA

Recently power attacks on RSA cryptosystems have been widely investigated, and various countermeasures have been proposed. One of the most efficient and secure countermeasures is the message blinding method, which includes the RSA derivative of the binary‐with‐random‐initial‐point algorithm on elliptical curve cryptosystems. It is known to be secure against first‐order differential power analysis (DPA); however, it is susceptible to second‐order DPA. Although second‐order DPA gives some solutions for defeating message blinding methods, this kind of attack still has the practical difficulty of how to find the points of interest, that is, the exact moments when intermediate values are being manipulated. In this paper, we propose a practical second‐order correlation power analysis (SOCPA). Our attack can easily find points of interest in a power trace and find the private key with a small number of power traces. We also propose an efficient countermeasure which is secure against the proposed SOCPA as well as existing power attacks.     

Design of differential power analysis resistant crypto chip based on time randomization

Differential Power Analysis (DPA) is an effective attack method to break the crypto chips and it has been considered to be a threat to security of information system. With analyzing the principle of resist-ing DPA, an available countermeasure based on randomization is proposed in this paper. Time delay is in-serted in the operation process and random number is precharged to the circuit during the delay time, the normal schedule is disturbed and the power is randomized. Following this methodology, a general DPA re-sistance random precharge architecture is proposed and DES algorithm following this architecture is imple-mented. This countermeasure is testified to be efficient to resist DPA.     

对智能卡进行微分功耗分析攻击的方法研究

详细阐述了对通用密码系统实施微分功耗分析攻击(DPA)的理论基础和对DES算法攻击的特定理论，并提出了对DPA的改进算法。在分析功耗信号的噪声特点以后，提出了一个信噪比(SNR)的建模方法和相应理论的证明。最后，给出了算法的一个实验结果。     

基于微控制器的AES激光注入攻击研究

密码设备面临故障攻击的威胁,针对密码芯片的故障攻击手段研究是密码学和硬件安全领域的重要研究方向。脉冲激光具有较好的时空分辨性,是一种准确度较高的故障攻击手段。该文详细描述了激光注入攻击的原理和方法,以集成AES-128算法的微控制器(MCU)为例实施了激光注入攻击实验。实验以微控制器的SRAM为攻击目标,分别成功实现了差分故障攻击和子密钥编排攻击,恢复了其16 Byte的完整密钥,其中后一种攻击是目前首次以激光的手段实现。研究表明,激光注入攻击能准确定位关键数据存放的物理位置,并能在任意的操作中引入错误,实现单比特的数据翻转,满足故障攻击模型的需求。激光注入攻击能在较短时间内完成自动攻击和密文收集,攻击过程贴近真实场景,对密码芯片具有极大的威胁。     

基于微控制器的AES激光注入攻击研究

密码设备面临故障攻击的威胁,针对密码芯片的故障攻击手段研究是密码学和硬件安全领域的重要研究方向.脉冲激光具有较好的时空分辨性,是一种准确度较高的故障攻击手段.该文详细描述了激光注入攻击的原理和方法,以集成AES-128算法的微控制器(MCU)为例实施了激光注入攻击实验.实验以微控制器的SRAM为攻击目标,分别成功实现了差分故障攻击和子密钥编排攻击,恢复了其16 Byte的完整密钥,其中后一种攻击是目前首次以激光的手段实现.研究表明,激光注入攻击能准确定位关键数据存放的物理位置,并能在任意的操作中引入错误,实现单比特的数据翻转,满足故障攻击模型的需求.激光注入攻击能在较短时间内完成自动攻击和密文收集,攻击过程贴近真实场景,对密码芯片具有极大的威胁.     

Pseudo 4D projective coordinate-based multi-base scalar multiplication

In order to address the problem of elliptic curve cryptosystem (ECC) for the expensive cost in scalar multiplication and the vulnerability to the power analysis attacks,a pseudo 4D projective coordinate-based multi-base scalar multiplication was proposed to optimize group operation layer and scalar multiplication operation layer,which aimed at increasing the performance of ECC and resisting common power analysis attacks.Experimental results show that compared with the state-of-the-art algorithms,the proposed algorithm decreases 5.71% of point doubling cost,3.17% of point tripling cost,and 8.74% of point quintupling cost under discrete group operations.When the key length is 160 bit,the proposed algorithm decreases 36.32% of point tripling cost,17.42% of point quintupling cost,and 8.70% of the system cost under continuous group operations.The analyzing of power consumption wave shows that the proposed algorithm can resist SPA and DPA attack.     

New Type of Collision Attack on First‐Order Masked AESs

This paper introduces a new type of collision attack on first‐order masked Advanced Encryption Standards. This attack is a known‐plaintext attack, while the existing collision attacks are chosen‐plaintext attacks. In addition, our method requires significantly fewer power measurements than any second‐order differential power analysis or existing collision attacks.