Source—Drain contact resistance in CMOS with self-aligned TiSi2

The contact resistance between TiSi2and n⁺-p⁺source-drain in CMOS is studied for a variety of junction profiles and silicide thicknesses. It is shown that the measured contact resistance is consistent with the transmission-line model for electrically long contacts. The contact contribution to the total device series resistance can be significant if excessive silicon is consumed during silicide formation. Contact resistivities of 3 × 10^-7and 1 × 10^-6Ω . cm²can be obtained for 0.15-0.20-µm-deep arsenic and boron junctions, respectively, if the interface doping concentration is kept at 1 × 10²⁰/cm³. Furthermore, low-temperature measurements show that the contact resistivity is nearly constant from 300 to 77 K, as would be expected from a tunneling-dominated current transport at the TiSi2-n⁺and TiSi2-P⁺interfaces.     

A self-aligned 1-µm-channel CMOS technology with retrograde n-well and thin epitaxy

A six-mask 1-µm CMOS process with many self-aligned features is described. It uses a thin p-type epitaxial layer on a p⁺substrate and a retrograde n-well. Self-aligned TiSi2is formed on n⁺and p⁺diffusions to reduce the sheet resistance and to make butted source contacts. It is shown that n⁺poly-gated p-channel devices can be properly designed with low threshold magnitudes and good turn-off characteristics. With a 5-V supply, the minimum gate delay of unloaded CMOS ring oscillators is 150 ps/stage. Furthermore, it is demonstrated that this CMOS technology is latchup free since the holding voltage for latchup is higher than 5 V.     

1.0-µm n-well CMOS/bipolar technology

High-performance 1.0-µm n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously resulting in collector-isolated vertical n-p-n bipolar transistor fabrication without any additional process step to CMOS process. On the other hand, 1.0-µm CMOS with a new "hot carrier resistant" self-defined polysilicon sidewall spacer (SEPOS) LDD NMOS was developed. It can operate safely under supply voltage over 5 V without performance degradation of CMOS circuits. By evaluating ring oscillators and differential amplifiers constructed by both CMOS and bipolar transistors, it can be concluded that in a digital and in an analog combined system, CMOS has sufficiently high-speed performance for digital parts, while bipolar is superior for analog parts. In addition, bipolar transistors with an n⁺-buried layer were also fabricated to reduce collector resistance. Concerning the bipolar input/output buffers, the patterned n⁺-buried layer improves the drivability and high-frequency response. As a result, the applications of n-well CMOS/bipolar technology become clear. This technology was successfully applied to a high-speed 64-kbit CMOS static RAM, and improvement in access time was observed.     

Self-focusing of 10.6-µm radiation in liquid CS2

Self-focusing of 9-kW CO2laser pulses was observed in liquid CS2. The calculated coefficient of nonlinear index of refraction (n2) from experimental data is approximately 10^-17MKS, which is nearly three orders of magnitude larger than the nonlinear index coefficient observed for visible radiation.     

A 1-µm bipolar VLSI technology

A 1-µm VLSI process technology has been developed for the fabrication of bipolar circuits. The process employs electron-beam slicing writing, plasma processing, ion implantation, and low-temperature oxidation/annealing to fabricate bipolar device structures with a minimum feature size of 0.9 µm. Both nonisolated I²L and isolated Schottky transistor logic (STL) devices and circuits have been fabricated with this process technology. The primary demonstration vehicle is a scaled LSI, I²L, 4-bit processor chip (SBP0400) with a minimum feature size of 1 µm. Scaled SPB0400's have been fabricated that operate at clock speeds 3 × higher than their full-size counterparts at 50-mA chip current. Average propagation delay has been measured as a function of minimum feature size for both I²L and STL device designs. Power-delay products of 14 fJ for I²L and 30 fJ for STL have been measured.     

A 2-µm silicon-gate C-MOS/SOS technology

A 2-µm silicon gate deep-depletion C-MOS/SOS technology is described and characterized. The fabrication technology features all dry processing (ion milling and plasma etching) ion implanted source and drain, 2-µm features on all levels, phosphorous glass reflow for improved yield, and low-temperature processing (T ≤ 875°C). Characterization of the static electrical parameters as a function of channel length is presented. Circuit performance was characterized using a ring oscillator and a pattern generator. The ring oscillator exhibited stage delay as small as 220 ps at 5 V and an associated speed power product of less than 5 pJ. The pattern generator achieved an 80-MHz data rate. The potential of this technology for extension to submicrometer geometries was demonstrated by fabrication of discrete transistors with O.5-µm channel lengths.     

Characteristics of a 1.2-µm CMOS technology fabricated on an RF-heated zone-melting recrystallized SOI

0.7-5-µm CMOSFET's were fabricated on SOI which was recrystallized using an RF-heated zone-melting recrystallization (RFZMR) method. The leakage currents of n-channel MOSFET's having gate lengths between 5- and 0.7-µm range between 10^-14and 10^-12A/µm and show no dependence on channel length. Those of the p-channel MOSFET's were 10^-14-10^-12A/µm when the gate lengths were longer than 1.2 µm, and increased when the gate lengths were shorter than 1.0 µm. The propagation delay time of the CMOSFET inverter was 0.13 ns per stage at a supply voltage of 3.5 V.     

A new oxidation-resistant self-aligned TiSi2process

This paper presents a thin amorphous Si (a-Si) on Ti as an oxidation-resistant material for a self-aligned TiSi2process. It is shown that a thin a-Si over Ti film will greatly suppress the interaction between Ti and ambient gases (N2and O2) during the thermal TiSi2formation cycle in conventional N2furnance while maintaining satisfactory self-aligned property after silicidation at a temperature below 630°C.     

1/4-µm CMOS isolation technique using selective epitaxy

A new CMOS isolation technique has been developed for reducing isolation width to a 1/4 µm with large latchup immunity. This technique is supported by three key processes. The first is to form 1/4 µm thick insulator films on trench sidewalls, which are shaped perpendicularly to the substrate surface plane. The second is to refill the trenches with selectively grown single-crystal silicon with a planar surface. The third is to form a low-resistance well for latchup prevention. The CMOS devices are composed of n-channel devices fabricated on a p-type substrate and p-channel devices fabricated on an n-type epi-layer. In this isolation structure, a parasitic MIS operation with vertical channel induces large leakage currents along the isolation sidewalls. However, the highly doped p-type region, due to deep boron implant in the p-type substrate, is effective to suppress parasitic operation. Submicrometer-gate CMOS inverter operation is shown, when the channel stop implant is carried out.     

Design methodology of a 1.2-µm double-level-metal CMOS technology

An advanced high-performance CMOS process and associated gate array and semicustom design approaches are described. Designed for rapid custom application, the process utilizes an n-well 1.2-µm gate length and two layers of metal. The gate array has a density of 10000 2-input gates with typical delays of 1.25 ns while the semicustom approach offers densities of 30000 gates with typical loaded delays of 1.0 ns.     

Dry etching technology for 1-µm VLSI fabrication

A dry etching technology for 1-µm VLSI has been developed. This technology led to successful fabrication of a 1-µm 256-kbit MOS RAM using electon-beam direct writing and molybdenum-polysilicon double-gate structure. Silicon nitride, silicon dioxide, phosphosilicate glass, polysilicon, single-crystal silicon, molybdenum, and aluminum are etched by parallel-plate RF diode reactors. Resist patterns are used as etching masks. The negative resist is CMS and the positive resist is FPM. Plasma polymerization is found to have significant effect on etching selectivity, undercutting, and residue. Directional etching profiles are realized and 1-µm patterns with less than 0.05-µm undercutting are obtained. High etching selectivities are achieved. Methods for preventing and removing contamination as well as damage are established. With these, dry etching proves to bring no adverse effects on device characteristics. Pattern-width fluctuations caused by negative-resist pattern foot are decreased to below 0.1 µm by a new foot trimming technique. Resist step coverage is also clarified.     

Characteristics of room-temperature 2.3-µm laser emission from tm3+in YAG and YAlO3

The relaxation of low-lying excited states of Tm³⁺ions doped in YAG, YAlO3, and Y2O3due to photon and phonon emission is studied theoretically. Stimulated emission cross sections (integrated over frequency), fluorescence lifetimes, and radiative quantum efficiencies are calculated and their implications for laser operation on the 2.3-μm³F4→³H5line of Tm³⁺are discussed. The calculations, based on a few phenomenological parameters which have been determined by others, are easily generalizable to other host materials and other rare-earth (RE) ions. Room-temperature pulsed laser emission from Tm³⁺ions near 2.3 μm was observed on one line in Tm:Cr:YAG, and on four lines in Tm:Cr:YAlO3. Lower oscillation thresholds were generally obtained in the YAlO3 rods, consistent with the theory presented. A threshold of 31 J was obtained with a Tm:Cr:YAlO3rod at 2.274 μm. In the free-running pulsed mode, peak power levels up to several hundred watts and total output energies up to 12 mJ/pulse were observed. Other general, observed operating characteristics are discussed.     

Two-dimensional simulation of a 2-µm CMOS process using ROMANS II

To accurately simulate processes applicable to fine-line geometry devices and VLSI circuits with feature size approaching 1 µm, a new two-dimensional process simulator program called ROMANS II (Redistribution and Oxidation Modeling ANalysis by Simulation in II dimensions) has been developed. This paper reports on the application of this program to simulate the thermal redistribution of the boron field and threshold voltage adjust implants for an n-channel device in the gate region of a 2-µm CMOS n-well process. The device fabrication schedule is discussed in detail and the process steps pertinent to the redistribution of the boron implants are simulated on ROMANS II. The surface topography and corresponding equidensity contours for each simulated process step are presented. The validity of the simulated results was checked by one-dimensional spreading-resistance measurements in the isolated field and channel regions, respectively, and the overall correlation was satisfactory. Since no two-dimensional experimental technique is available to measure impurity profiles in the transition region of the birds's beak, predictions based on ROMANS II are important.     

A systems approach to 1-µm NMOS

In 1977, groups from diverse disciplines at Bell Labs were brought together for the first time, with the goal of applying a systems approach to high-performance NMOS technology. These groups, namely, solid-state physics, device design, materials, processing, and lithography found a symbiotic relationship that has produced not only NMOS devices with unparalleled performance, but also improved materials, processes, and tools-many of which are in production today.     

Process and device performance of submicrometer-channel CMOS devices using deep-trench isolation and self-aligned TiSi2technologies

According to our scaling study, a deeper n-well allows for a lower n-well surface concentration with improved short-channel effects in submicrometer-channel PMOS-FET's. The deep n-well, however, requires a large space between n- and p-channel devices. This large space limits the integration density in scaled bulk CMOS VLSI's. The deep-trench isolation combined with an epitaxial layer resolves this drawback with significantly improved device-to-device isolation and latchup susceptibility. The 6-µm-deep with 2-µm-wide deep trench is etched in the epitaxial layer and is refilled with 1500 Å of thermal silicon-dioxide film and 2 µm of polysilicon film. The sheet resistances of N⁺and P⁺diffusion and N⁺-doped polysilicon layers were reduced to 3 to 4 Ω/□ by using the self-aligned TiSi2layer with an oxide sidewall spacer. As a result of this low sheet resistance, the saturation drain current of submicrometer n- and p-channel MOSFET's was improved approximately 33 to 37 percent compared with conventional MOSFET's without the self-aligned TiSi2layer. The 0.5-µm-channel CMOS devices using the deep-trench isolation with an epitaxial layer and the self-aligned TiSi2layer operated at a propagation delay time of 140 ps with a power dissipation of 1.1 mW per inverter and attained a maximum clock frequency of 400 MHz in a static / 4 counter without suffering from latchup even at the latchup trigger current of 200 mA.     

A short-channel CMOS/SOS technology in recrystallized 0.3-µm-thick silicon-on-sapphire films

CMOS/SOS devices and circuits were fabricated in 0.3-µm-thick epitaxial silicon-on-sapphire (SOS) films. Two solid-phase epitaxial recrystallization techniques double solid-phase epitaxy (DSPE) and solid-phase epitaxy and regrowth (SPEAR) reduced the total microtwin concentrations in the Si layers more than tenfold, while increasing electron and hole inversion-layer mobilities between 30 and 45 percent. Leakage currents were substantially reduced in all SPEAR devices and in n-channel DSPE transistors, with some increase observed for p-channel DSPE devices. Drive currents and subthreshold slopes also showed significant improvement in both n- and p-devices. Propagation delays below 75 ps were obtained for CMOS/SOS inverters with Loff= 0.5 µm. The application of DSPE and SPEAR techniques to 0.3-µm SOS films will extend the scaling of CMOS/SOS to circuits with VLSI complexity.     

Variable-shaped electron-beam direct writing technology for 1-µm VLSI fabrication

A 1-µm 256K MOS RAM has been fabricated using a variable-shaped electron-beam (EB) direct writing technology. EB drawing data are prepared using a new program, PEBL, which includes a new algorithm for shot division. PEBL plays an important role in obtaining high EB system throughput and high quality patterns. A new proximity correction technique, DCA, has also been proposed. This technique is simple and very effective in fabricating 1-µm VLSI patterns. Negative resist CMS or positive resist FPM are used appropriately, according to process levels. In fabrication of a 1-µm 256K MOS RAM, ±0.2-µm overlay accuracy and ±0.1-µm linewidth accuracy were achieved.     

Titanium disilicide contact resistivity and its impact on 1-µm CMOS circuit performance

A major feature of modern 1-µm CMOS technology is the use of TiSi2-clad diffusions with effective sheet resistances of typically 1 Ω /square. However, until now very little attention has been given to the contact resistance between the TiSi2and the underlying diffusions which form the source and drain of the active transistors. Our experimental results have shown that, depending on process conditions, the specific contact resistivity from silicide to n-diffusion varies by six orders of magnitude. In this work it is demonstrated that unless proper care is taken with respect to junction doping concentrations and post-silicide processing to minimize the silicide to diffusion contact resistance, the use of silicided diffusions actually can be detrimental to circuit performance instead of the intended performance enhancement. In this paper we will present: 1) a novel method to evaluate silicide to diffusion contact resistance using only two masks, 2) an outline of the process conditions that yield a minimum contact resistance, 3)circuit simulations showing the impact of this work on circuit performance, and 4) results showing that the modulation of the contact resistance at high current levels can distort the MOS linear region current-voltage characteristics.     

CO2laser preamplifier capabilities for low-level 10.6-µm direct-detection receivers

We examine the potential of CO2laser preamplifiers for sensitivity enhancement in low-level, direct-detection 10.6-μm receivers. For the condition in which a gain-dependent competition exists between the background noise and amplifier spontaneous emission noise (assuming negligible thermal noise), the analysis predicts an optimum useful SNR enhancement of only 6 dB for a blackbody background field of 300 K and 4.1 dB for a background of 260 K, when the amplifier gain bandwidth perp-line is 100 MHz and the infrared (IR) filter bandwidth is 0.10 μm. Based on preselected choice of gain and bandwidth, a two-stage, water-cooled, flowing-gas amplifier of optimized design was constructed. A maximum gain of 3.12 dB was attained forP(20)with a He : CO2: N2mixture of 5.0 : 1.0 : 0.6 at a coolant temperature of 285 K and a slow gas refresh rate of 0.2 volumes/s. Using a fast-flow system with 12-volume/s refresh rate, we measured an amplifier gain of 3.9 dB, close to the design estimate of 4.1 dB. With a calibrated HgCdTe detector,f/4cold shield, and narrow-band (0.25 μm) cold filter, a spontaneous emission flux density ofsim 1.0 times 10^{14}photons/ cm². s was measured at the 3.12-dB gain level, in close agreement with the theoretical estimate. Excess noise resulting from amplifier discharge was undetectable above the basic detector noise.     

Collisionless self-focusing of CO210 µm P(20) laser light in SF6

We develop a simple intuitive picture of the vibration-rotation structure of the SF6molecule such that the molecular susceptibility responsible for self-focusing can be calculated. We treat the propagation dynamics by generalizing the standard steady-state Gaussian propagation equations to include the important effect of absorption in the wings of the spatial profile. By calibrating the model to absorption data at CO210 μmP(2)we find good agreement with beam waist data at the same wavelength. Absorption in the wings is dominant at low laser fluences, and the real part of the susceptibility is responsible for the defocusing-to-focusing turnover in the beam waist near 100 mJ/cm², consistent with the interpretation of Nowak and Ham [6].