A 10 b, 20 Msample/s, 35 mW pipeline A/D converter

This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 μm CMOS technology which achieves a power dissipation of 35 mW at full speed operation. Circuit techniques used to achieve this level of power dissipation include digital correction to allow the use of dynamic comparators, and optimum scaling of capacitor values through the pipeline. Also, to be compatible with low voltage mixed-signal system environments, a switched capacitor (SC) circuit in each pipeline stage is implemented and operated at 3.3 V with a new high-speed, low-voltage operational amplifier and charge pump circuits. Measured performance includes 0.6 LSB of INL, 59.1 dB of SNDR (Signal-to-Noise-plus-Distortion-Ratio) for 100 kHz input at 20 Msample/s. At Nyquist sampling (10 MHz input) SNDR is 55.0 dB. Differential input range is ±1 V, and measured input referred RMS noise is 220 μV. The power dissipation at 1 MS/s is below 3 mW with 58 dB of SNDR     

A 1-V 10.7-MHz switched-opamp bandpass /spl Sigma//spl Delta/ modulator using double-sampling finite-gain-compensation technique

A 1 V switched-capacitor (SC) bandpass sigma-delta (/spl Sigma//spl Delta/) modulator is realized using a high-speed switched-opamp (SO) technique with a sampling frequency of up to 50 MHz, which is improved ten times more than prior 1 V SO designs and comparable to the performance of the state-of-the-art SC circuits that operate at much higher supply voltages. On the system level, a fast-settling double-sampling SC biquadratic filter architecture is proposed to achieve high-speed operation. A low-voltage double-sampling finite-gain-compensation technique is employed to realize a high-resolution /spl Sigma//spl Delta/ modulator using only low-DC-gain opamps to maximize the speed and to reduce power dissipation. On the circuit level, a fast-switching methodology is proposed for the design of the switchable opamps to achieve a switching frequency up to 50 MHz. Implemented in a 0.35-/spl mu/m CMOS process (V/sub TP/=0.82 V and V/sub TN/=0.65 V) and at 1 V supply, the modulator achieves a measured peak signal-to-noise-and-distortion ratio (SNDR) of 42.3 dB at 10.7 MHz with a signal bandwidth of 200 kHz, while dissipating 12 mW and occupying a chip area of 1.3 mm/sup 2/.     

A 80-MHz bandpass ΔΣ modulator for a 100-MHz IFreceiver

A fully differential fourth-order bandpass ΔΣ modulator is presented. The circuit is targeted for a 100-MHz GSM/WCDMA-multimode IF-receiver and operates at a sampling frequency of 80 MHz. It combines frequency downconversion with analog-to-digital conversion by directly sampling an input signal from an intermediate frequency of 100 MHz to a digital intermediate frequency of 20 MHz. The modulator is based on a double-delay single-op amp switched-capacitor (SC) resonator structure which is well suited for low supply voltages. Furthermore, the center frequency of the topology is insensitive to different component nonidealities. The measured peak signal-to-noise ratio is 80 and 42 dB for 270 kHz (GSM) and 3.84-MHz (WCDMA) bandwidths, respectively. The circuit is implemented with a 0.35-μm CMOS technology and consumes 56 mW from a 3.0-V supply     

Low-voltage high-speed switched-capacitor circuits without voltage bootstrapper

Low-voltage high-speed switched-capacitor (SC) circuit design without using voltage bootstrapper is presented. The basic building block used for low-voltage SC circuit design is the auto-zeroed integrator (AZI), which can work at both low voltage and high sampling frequency. With this method, two low-voltage SC systems were successfully designed and implemented in 1.2-/spl mu/m CMOS technology. The first one is a fully differential SC bandpass biquad working at 1.5 V and 5.0-MHz clock frequency. The measured Q value is 8.0 at the center frequency of 833 kHz. The second one is a fully differential fourth-order bandpass /spl Delta//spl Sigma/ modulator that also works at 1.5 V and 5.0 MHz. Its measured third-order intermodulation is less than -78 dBc due to the low distortion characteristic of AZI. The measured signal-to-noise ratio of the modulator is 61 dB within the narrow band of 25 kHz centered at 1.25 MHz.     

A triple-mode continuous-time /spl Sigma//spl Delta/ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver

Time jitter in continuous-time /spl Sigma//spl Delta/ modulators is a known limitation on the maximum achievable signal-to-noise-ratio (SNR). Analysis of time jitter in this type of converter shows that a switched-capacitor (SC) feedback digital-to-analog converter (DAC) reduces the sensitivity to time jitter significantly. In this paper, an I and Q continuous-time fifth-order /spl Sigma//spl Delta/ modulator with 1-bit quantizer and SC feedback DAC is presented, which demonstrates the improvement in maximum achievable SNR when using an SC instead of a switched-current (SI) feedback circuit. The modulator is designed for a GSM/CDMA2000/UMTS receiver and achieves a dynamic range of 92/83/72 dB in 200/1228/3840 kHz, respectively. The intermodulation distance IM2, 3 is better than 87 dB in all modes. Both the I and Q modulator consumes a power of 3.8/4.1/4.5 mW at 1.8 V. Processed in 0.18-/spl mu/m CMOS, the 0.55-mm/sup 2/ integrated circuit includes a phase-locked loop, two oscillators, and a bandgap.     

A stereo multibit ΣΔ DAC with asynchronous master-clockinterface

A two-channel multibit ΣΔ audio digital-to-analog converter (DAC) with on-chip digital phase-locked loop and sample-rate converter is described. The circuit requires no over-sampled synchronous clocks to operate and rejects input sample clock jitter above 16 Hz at 6 dB/octave. A second-order modulator with a multibit quantizer, switched-capacitor (SC) DAC, and single-ended second-order SC filter provides a measured out-of-band noise of -63 dBr with less than 0.1° phase nonlinearity. Measured S/(THD+N) of the DAC channel including a 0-63 dB, 1 dB/step attenuator is greater than 90 dB unweighted. The circuit is implemented in 0.6-μm DPDM CMOS, dissipating 220 mW at 5 V. Die size is 3 mm×4 mm     

Power harvesting with PZT ceramics and circuits design

Power generated from a piezoelectric material usually comes with poor characteristics such as high voltage, low current and high impedance. In order to drive the embedded sensor circuit, piezoelectric power needs to be characterized and regulated. In this paper, we present an analysis on the power generation characteristics and the efficiency of power conversion of the stiff lead zirconate titanate (PZT) ceramics. Moreover, a power circuit design is put forward in the application where PZT elements are used for power generation in a TKR implant. A hybrid direct current (DC)–DC, comprising a switched capacitor (SC) DC–DC converter and a low dropout (LDO) linear voltage regulator, is presented. The variable ratio SC converter has been taped out with 0.35 μm CMOS technology. The test results show that the SC converter can transfer the input voltage that ranges from 5 to 14 V from the PZT ceramics into the voltage ranging from 2 to 2.5 V which will be dealt with by LDO circuit whose efficiency can reach 80%.     

A rail-to-rail ping-pong op-amp

A rail-to-rail ping-pong op-amp achieves offset cancellation and 1/f noise reduction without folding of the input spectrum. The clocking scheme minimizes the clock feedthrough and the residual offset due to charge injection. With a clock frequency of 100 kHz, the residual offset is less than 100 μV, and the input referred noise is about 225 nV/Hz ^1/2. The rail-to-rail distortion at 1 kHz is lower than -71 dB. The total silicon area is 610×420 μm², and the circuit dissipates 1.5 mW from a single 5 V supply     

一种适用于传感器信号检测的斩波运算放大器

提出一种适合传感器微弱信号检测应用的全差分低噪声、低失调斩波运算放大器。采用两级折叠共源共栅运放结构,基于斩波稳定及动态元件匹配技术,通过在运放低阻节点的电流通路上添加斩波开关的设计方式,增加了运放的输入信号带宽和输出电压摆幅。芯片采用TSMC 0.18μm 1P6MCMOS工艺实现。测试结果表明,在1.8V电源电压,25kHz输入信号和300kHz斩波频率下,斩波运放输入等效失调电压小于120μV,在10Hz～1kHz之间,输入等效噪声为5nV/Hz^1/2,最高开环增益为84dB,单位增益带宽为4MHz。     

一种10位50MHz流水线模数转换器的设计

采用每级1.5 bit和每级2.5 bit相结合的方法设计了一种10位50 MHz流水线模数转换器。通过采用自举开关和增益自举技术的折叠式共源共栅运算放大器,保证了采样保持电路和级电路的性能。该电路采用华润上华(CSMC)0.5μm 5 V CMOS工艺进行版图设计和流片验证,芯片面积为5.5 mm2。测试结果表明:该模数转换器在采样频率为50 MHz,输入信号频率为30 kHz时,信号加谐波失真比(SNDR)为56.5 dB,无杂散动态范围(SFDR)为73.9 dB。输入频率为20 MHz时,信号加谐波失真比为52.1 dB,无杂散动态范围为65.7 dB。     

A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR

An ultra-low-voltage CMOS two-stage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted low-voltage circuit technique achieves high-accuracy high-speed clocking without the use of clock boosting or bootstrapping. A resistor-based input sampling branch demonstrates high linearity and inherent low-voltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a two-channel ADC architecture. The prototype ADC, fabricated in a 0.18 /spl mu/m CMOS process, achieves 77-dB SFDR at 0.9 V and 5MSPS (30 MHz clocking) after calibration. The measured SNR, SNDR, DNL, and INL at 80 kHz input are 50 dB, 50 dB, 0.6 LSB, and 1.4 LSB, respectively. The total power consumption is 12 mW, and the active die area is 1.4 mm/sup 2/.     

High Linearity BiCMOS Multiplier/Transconductor Structures

A new wide-input range BiCMOS analog multiplier is proposed basedon the triode and saturation region operation of the MOS transistors. Thenew circuit can also be reconfigured to operate as a versatile OperationalTransconductance Amplifier, OTA, with independent current bias control for Nstages. The novel design involves the use of attenuators at the input stageto boost the input linear range. It also utilizes a high output impedancesubtractor setup at the output stage to obtain a single-ended output. Thenew circuit is characterized by its large input range, its high linearityand ability to operate at low voltages as well as high frequencies. HSPICEsimulation results of the circuit, using the MOSIS 2 µm processparameters, resulted in an input range of ±4 V (±5 V supply),±1.9 V (±3 V supply) and ±1 V (±2 V supply),with linearity error less than 0.5%. Its usages in certainanalog signal processing applications are also discussed.     

A synchronous phase-lock loop detector for integrated AM radio

A synchronous phase-lock loop AM detector has been realized on a single chip in a bipolar process with an f/SUB T/ of 400 MHz. The circuit accepts input signals at an IF frequency of 450-500 kHz with effective values between 20 and 100 mV. The phase-lock loop capture range is about 150 kHz. AM signals with over 80% modulation depth can be demodulated with less than 1% harmonic distortion in the audio output signal. The power dissipation of the chip is 120 mW at 8 V. The total chip size is 1900/spl times/1300 /spl mu/m/SUP 2/. Since the VCO and the 90/spl deg/ phase shift are completely realized on-chip, large signals at the IF frequency do not occur at the pins of the IC, and parasitic feedback of such signals to the IF amplifier input is minimized.     

A highly linear CMOS Gm-C bandpass filter with on-chipfrequency tuning

A fourteenth-order CMOS transconductance-C (G_m-C) bandpass filter with on-chip automatic frequency tuning is described. By using highly linear G_m-C integrators, the filter achieves 75 dB dynamic range over 700 kHz noise bandwidth. The measured intermodulation distortion (IM3) @ 600 kHz for a 4 V_pp input signal is only -61 dB. On-chip automatic frequency tuning provides more than 300% center frequency range (i.e., 165-505 kHz) of the filter with ±1% frequency accuracy. The 0.7-μm CMOS filter measures 4.8 mm ² and consumes 70 mW from a single 5 V power supply     

A modified asymmetrical pulse-width-Modulated resonant DC/DC converter topology

A modified asymmetrical pulse-width-modulated resonant dc/dc converter employing an auxiliary circuit will be proposed in this paper. The auxiliary circuit consists of a network of two capacitors and an inductor. The aim of this network is to produce zero-voltage-switching (ZVS) over a wide input voltage range, while reducing the voltage stress on the resonant component. A detailed analysis and performance characteristics are presented. Experimental results for a 5 V, 35 W converter show an efficiency of 83% at a constant operating frequency of 500 kHz. Using metal oxide semiconductor field effect transistors (MOSFETs) as synchronous rectifiers can further reduce power losses and improve the efficiency to be greater than 90%.     

一种基于斩波调制的低压高精度CMOS带隙基准源

实现了一种适用于SOC的低压高精度带隙基准电压源设计。利用斩波调制技术有效地减小了带隙基准源中运放的失调电压所引起的误差,从而提高了基准源的精度。考虑负载电流镜和差分输入对各2%的失配时,该基准源的输出电压波动峰峰值为0.31 mV。与传统带隙基准源相比,相对精度提高了86倍。在室温下,斩波频率为100 kH z时,基准源提供0.768 V的输出电压。当电源电压在0.8 V到1.6 V变化时,该基准源输出电压波动小于0.05 mV;当温度在0°C到80°C变化时,其温度系数小于12 ppm/°C。该基准源的最大功耗小于7.2μW,采用0.25μm 2P 5M CM O S工艺实现的版图面积为0.3 mm×0.4 mm。     

A 1.8-V ΔΣ modulator interface for an electretmicrophone with on-chip reference

The design of a delta-sigma (ΔΣ) analog-to-digital converter (ADC) for direct voltage readout of an electret microphone is presented. The ADC is integrated on the same chip with a bandgap voltage reference and is designed to be packaged together with an electret microphone. Having a power consumption of 1.7 mW from a supply voltage of 1.8 V, the circuit is well suited for use in mobile applications. The single-loop, single-bit, fourth-order ΔΣ ADC operates at 64 times oversampling for a signal bandwidth of 11 kHz. The measured dynamic range is 80 dB and the peak signal-to-(noise+distortion) ratio is 62 dB. The harmonic distortion is minimized by using an integrator with an instrumentation amplifier-like input which directly integrates the 125-mV peak single-ended voltage generated by the microphone. A combined continuous-time/switched-capacitor design is used to minimize power consumption     

A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in0.7-μm CMOS

A dual-modulus divide-by-128/129 prescaler has been developed in a 0.7-μm CMOS technology. A new circuit technique enables the limitation of the high-speed section of the prescaler to only one divide-by-two flipflop. In that way, a dual-modulus prescaler with the same speed as an asynchronous divider can be obtained. The measured maximum input frequency of the prescaler is up to 2.65 GHz at 5 V power supply voltage. Running at a power supply of 3 V, the circuit consumes 8 mA at a minimum input frequency of 1.75 GHz     

Micropower switched capacitor biquadratic cell

The implementation of the double correlated sampling noise reduction technique in conventional strays-insensitive switched capacitor biquad building blocks is described. The function is performed by an offset cancellation circuit which is incorporated into the structure without the use of any additional capacitor, only minor modifications in the switching topology, and one supplementary clock phase. Consequently, a significant reduction of the low-frequency (1/f) noise is made possible and the usual differential amplifiers may be replaced by simple inverting amplifiers operated in class AB, featuring high-speed, low-quiescent power dissipation and low noise. An experimental micropower SC biquadratic filter section designed for `leapfrog' or `follow-the-leader feedback' structures has been developed using high gain (>80 dB) CMOS push/pull inverting amplifiers together with a three-phase clocking sequence. The integrated circuit, implemented in a low-voltage Si-gate CMOS process, achieves excellent accuracy and less than 5 /spl mu/W power dissipation with a 32 kHz sampling rate and /spl plusmn/1.5 V supplies; dynamic range is 66 dB.     

A fully integrated neural recording amplifier with DC input stabilization

This paper presents a low-power low-noise fully integrated bandpass operational amplifier for a variety of biomedical neural recording applications. A standard two-stage CMOS amplifier in a closed-loop resistive feedback configuration provides a stable ac gain of 39.3 dB at 1 kHz. A subthreshold PMOS input transistor is utilized to clamp the large and random dc open circuit potentials that normally exist at the electrode-electrolyte interface. The low cutoff frequency of the amplifier is programmable up to 50 Hz, while its high cutoff frequency is measured to be 9.1 kHz. The tolerable dc input range is measured to be at least +/- 0.25 V with a dc rejection factor of at least 29 dB. The amplifier occupies 0.107 mm2 in die area, and dissipates 115 microW from a 3 V power supply. The total measured input-referred noise voltage in the frequency range of 0.1-10 kHz is 7.8 microVrms. It is fabricated using AMI 1.5 microm double-poly double-metal n-well CMOS process. This paper presents full characterization of the dc, ac, and noise performance of this amplifier through in vitro measurements in saline using two different neural recording electrodes.