A Wide-Bandwidth 2.4 GHz ISM Band Fractional-N PLL With Adaptive Phase Noise Cancellation

A fast-settling adaptive calibration technique is presented that makes phase noise cancelling DeltaSigma fractional-N PLLs practical for the low reference frequencies commonly used in wireless communication systems. The technique is demonstrated as an enabling component of a 2.4 GHz ISM band CMOS PLL IC with a 730 kHz bandwidth, a 12 MHz reference, and an on-chip loop filter. In addition to the adaptive calibration technique, the IC incorporates a dynamic charge pump biasing technique to reduce power dissipation. The worst-case phase noise of the IC is -101 dBc/Hz and -124 dBc/Hz at 100 kHz and 3 MHz offsets, respectively, and the adaptive phase noise cancellation technique has a worst-case settling time of 35 mus . The IC is implemented in 0.18 CMOS technology. It measures 2.2 x 22 mm² and its core circuitry consumes 20.9 mA from a 1.8 V supply.     

A 4224 MHz low jitter phase-locked loop in 0.13-μm CMOS technology

A 4224 MHz phase-locked loop (PLL) is implemented in 0.13 μm CMOS technology. A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump. Dynamic mismatch of charge pump is considered. By balancing the switch signals of the charge pump, a good dynamic matching characteristic is achieved. A high-speed digital frequency divider with balanced input load is also designed to improve in-band phase noise performance. The 4224 MHz PLL achieves phase noises of-94 dBc/Hz and -114.4 dBc/Hz at frequency offsets of 10 kHz and 1 MHz, respectively. The integrated RMS jitter of the PLL is 0.57 ps (100 Hz to 100 MHz) and the PLL has a reference spur of-63 dB with the second order passive low pass filter.     

基于电感电容振荡器的电荷泵锁相环的设计

设计并实现了一种采用电感电容振荡器的电荷泵锁相环,分析了锁相环中鉴频/鉴相器(PFD)、电荷泵(CP)、环路滤波器(LP)、电感电容压控振荡器(VCO)的电路结构和设计考虑。锁相环芯片采用0.13μm MS&RF CMOS工艺制造。测试结果表明,锁相环锁定的频率为5.6～6.9 GHz。在6.25 GHz时,参考杂散为-51.57 dBc;1 MHz频偏处相位噪声为-98.35 dBc/Hz;10 MHz频偏处相位噪声为-120.3 dBc/Hz;在1.2 V/3.3 V电源电压下,锁相环的功耗为51.6 mW。芯片总面积为1.334 mm2。     

A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications

A CMOS phase-locked loop (PLL) which synthesizes frequencies between 6.336 and 8.976 GHz in steps of 528 MHz and settles in approximately 150 ns is presented. The proposed PLL can be employed as a building block for a frequency synthesizer which generates a seven-band hopping carrier for multiband orthogonal frequency division multiplexing (MB-OFDM) ultrawideband (UWB) radio. To achieve fast loop settling, integer-N architecture that operates with 528-MHz reference frequency is implemented and a wideband active-loop filter is integrated. An improved phase-frequency detector (PFD) is proposed for faster loop settling. To reduce reference sidebands, a feedback circuit using replica bias is implemented in the charge pump. I/Q carriers are generated by two cross-coupled LC VCOs. The output current of the charge pump is controlled to compensate for the VCO gain nonlinearity and a programmable frequency divider (12/spl les/N/spl les/17) that reliably operates at 9 GHz is designed. Fabricated in 0.18-/spl mu/m CMOS technology, the PLL consumes 32 mA from a 1.8-V supply and achieves phase noise of -109.6dBc/Hz at 1-MHz offset and spurs of -52 dBc.     

A 1.6-GHz CMOS PLL with on-chip loop filter

A 1.6-GHz phase locked loop (PLL) has been fabricated in a 0.6-μm CMOS technology. The PLL consists of an LC-tank circuit, divider, phase detector with charge pump, and an on-chip passive loop filter. When the oscillator is open loop, it exhibits -115 dBc/Hz phase noise at a 600-kHz offset from the carrier. The PLL occupies an active area of 1.6 mm² and dissipates 90 mW from a single 3-V supply     

一种超高频RFID阅读器中的双环锁相环

采用GF 130 nm CMOS工艺,设计了一种低功耗低噪声的电荷泵型双环锁相环,该锁相环可应用于符合国际及中国标准的超高频射频识别阅读器芯片。通过对双环锁相环在带宽和工作频率上的合理设置,以及对压控振荡器中变容二极管偏置电阻及电荷泵中参考杂散的理论分析和优化设计,改进了锁相环电路功耗和噪声性能。仿真结果表明,该锁相环在输出工作频率范围为840~960 MHz时,功耗为31.21 mW,在距中心频率840.125 MHz频偏100 kHz处的相位噪声为 -108.5 dBc/Hz,频偏1 MHz处的相位噪声为 -132.3 dBc/Hz。与同类锁相环相比较,本文电路在噪声和功耗方面具有一定优势。     

A 1.8-GHz Spur-Cancelled Fractional-N Frequency Synthesizer With LMS-Based DAC Gain Calibration

A 1.8-GHz wideband DeltaSigma fractional-N frequency synthesizer achieves the phase noise performance of an integer-N synthesizer using a spur-cancellation digital-to-analog converter (DAC). The DAC gain is adaptively calibrated with a least-mean-square (LMS) sign-sign correlation algorithm for better than 1% DAC and charge pump (CP) gain matching. The proposed synthesizer phase-locked loop (PLL) is demonstrated with a wide 400-kHz loop bandwidth while using a low 14.3-MHz reference clock, and offers a better phase noise and bandwidth tradeoff. Using an 8-bit gain-calibrated DAC, DeltaSigma-shaped divider ratio noise is suppressed by as much as 30 dB. The second-order DeltaSigma fractional-N PLL exhibits in-band and integrated phase noises of -98 dBc/Hz and 0.8deg. The chip, fabricated in 0.18-mum CMOS, occupies 2 mm², and consumes 29 mW at 1.8-V supply. The spur cancellation and correlation function consumes 30% additional power     

A 1-V 24-GHz 17.5-mW phase-locked loop in a 0.18-/spl mu/m CMOS process

A 1-V 24-GHz 17.5-mW fully integrated phase-locked loop employing a transformer-feedback voltage-controlled oscillator and a stacked divide-by-2 frequency divider for low voltage and low power is presented. Implemented in a 0.18-/spl mu/m CMOS process and operated at 24 GHz with a 1-V supply, the PLL measures in-band phase noise of -106.3 dBc at a frequency offset of 100 kHz and out-of-band phase noise of -119.1 dBc/Hz at a frequency offset of 10 MHz. The PLL dissipates 17.5 mW and occupies a core area of 0.55 mm/sup 2/.     

A 2.4-GHz ring-oscillator-based CMOS frequency synthesizer with a fractional divider dual-PLL architecture

A 2.4-GHz frequency synthesizer was designed that uses a fractional divider to drive a dual-phase-locked-loop (PLL) structure, with both PLLs using only on-chip ring oscillators. The first-stage narrow-band PLL acts as a spur filter while the second-stage wide-band PLL suppresses VCO phase noise so that simultaneous suppression of phase noise and spur is achieved. A new low-power, low-noise, low-frequency ring oscillator is designed for this narrow-band PLL. The chip was designed in 0.35-/spl mu/m CMOS technology and achieves a phase noise of -97 dBc/Hz at 1-MHz offset and spurs of -55 dBc. The chip's output frequency varies from 2.4 to 2.5 GHz; the chip consumes 15 mA from a 3.3-V supply and occupies 3.7 mm/spl deg/.     

A low jitter, low spur multiphase phase-locked loop for an IR-UWB receiver

A low jitter,low spur multiphase phase-locked loop(PLL) for an impulse radio ultra-wideband(IR-UWB) receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output.In this design,a noise and matching improved voltage-controlled oscillator(VCO) is devised to enhance the timing accuracy and phase noise performance of multiphase clocks.By good matching achieved in the charge pump and careful choice of the l...     

A 17-mW transmitter and frequency synthesizer for 900-MHz GSM fully integrated in 0.35-/spl mu/m CMOS

A fractional-N phase-locked loop (PLL) serves as a Gaussian minimum-shift keying (GMSK) transmitter and a receive frequency synthesizer for GSM. The entire transmitter/synthesizer is fully integrated in 0.35-/spl mu/m CMOS and consumes 17.4 and 12 mW from 2.5 V in the transmit and receive modes, respectively, including an on-chip voltage-controlled oscillator. The circuit meets GSM specifications on modulation accuracy in transmit mode, and measured phase noise from the closed-loop PLL is -148 dBc/Hz and -162 dBc/Hz, respectively, at 3- and 20-MHz offset. Worst case spur at 13-MHz offset is -77 dBc.     

A 14-GHz 256/257 dual-modulus prescaler with secondary feedback and its application to a monolithic CMOS 10.4-GHz phase-locked loop

A 14-GHz 256/257 dual-modulus prescaler is implemented using secondary feedback in the synchronous 4/5 divider on a 0.18-/spl mu/m foundry CMOS process. The dual-modulus scheme utilizes a 4/5 synchronous counter which adopts a traditional MOS current mode logic clocked D flip-flop. The secondary feedback paths limit signal swing to achieve high-speed operation. The maximum operating frequency of the prescaler is 14 GHz at V/sub DD/=1.8 V. Utilizing the prescaler, a 10.4-GHz monolithic phase-locked loop (PLL) is demonstrated. The voltage-controlled oscillator (VCO) operates between 9.7-10.4 GHz. The tuning range of the VCO is 690 MHz. The phase noise of the PLL and VCO at a 3-MHz offset with I/sub vco/=4.9 mA is -117 and -119 dBc/Hz, respectively. At the current consumption of I/sub vco/=8.1 mA, the phase noise is -122 and -122 dBc/Hz, respectively. The PLL output phase noise at a 50-kHz offset is -80 dBc/Hz. The PLL consumes /spl sim/31 mA at V/sub DD/=1.8 V.     

Current-mode phase-locked loop with constant-Q active inductor CCO and active transformer loop filter

This paper presents a current-mode phase-locked loop (PLL) with a constant-Q CMOS active inductor current-controlled oscillator (CCO) and a CMOS current-mode active-transformer loop filter. The constant-Q active inductor provides a large and swing-independent quality factor such that the phase noise of the CCO utilizing the constant-Q active inductor is comparable to that of CCO with spiral inductors. The current-mode active-transformer loop filter offers the advantage of a large and tunable inductance and low silicon consumption such that the loop bandwidth of the PLL can be made small and tunable. The PLL was designed in TSMC-0.18 μm 6-metal 1.8V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3v3 device models. The phase noise of the PLL was analyzed using Cadence’s Verilog-AMS behavioral modeling. The phase noise of the CCO with the constant-Q active inductor is ?123.1 dBc/Hz at 1 MHz frequency offset, over 10 dB better as compared with that of the CCO with conventional active inductors, and is only a few dB higher than that of the CCO with spiral inductors. The phase noise of the PLL with an active-transformer loop filter and a constant-Q CCO is ?116 dBc/Hz at 1 MHz frequency offset, nearly 20 dB lower than that of the PLL with the same active-transformer loop filter and a conventional active-inductor CCO. The lock time, power consumption, and phase noise of the PLL are 60 ns, 34 mW, and ?116 dBc/Hz at 1 MHz frequency offset, respectively. The total silicon consumption of the PLL excluding bond pads is 0.013 mm².     

A quad-band GSM-GPRS transmitter with digital auto-calibration

A low-power low-voltage fully integrated fast-locking quad-band (850/900/1800/1900-MHz) GSM-GPRS transmitter is described. It exploits closed-loop phase-locked loop (PLL) upconversion using a modulated fractional-N frequency synthesizer with digital auto-calibration. It uses a type-I PLL in a mostly digital IC with no external components and achieves a lock time of 43 /spl mu/s, a tuning range of 500 MHz, receive-band phase noise of -158dBc/Hz and -165 dBc/Hz for the high and low bands, respectively, and reference feed through of -93.9 dBc. It is implemented in 2.1 mm/sup 2/ using a 0.13-/spl mu/m CMOS process and meets all quad-band GSM transmitter specifications with a current consumption of only 28 mA from a single 1.5-V power supply.     

一种基于55nmCMOS工艺，输出频率0.1G-1.5G Hz的低抖动锁相环

本文设计了一种0.1G-1.5GHz,3.07pS RMS 抖动的多相位输出锁相环。通过引入双路径电荷泵,极大的减小了锁相环中的低通滤波器的尺寸。基于指定的功耗约束,提出了一种新颖的压控振荡器、电荷泵与鉴频鉴相器的尺寸优化方法,使用该方法,每个模块输出相位噪声减小了约3-6dBc/Hz。该锁相环在55nm的工艺下流片,集成了16pF的MOM电容,占用面积仅为0.05平方毫米。输出1.5GHz信号时,功耗2.8mW,相位噪声为-102dBc/Hz@1MHz。     

Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL

This paper demonstrates that spurious tones in the output of a fractional-N PLL can be reduced by replacing the $DeltaSigma$ modulator with a new type of digital quantizer and adding a charge pump offset combined with a sampled loop filter. It describes the underlying mechanisms of the spurious tones, proposes techniques that mitigate the effects of the mechanisms, and presents a phase noise cancelling 2.4 GHz ISM-band CMOS PLL that demonstrates the techniques. The PLL has a 975 kHz loop bandwidth and a 12 MHz reference. Its phase noise has a worst-case reference spur power of $-$ 70 dBc and a worst-case in-band fractional spur power of $-$64 dBc.      

An integrated 10 GHz low-noise phase-locked loop with improved PVT tolerance

An integrated phase-locked loop (PLL) with low phase noise is presented, which is robust with respect to variations of device parameters with process, supply voltage, and temperature (PVT). The low-noise CMOS voltage-controlled oscillator (VCO) employs two varactors for fine and coarse tuning. By using a CMOS charge pump with output biasing, the dc fine tuning voltage of the VCO and the loop dynamics of the PLL are well defined and fairly independent of PVT variations. Device noise in the charge pump and linearity of the phase detector are much improved by a two-transistor charge pump architecture for fine tuning. We measured a phase noise below −131 dBc/Hz at 10 MHz offset and below −94 dBc/Hz at 10 kHz offset over a tuning range of 1.2 GHz. An integrated phase error below 0.6° was measured, corresponding to an rms jitter below 160 fs. The chip was produced in a 0.25 μm low-cost SiGe BiCMOS technology, occupies a chip area of 2.25 mm² and draws 60 mA from a 3 V supply.     

一种快速捕获、带宽可调的锁相环电路

设计实现了一个快速捕获,带宽可调的电荷泵型锁相环电路。采用了一种利用状态机拓展鉴频鉴相器检测范围的方法,加快了环路的锁定;通过SPI总线实现电荷泵电流配置和调整VCO延时单元的延迟时间,优化了电路性能。芯片采用中芯国际0.18μmCMOS工艺,测试结果表明,锁相环锁定在100MHz时的抖动均方值为24ps,偏离中心频率1MHz处的相位噪声为-98.62dBc/Hz。     

A 1.41–1.72 GHz sigma-delta fractional-N frequency synthesizer with a PVT insensitive VCO and a new prescaler

A 1.41–1.72 GHz fractional-N phase-locked loop (PLL) frequency synthesizer with a PVT insensitive voltage-controlled oscillator (VCO) is presented. In this PLL, a VCO with process, voltage, and temperature (PVT) insensitive bias circuit, and a divided-by-7/8 prescaler with improved multi-phase frequency divider are adopted. A novel multi-stage noise shaping (MASH) sigma-delta modulator (SDM) is adopted here. A new combination of low-current-mismatch charge pump (CP) and a phase/frequency detector (PFD) is proposed in this paper. Using Hejian Technology CMOS 0.18 μm analog and digital mixed-mode process, a fractional-N PLL prototype circuit is designed, the VCO in the prototype circuit can operate at a central frequency of 1.55 GHz, and its phase noise is −121 dBc/Hz at 1.0 MHz, the variety of phase noise is depressed by about 1.4 dB with the help of PVT insensitive bias. Under a 1.8-V supply voltage, the phase noise of the PLL is −113 dBc/Hz at 1.0 MHz.