Enhanced CRC-based correction of multiple errors with candidate validation

Cyclic redundancy checks (CRC) are widely used in transmission protocols to detect whether errors have altered a transmitted packet. It has been demonstrated in the literature that CRC can also be used to correct transmission errors. In this paper, we propose an improvement of the state-of-the-art CRC-based error correction method. The proposed approach is designed to significantly increase the error correction capabilities of the previous method, by handling a greater part of error cases through the management of candidate lists and using additional validations. Simulations and results for wireless video communications over 802.11p and Bluetooth Low Energy illustrate the Peak Signal-to-Noise Ratio (PSNR) and visual quality gains achieved with the proposed approach versus the state-of-the-art and traditional approaches. These gains range on average from 1.6 dB to 7.3 dB over Bluetooth Low Energy channels with Eb/No ratio of 10 dB and 8 dB, respectively.     

A method for automatic design error location and correction in combinational logic circuits

We present a new diagnostic algorithm, based on backward-propagation, for localising design errors in combinational logic circuits. Three hypotheses are considered, that cover all single gate replacement and insertion errors. Diagnosis-oriented test patterns are generated in order to rapidly reduce the suspected area where the error lies. The originality of our method is the use of patterns which do not detect the error, in addition to detecting patterns. A theorem shows that, in favourable cases, only two patterns suffice to get a correction. We have implemented the test generation and diagnosis algorithms. Results obtained on benchmarks show that the error is always found, after the application of a small number of test patterns, with an execution time proportional to the circuit size. This work is partially supported by EUREKA “JESSI-AC3” project and the ESPRIT Basic Research Action CHARME Working Group #6018.     

VLSI logic design with logic programming and knowledge-basetechnology

An approach to VLSI logic design using partial and general structural specifications in addition to behavioral specifications is developed. This approach requires a new style of programming technique, especially if a universal solution procedure for all types of architectures is needed. Knowledge of the design process involves unification of the heterogeneous (i.e. behavior and structure) information between a system and its parts, as well as representation of functional modules in order to ensure their reusability in an efficient manner. Following these strategies, a logic synthesis expert system, ProLogic, is developed, and the system is evaluated using MPU-type VLSIs. It is found that the universal connecting procedure for any compound functional module that unifies the behavioral and structural specifications between a total module and its parts improves logic design efficiency by a factor of 2 and that logic programming, object-oriented frames, and rule bases implemented in ProLogic improve software productivity by a factor of 5     

Detection and correction of transmission errors in facsimile images

Today, facsimile is recognized as the primary communication tool for both printed and written materials. Most facsimile machines operating on public switched telephone networks use the Group 3 (G3) facsimile compression standards, in which images are entropy-coded. Although the synchronization codeword end of line (EOL) is employed, a transmission error in a codeword may cause the current codeword, the subsequent codewords in the current line, even the codewords in the subsequent lines to be misinterpreted, resulting in a great degradation of the received image. The objective of the proposed error detection and correction approaches is to completely or partially eliminate transmission errors in G3 facsimile images, requiring no extra transmission bit rate and without changing the transmitter and the receiver. The proposed approaches are based on the error checking conditions derived from the relationship between the current line and the previous line as well as the constraints on compressed image data. A corrupted line is detected if any of the error checking conditions is satisfied. When a corrupted line is detected, a sequence of bit inversions and redecoding operations are performed on the current corrupted line and/or its previous lines so that at least one possible (feasible) redecoding solution can be found. Then, the best solution is selected by using some selection criterion. Based on simulation results, the proposed approaches can recover the original or high-quality facsimile images from their corresponding corrupted facsimile images. This shows the feasibility of the proposed approaches     

Offline correction of microwave-network-analyser reflection-coefficient errors

This program has been developed to correct certain errors arising in the use of microwave-network-analyser systems. In using a network analyser to measure the reflection coefficient, errors arise from imperfections in directional couplers, source and other mismatches and crosstalk and inaccurate tracking between test and reference channels. This program facilitates calibration of the system and corrects the measurement data obtained. The use of error correction can also extend the useful frequency range of the analyser. In addition, the program can modify data for various reference planes and has facilities for graphical output on a Smith-chart display. The program was designed to run on an ICL 4100 series computer with incremental plotter, magnetic tape handlers and paper-tape station, in addition to card reader and line-printer.     

Temperature effects on BTI and soft errors in modern logic circuits

Since thermal responses of the drive current in recent 3D FinFET and conventional planar transistors are different, addressing performance and reliability in advanced VLSI circuits must be reconsidered. This study investigates temperature effects on two of the most problematic reliability issues in modern logic circuits, namely Bias Temperature Instability (BTI) and soft errors. In particular, we initially examine the inversion of temperature effect that strengthens the drive current in 14-nm bulk tri-gate FinFETs with increasing temperature, and model it as a source of threshold voltage reduction. This temperature-induced threshold voltage variation is consequently adapted into our proposed simulation and analysis framework for BTI degradation in large combinational circuits. The BTI aging results from our proposed estimation are more pessimistic than that from the conventional approach where the temperature effect is excluded. Simulation results show that long-term BTI aging delay worsens as temperature increases, yet the domination of thermal effect on the drive current leads to overall performance improvement in all circuits under 10-year BTI stress. In addition, soft errors and their masking probabilities in logic circuits are addressed under the inversion of temperature effect and supply voltage variation. The results reveal that soft error immunity in all experimental circuits improves significantly with increasing supply voltage and temperature, mainly due to the increase of critical charge. The average relative soft error rate when the supply voltage changes from 0.4 V to 0.6 V and 0.8 V at 0 °C is as low as 3.7% and 0.08% of the average result at 0.4 V, respectively. On average, the relative soft error rate at a particular supply voltage when temperature changes from 0 °C to 40 °C, 80 °C, and 120 °C is around 70%, 50%, and 30% of the average result at 0 °C, respectively.     

Automatic correction of registration errors in surgical navigation systems

Surgical navigation systems are used widely among all fields of modern medicine, including, but not limited to ENT- and maxillofacial surgery. As a fundamental prerequisite for image-guided surgery, intraoperative registration, which maps image to patient coordinates, has been subject to many studies and developments. While registration methods have evolved from invasive procedures like fixed stereotactic frames and implanted fiducial markers toward surface-based registration and noninvasive markers fixed to the patient's skin, even the most sophisticated registration techniques produce an imperfect result. Due to errors introduced during the registration process, the projection of navigated instruments into image data deviates up to several millimeter from the actual position, depending on the applied registration method and the distance between the instrument and the fiducial markers. We propose a method that allows to automatically and continually improve registration accuracy during intraoperative navigation after the actual registration process has been completed. The projections of navigated instruments into image data are inspected and validated by the navigation software. Errors in image-to-patient registration are identified by calculating intersections between the virtual instruments' axes and surfaces of hard bone tissue extracted from the patient's image data. The information gained from the identification of such registration errors is then used to improve registration accuracy by adding an additional pair of registration points at every location where an error has been detected. The proposed method was integrated into a surgical navigation system based on paired points registration with anatomical landmarks. Experiments were conducted, where registrations with deliberately misplaced point pairs were corrected with automatic error correction. Results showed an improvement in registration quality in all cases.     

The analysis and design of CMOS multidrain logic and stacked multidrain logic

A CMOS logic circuit called the CMOS multidrain logic (MDL) is proposed, analyzed, and experimentally observed. The basic circuit structure, which is derived from integrated injection logic, consists of an enhancement-mode MOSFET as a current injector and a multidrain MOSFET with drain terminals as output nodes and the gate terminal as input node. As compared with the multidrain NMOS logic, the difference is that an enhancement MOS instead of a depletion NMOS is used as a current injector.     

Partial correction of transmission errors in Walsh transform image without recourse to error correction coding

A sequency difference detection and correction (s.d.d.c.) system is described which enables the partial correction of transmission errors in a Walsh-Hadamard transform image to be achieved without channel coding. Using a first-order two-dimensional random Gaussian Markov field as the image, the percentage mean-square error in the recovered signal is reduced with the aid of the s.d.d.c. system by two orders of magnitude for transmission error rates <3%.     

Analysis and correction of errors in a polarimeter for Faraday rotation measurements

Sources of error in polarization measurements on electromagnetic waves are investigated. A method is described for correcting the error in the measurement of a Faraday rotation in propagation from a geostationary satellite by calibrating the receiving system.     

Parameter spectrum in spectral multiple-valued logic design

A Chrestenson transform over the p-valued logic domain is introduced. The parameter spectral coefficients, which consist of p parameters, from the transform are interpreted as measures of the dependence of the logic function on the linear logic functions. Six spectral operations and their applications to p-valued logic design are presented.     

RTD多值逻辑电路原理与电路模拟

由共振隧穿二极管(RTD)和高电子迁移率晶体管(HEMT)构成的多值逻辑(MVL)电路可以用最少的器件来完成一定的逻辑功能,达到大大简化电路的目的。共振隧穿二极管和高电子迁移率晶体管属于量子器件,具有高频高速的特点,所以这一逻辑电路有很好的应用前景。本文就多值逻辑电路中的几个典型电路用Pspice软件进行电路模拟,得到了与理论分析一致的模拟结果。     

射电成像中电离层扰动的最小熵校正方法

在合成孔径射电成像中,电离层的扰动会在接收信号中引入相位误差,导致图像出现模糊和漂移。本文提出了一种新方法,以校正这种相位误差。使用熵作为衡量射电天文图像质量的指标,熵越小代表图像质量越高,当熵值达到最小时,认为相位误差被校正。相比其他传统方法,本方法仅利用脏图本身就能够校正相位误差。     

设计模式在业务逻辑层中的应用

传统的软件应用系统一般采用3层应用框架,业务逻辑层代码中混杂各种数据库调用语句,严重影响系统的可扩展性、可复用性、可维护性。从设计模式考虑,提出从业务逻辑层分出数据接口层,负责与数据层沟通,实现业务逻辑层与数据层的真正独立,提高系统的可扩展性、可复用性和可维护性,并通过具体应用实例实现数据访问对象(DAO)设计模式。     

设计模式在业务逻辑层中的应用

传统的软件应用系统一般采用3层应用框架,业务逻辑层代码中混杂各种数据库调用语句,严重影响系统的可扩展性、可复用性、可维护性.从设计模式考虑,提出从业务逻辑层分出数据接口层,负责与数据层沟通,实现业务逻辑层与数据层的真正独立.提高系统的可扩展性、可复用性和可维护性,并通过具体应用实例实现数据访问对象(DAO)设计模式.     

Balance testing and balance-testable design of logic circuits

We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome testing, it detects faults by checking the difference between the number of ones and the number of zeros in the test response sequence. A key advantage of balance testing is that the testability of various fault types can be easily analyzed. We present a novel analysis technique which leads to necessary and sufficient conditions for the balance testability of the standard single stuck-line (SSL) faults. This analysis can be easily extended to multiple stuck-line and bridging faults. Balance testing also forms the basis for design for balance testability (DFBT), a systematic DFT technique that achieves full coverage of SSL faults. It places the unit under test in a low-cost framework circuit that guarantees complete balance testability. Unlike most existing DFT techniques, DFBT requires only one additional control input and no redesign of the underlying circuit is necessary. We present experimental results on applying balance testing to the ISCAS 85 benchmark circuits, which show that very high fault coverage is obtained for large circuits even with reduced deterministic test sets. This coverage can always be made 100% either by adding tests or applying DFBT.This research was supported by the National Science Foundation under Grant No. MIP-9200526. Parts of this paper were published in preliminary form in Proc. 23rd Symp. Fault-Tolerant Computing, Toulouse, June 1993, and in Proc. 31st Design Automation Conf, San Diego, June 1994.     

基于决策列表的中文同音词自动识别与校对

中文文本校对是自然语言处理领域重要课题,在汉语校对中,文本错误有很多种,其中同音词错误占很大的比例,文中提出一种基于决策列表的方法,首先手工整理出常见的1000对同音词混淆集,通过大量语料训练出2元模型和上下文语境模型,校对文本时提取词以及它所有同音词的2元特征和上下文特征,根据训练好的模型计算出支持度,这就是同音词组决策列表的构建,从决策列表中判断哪个词的支持度最高,从而实现同音词自动查错与纠错。最后,为了改善由于数据稀疏带来的问题,文章用同义词聚类对实验进行了改进,提高了召回率等。根据实验,这种方法能有效的解决同音词错误。     

Digital estimation and correction of DAC errors in multibitΔΣ ADCs

An adaptive digital algorithm is described for acquiring and correcting the errors of the feedback DAC used in a multibit ΔΣ ADC. The method is highly accurate, and is particularly useful for wideband ADCs, where mismatch error shaping becomes ineffective     

Logic design error diagnosis and correction

Logic verification tools are often used to verify a gate-level implementation of a digital system in terms of its functional specification. If the implementation is found not to be functionally equivalent to the specification, it is important to correct the implementation automatically. This paper describes a formal method for the diagnosis and correction of logic design errors in an incorrect gate-level implementation. We use Boolean equation techniques to search for potential error locations. An efficient search and pruning algorithm is developed by introducing the notion of immediate dominator set. Two correction procedures are proposed. Gate correction corrects errors such as wrong gate type, missing inverters, etc.; line correction corrects errors such as missing wires and wrong connections. Our method is robust and covers all, simple design errors described by Abadir et al. (1988). Experimental results for a set of ISCAS and MCNC benchmark circuits demonstrate the effectiveness of the proposed techniques     

Use of n-cubes in the design of logic circuits

A method of visualising n-cubes is presented, which may make n-cubes more convenient in logic design than the more usual Karnaugh maps.