DDFSGEN

This paper presents a functional compiler for the automatic design of Direct Digital Frequency Synthesizer (DDFS) integrated circuits (ICs) using a ROM based table look-up architecture. The compiler allows the user to specify high-level specifications such as the acceptable spurious response and it generates the IC architecture, floorplan, and layout. To construct the layout for different specifications, a library of parameterized macrocells has been developed in 1.2 m CMOS technology.A test chip with a quadrature DDFS module has been generated, using the compiler, and fabricated. The chip has two input signals: one is for frequency control while the other is for phase initialization. Input and output word lengths are 16 bits and 6 bits respectively. The chip complexity is approximately 12,000 transistors (DDFS core) and the die size is 4.8×2.9mm ². A maximum sample rate of 80 MHz has been attained implying a maximum sine (cosine) output frequency of 40 MHz and a frequency resolution of 1.22 kHz. The maximum spurious level measured is –46 dB.     

A 9 b/12 b 50 MS/s experimental ADC with continuous approximation architecture in 65 nm CMOS

A 9 bits 50 MS/s 0.5 mW continuous approximation mixed successive approximation (CAR&SAR) ADC is presented. A 12 bits 50 MS/s 0.6 mW CAR&CAR ADC is presented. In the field of low power and high performance ADC, CAR is a new architecture different from SAR. It is faster and easier to get high accuracy. Here we will introduce CAR and its circuit implementation, and the 9 bits experimental ADC is designed to verify CARADC''s feasibility. Meanwhile, its resolution can be extended to 12 bits with adding an extra CAR, and then the performance is raised to 0.6 mW 50 MS/s 72 dB SNDR at TT corner and the Walden FOM is 3.6 fj/conv-step. The 9 b ADC was fabricated by using TSMC 1P9M 65 nm CMOS technology. The ADC achieves 50 dB SNDR and the realized Walden FOM is 34 fj/conv-step. The simulation and measurement results prove that CAR is available in the low power and high performance ADC and it even outperforms SAR. The ADC core occupies an active area of 0.045 mm².     

An Architectural Comparison and CMOS Implementation of Sixth-Order Cascaded ΣΔ Modulator

A sixth-order cascaded sigma-delta modulator isreported aiming low power data-converter architectures.Behavioral simulation shows that the cascaded (2-1-1-2)architecture is the most robust in terms of noiseperformance and accuracy. A prototype of this architecture was fabricated using a 2 m analogCMOS process. Measured results indicate that the modulator achieved 89 dB (14.8-b) peak in-bandsignal-to-noise ratio (SNR) and 92 dB (15.3-b) dynamicrange (DR) for a 32 kHz bandwidth, at a sampling rate ofonly 1 MHz. The modulator dissipated 79 mW from a±3.3 V supply voltage and only 45 mW from a±2.5 V supply voltage with negligible SNRdeterioration. Process scaling and supply-voltagescaling can thus drastically reduce power dissipationusing this architecture while maintaining high SNR andDR performance.     

一种16位1 GS/s电流舵型DAC的设计

设计了一种基于UMC 0.18μm CMOS工艺的16位1GS/s的电流舵型D/A转换器。该DAC采用7+4+5分段结构,1.8V/3V双电源供电,满摆幅输出电流为20mA。采用四开关结构、限幅开关驱动电路、两个cascode管的单位电流源以及两层结构的逻辑译码器,实现了优异的性能。在1GHz采样率、101.07MHz输入信号下,无杂散动态范围(SFDR)达到78.06dB。     

Design-to-testing: a low-power, 1.25 GHz,single-bit single-loop continuous-time $$\Delta \Sigma$$ modulator with 15 MHz bandwidth and 60 dB dynamic range

Continuous-time Delta-Sigma (CT-\(\Delta \Sigma\)) analog-to-digital converters have been extensively investigated for their use in wireless receivers to achieve conversion bandwidths >15 MHz and higher resolution of 10–14 bits. This paper presents the complete design-to-testing tutorial of a state-of-the-art high-speed single-bit CT-\(\Delta \Sigma\) architecture and its circuit design details in 0.13 μm CMOS technology node sampling at 1.25 GS/s. The designed modulator achieves higher dynamic range of 60 dB in a wide conversion bandwidth of 15 MHz and consumes only 3.5 mW. The proposed modulator achieves a Figure of Merit of 154 fJ/level.     

A 10-bit 50 MS/s Pipelined ADC With Capacitor-Sharing and Variable-$g_{m}$ Opamp

A pipelined analog-to-digital converter (ADC) architecture which is suitable for low power and small area is presented. The prototype ADC achieves 10-bit resolution with only two opamps by removing a front-end sample-and-hold amplifier (SHA) and sharing an opamp between two successive pipeline stages. The errors from the absence of SHA and opamp-sharing are greatly reduced by the proposed techniques and circuits. Further reduction of power and area is achieved by using a capacitor-sharing technique and variable- $g_{m}$ opamp. The ADC is implemented in 0.18 $muhbox{m}$ CMOS technology and occupies a die area of 0.86 ${hbox{mm}}^{2}$. The differential and integral nonlinearity of the ADC are less than 0.39 LSB and 0.81 LSB, respectively, at full sampling rate. The ADC achieves 56.2 dB signal-to-noise plus distortion ratio, 72.7 dB spurious free dynamic range, ${-}$66.2 $~$dB total harmonic distortion, 9.03 effective number of bits for a Nyquist input at full sampling rate, and consumes 12 mW from a 1.8 V supply.      

Demonstration of using multi-band 16-QAM OFDM modulation with direct-detection in 10 GHz bandwidth for 37.3-Gb/s PON

We propose and experimentally demonstrate a 37.3 Gb/s passive optical network using four-band orthogonal-frequency-division-multiplexing (OFDM) channels within 10 GHz bandwidth. Here, the required sampling rate and resolution of digital-to-analog/analog-to-digital (DA/AD) converter are only 5 GS/s and 8 bits to accomplish the 40 Gb/s OFDM downstream rate. Moreover, to reduce the power fading and fiber chromatic dispersion issues, a $-$ 0.7 chirp parameter Mach-Zehnder modulator is used for the four-band OFDM modulation scheme. Downstream negative power penalty of $-$ 0.37 dB can be obtained at the bit error rate of $3.8\times 10^{-3}$ after 20 km standard single mode fiber transmission without dispersion compensation.     

High-Speed CMOS Track/Hold Circuit Design

This paper describes the design of a high-speed CMOSTrack/Hold circuit in front of an ADC. The Track/Hold circuit employsdifferential open-loop architecture, very linear source follower inputbuffers, NMOS sampling switches and bootstrap sampling-switch drivercircuits for high-speed operation with 3.3 V supply voltage. SPICEsimulations with MOSIS 0.35 m CMOS BSIM3v3 parameters showed thatit achieves a signal-to-(noise+distortion)-ratio (SNDR) of morethan 50 dB for up to 100 MHz sinusoidal input at 200 MS/s with 40 mWpower consumption.     

Linear relationship ADC with complimentary switch-based bootstrapped sample and hold circuit

This paper presents the design, fabrication and tested results of an analogue-to-digital converter (ADC) using linear relationship ratio of comparator and resolution. An original N-bit flash architecture uses 2^N?1 comparators (N = resolution), while the proposed architecture uses only N comparators for N-bit making it a linear relationship design. This paper also deals with the design of sample and hold circuit that utilises clock bootstrapping technique which allows sampling at peak voltages and helps in minimising charge injection errors, attaining 125 µV for the proposed design. The proof of concept of 4-bit prototype ADC using 1P?2M is fabricated using AMIS 500 nm CMOS C5X technology and the experimental results at a sampling rate of 800 MS/s reveal an effective no. of bit of 3.34 bits, signal-to-noise ratio of 24.44 dB and differential non-linearity and integral non-linearity of 0.42 and 0.40, respectively. The converter consumes 7 mW power when operated on 2.5 V supply and occupies 0.014 mm² chip area.     

A VLSI decoder for a new type of constellations adapted to the Rayleigh Fading Channel

Diversity is the key solution to obtain efficient channel coding in wireless communications, where the signal is subject to fading (Rayleigh Fading Channel). For high spectral efficiency, the best solutions used nowadays are based on QAM constellations of 1-order diversity, associated with a binary code or a trellis coded modulation to increase the overall diversity. It has been shown that a new class of d-dimensional non-QAM constellations, named -constellations, can bring a d-order diversity without the addition of redundancy. Combined with classical coding techniques, -constellations are very efficient. However, the decoding algorithm is far more complicated for -constellations than for QAM-constellations. A sub-optimal algorithm that allows the decoding of -constellations is proposed. An example of an application for a 4 bits/Hz/s spectral efficiency with a 4-D -constellation is given. The VLSI architecture of the decoder is described. The implementation leads to 72 K gates, a binary rate of 32 Mbits/s and a BER of 10^-3 for a SNR of 14 dB.     

A 63 mA 112/94 dB DR IF Bandpass $DeltaSigma$ Modulator With Direct Feed-Forward Compensation and Double Sampling

We developed a 10.7 MHz intermediate frequency bandpass discrete-time 4th-order 4-bit $DeltaSigma$ modulator for AM/FM car radio tuners. Using direct feed-forward compensation and double sampling, we have achieved a dynamic range (DR) of 112 dB in the 3 kHz AM bandwidth (BW) and a DR of 94 dB in the 200 kHz FM BW. The modulator occupies 3 ${hbox {mm}}^{2}$ , in 0.15 $mu{hbox {m}}$ CMOS technology, and draws 63 mA of current.      

22 μm-pitch 9-bit Column-Parallel Overlapping-Subrange SAR (CPOSSAR) ADC

The Column-Parallel Overlapping-Subrange Successive-Approximation-Register Analog-to-Digital Converter (CPOSSAR ADC) uses a 5-bit split capacitor DAC twice to achieve 9-bit resolution. Its total capacitor area is only 3% of a 9-bit binary weighted DAC and the average switching power is only 12% of a conventional 9-bit DAC. The ADC can perform a 9-bit conversion by first digitizing the 4 most significant bits (MSB) in a coarse conversion stage and then digitizing the 5 least significant bits (LSB) in a fine conversion stage. The accuracy requirement of the DAC is reduced by using overlapping subranges. The proposed ADC achieved an SFDR of 73.6 dB and a SINAD of 55 dB in post-layout simulation, corresponding to an ENOB of 8.8 bits. The design was fabricated in a TSMC׳s 0.35 μm high-voltage process. The use of overlapping subranges reduced the DNL error from +5.14/−1 LSB to +1.27/−0.92 LSB, and improved the INL error from +5.35/−5.34 LSB to +3.17/−3.18 LSB. At a sampling rate of 1.1 MS/s the ADC achieved 41.5 dB SFDR, 34.2 dB SINAD, and consumed 242 μW/channel dynamic power. An individual ADC channel is only 22 μm wide. COPSSAR ADCs are a factor of 4, 2, and 2.5 more area efficient than Multiple-ramp Single-slope ADCs, SAR ADCs, and Cyclic ADCs.     

Engineering of Facets,Band Structure,and Gas‐Sensing Properties of Hierarchical Sn2+‐Doped SnO2 Nanostructures

Hierarchical SnO₂ nanoflowers, assembled from single‐crystalline SnO₂ nanosheets with high‐index (11$ \bar 3 $ ) and (10$ \bar 2 $ ) facets exposed, are prepared via a hydrothermal method using sodium fluoride as the morphology controlling agent. Formation of the 3D hierarchical architecture comprising of SnO₂ nanosheets takes place via Ostwald ripening mechanism, with the growth orientation regulated by the adsorbate fluorine species. The use of Sn(II) precursor results in simultaneous Sn²⁺ self‐doping of SnO₂ nanoflowers with tunable oxygen vacancy bandgap states. The latter further results in the shifting of semiconductor Fermi levels and extended absorption in the visible spectral range. With increased density of states of Sn²⁺‐doped SnO₂ selective facets, this gives rise to enhanced interfacial charge transfer, that is, high sensing response, and selectivity towards oxidizing NO₂ gas. The better gas sensing performance over (10$ \bar 2 $ ) compared to (11$ \bar 3 $ ) faceted SnO₂ nanostructures is elucidated by surface energetic calculations and Bader analyses. This work highlights the possibility of simultaneous engineering of surface energetics and electronic properties of SnO₂ based materials.     

A High Voltage Line Driver for Subscriber Loop Interfaces in a Low Voltage Submicron BiCMOS Technology

This paper presents a 30 V line driver for short loop subscriber line interface circuit applications. The high voltage line drivers was implemented in a low-voltage 0.8 m BiCMOS process using 30 V extended-drain MOS transistors, fully compatible with the low voltage technology. Using a Quasi-Current Mirror architecture for the output stage, the line driver is capable of delivering more than 30 mA current into the lines with an idle current as low as 1 mA, satisfying the short loop requirements. With less than 0.24 mm² area, the circuit can be easily integrated with low-voltage circuitry on a single chip.     

Distributed Orthogonal and Quasi-Orthogonal Space-Time Block Code with Embedded AAF/DAF Matrix Elements in Wireless Relay Networks with Four Relays

We consider cooperative networks of one source, four relays, and one destination. Each of them has a single antenna. The four relays use a proposed full rate distributed quasi orthogonal space time block code (DQOSTBC) scheme. If the channel state between the source and a relay is above a threshold, we select the elements of the DQOSTBC matrix to be the decode-and-forward (DAF) type; if it is below the threshold, the corresponding elements are the amplify-and-forward (AAF) type. Thus the proposed scheme is a DQOSTBC matrix with embedded adaptive DAF/AAF elements. The bit error rate (BER) simulation results show that the proposed DQOSTBC is approximately 7 dB better than the traditional DQOSTBC (all matrix elements are fixed as DAF type) at a BER of $10^{-3}$ because traditional DQOSTBC loses full diversity due to errors in the information received. The proposed DQOSTBC is about 3 dB better than the rate 1/2 DOSTBC also proposed with adaptive DAF/AAF matrix elements at a BER of $10^{-3}$ at the same spectral efficiency of 2 bits/s/Hz.     

Wavelength-Insensitive Integrated-Optic Circuit Consisting of Asymmetric X-Junction Couplers for Recognition of BPSK Labels

We have proposed a label recognition integrated-optic circuits for photonic label switching using self-routing of the label pulses. Binary phase shift keying (BPSK) format is considered as the label. An identifying bit is placed ahead of the address bits in the label. The label recognition system consists of a tree-structure connection of asymmetric X-junction couplers. The system uses self-routing propagation of the identification bit controlled by the address bits. Asymmetric X-junction couplers have a feature of small dependence on wavelength. However, the wavelength dependence of optical circuits consisting of multiple asymmetric X-junction couplers depends strongly on its architecture. In this paper, we propose a wavelength insensitive architecture of the recognition circuit. The wavelength independence in the improved circuit is confirmed using finite-difference beam propagation method (FD-BPM). We numerically demonstrate that our proposed system can recognize all the binary-code labels in wavelength range of 1500–1600 nm with crosstalk less than ${-}25$ dB and ${-}15$ dB for label length three and four, respectively.      

A Novel Low Power 1 GS/s S&H Architecture With Improved Analog Bandwidth

A new sample-and-hold (S&H) architecture is proposed for time-interleaved analog-to-digital converter (ADC). The use of this S&H circuit in front-end of a time-interleaved ADC system eliminates the need for sample-time calibration. Using the techniques of precharging and output capacitor coupling along with a new sampling technique called middle-plate-sampling can mitigate the stringent performance requirements for the opamp and sampling switches, resulting in low power consumption and allowing very high sampling rate. Simulated by HSPICE with a standard BSIM3v3 0.18 $mu{hbox{m}}$ technology, the S&H achieves 10-12 bits resolution for a 1.6-${hbox{V}}_{ rm{pp}}$ output at 1-GHz sampling rate. The S&H dissipates 12 mW from a 1.8-V supply.      

A 24 GHz Amplitude Monopulse Comparator in 0.13 $mu$m CMOS

This letter presents the design and implementation of a wideband 24 GHz amplitude monopulse comparator in 0.13 $mu$m CMOS technology. The circuit results in 9.6 dB gain in the sum channel at 24 GHz with a 3-dB bandwidth of 23.0–25.2 GHz, and a sum/difference ratio of $> 25$ dB at 20–26 GHz. The measured input P1 dB is ${-}14.4$ dBm at 24 GHz. The chip is only 0.55$,times,$ 0.50 mm$^{2}$ (without pads) and consumes 44 mA from a 1.5 V supply, including the input active baluns and the differential to single-ended output stages (28 mA without the input and output stages). To our knowledge, this is the first demonstration of a high performance mm-wave CMOS monopulse comparator RFIC.      

An UTRA/FDD Direct-Downconversion Mixer in 0.25 μm CMOS

In this paper the design of a 2 GHz direct-downconversion mixer for a UTRA/FDD receiver is presented. The mixer is implemented using a standard low-cost 0.25 m, single-poly, six-metal CMOS process. An on-chip passive balun is used to generate a balanced RF input signal. In-house optimized device models are used for both active and passive components to achieve a voltage conversion gain of 12.8 dB, an iIP₂ of 25 dBm, an iIP₃ of –3.1 dBm, and a noise figure of 8 dB. The circuit provides I and Q signal path outputs while drawing 6 mA from a 2.5 V supply.     

W-Band Active Down-Conversion Mixer in Bulk CMOS

A W-band (76–77 GHz) active down-conversion mixer has been demonstrated using low leakage (higher ${rm V}_{{rm T}}$) NMOS transistors of a 65-nm digital CMOS process with 6 metal levels. It achieves conversion gain of ${-}8$ dB at 76 GHz with a local oscillation power of 4 dBm (${sim-}2$ dBm after de-embedding the on-chip balun loss), and 3 dB bandwidth of 3 GHz. The SSB noise figures are 17.8–20 dB (11.3–13.5 dB after de-embedding on-chip input balun loss) between 76 and 77 GHz. ${rm IP}_{1{rm dB}}$ is ${-}6.5$ dBm and IIP3 is 2.5 dBm (${sim-}13$ and ${sim}-4$ dBm after de-embedding the on-chip balun loss). The mixer consumes 5 mA from a 1.2 V supply.