振荡神经网络的建模与动态联想记忆

本文提出一种全程耦合映射格子式的振荡神经网络模型，该模型具有丰富的非线性动力学行为，在其联想记忆的数值模拟中，观察到同步振荡和时空混沌现象。该网络的动态特性有助于区分具有相同吸引子的不同模式。     

一种新的高阶联想存贮模型

由于Kohonen模型对噪声极端敏感，Murakami提出一个利用带噪输入优化Kohonen模型的最小平方联想存贮模型（LSAM），大大降低了原有模型的噪声敏感性。但是与Kohonen模型一样，LSAM模型的联想存贮能力随着样本数的增加而大大下降。本文提出一种高阶联想存贮模型，对LSAM模型作了改进，使原有模型的联想存贮能力得到极大地提高。计算机模拟结果证实了这一点。     

正则模糊联想记忆

本文提出了一种特殊的模糊联想记忆系统（ＦＡＭ）一正则数据联想记忆及其学习算法－正则学习算法，正则模糊联想记忆具有比一般方法所设计的模糊联想记忆更好的性能，且其性能受训练数据不足和训练数据噪声的影响很小，最后，举例说明了正则模糊联想记忆在模糊控制器的应用。     

复值多状态双向联想记忆神经网络

离散但非二值状态将提供一种更好的信息表达方式。本论文中,我们将复符号操作子（ｃｏｍｐｌｅｘ－ｓｉｇｎｕｍ ｏｐｅｒａｔｉｏｎ）和双向联想记忆（Ｂｉｄｉｒｅｃｔｉｏｎａｌ Ａｓｓｏｃｉａｔｉｖｅ Ｍｅｍｏｒｙ,ＢＡＭ）结合起来并提出了一种非二值ＢＡＭ,即复值多状态双向联想记忆神经网络（Ｃｏｍｐｌｅｘ－Ｖａｌｕｅｄ Ｍｕｌｔｉｓｔａｔｅ Ｂｉｄｉｒｅｃｔｉｏｎａｌ Ａｓｏｃｉａｔｉｖｅ Ｍａｍｏｒｙ,     

一个高性能的相关编码联想存贮模型

传统的二层联想存贮器具有有限的存贮能力和缺乏非线性映射能力，本文将通过存贮结构的扩展，获得极高的联想性能和非线性映射能力，通过信噪比分析证实了所提模型的优越性。     

Winner-Takes-All Associative Memory: A Hamming Distance Vector Quantizer

We present a design methodology for mapping neuralyinspired algorithms for vector quantization, into VLSI hardware.We describe the building blocks used: memory cells, current conveyors,and translinear circuits. We use the basic building blocks todesign an associative processor for bit-pattern classification;a high-density memory based neuromorphic processor. Operatingin parallel, the single chip system determines the closest match,based on the Hamming distance, between an input bit pattern andmultiple stored bit templates; ties are broken arbitrarily. Energyefficient processing is achieved through a precision-on-demandarchitecture. Scalable storage and processing is achieved througha compact six transistor static RAM cell/ALU circuit. The singlechip system is programmable for template sets of up to 124 bitsper template and can store up to 116 templates (total storagecapacity of 14 Kbits). An additional 604 bits of auxiliary storageis used for pipelining and fault tolerance re-configuration capability.A fully functional 6.8 mm by 6.9 mmchip has been fabricated in a standard single–poly, double–metal2.0µmn–well CMOS process.     

Dynamic reconfiguration schemes for megabit BiCMOS SRAMs and performance evaluation

In this paper two dynamic configuration schemes are discussed for megabit BiCMOS static random access memories (SRAMs). Dynamic reconfiguration schemes allows failure detection at the chip level and automatic reconfiguration to fault free memory cells within the chip. The first scheme is a standby system approach where the I/O lines of the memory can be dynamically switched to spare bit slices in the SRAM. This scheme is implemented through a switching network at the memory interface. Every memory access is controlled by a fault status table (FST) which memorizes the fault conditions of each memory block. This FST is implemented outside the memory system. A second dynamic reconfiguration scheme for BiCMOS SRAMs is addressed through a graceful degradation approach. Basic design considerations and performance evaluation of megabit BiCMOS SRAMs using dynamic reconfiguration schemes are presented. The basic properties of the proposed schemes and a prototype VLSI chip implementation details are discussed. BiCMOS SRAM access time improvement of about 35%, chip area of 25%, and chip yield of 10% are achieved, respectively, as compared to conventional methods. A comparison of reliability improvement of 1 Mb BiCMOS SRAMs using dynamic configuration schemes is presented. These two dynamic reconfiguration schemes have considerable importance in reliability improvement when compared to conventional methods. The major advantage is that the size of reconfiguration of the system can be considerably reduced.     

约束最小平方双向联想存贮器

基于Ｋｏｓｋｏ的双向联想贮存和Ｋｏｈｏｎｅｎ的广义逆存贮的思想。本文提出了一种约束最小平方双向联想存贮器模型，其联想存贮阵满足Ｌｙａｐｕｎｏｖ型方程。     

光学模糊联想神经网络

本文提出一种模糊联想神经网络的非相干光学实现系统。利用空间区域编码技术和阴影投射系统，模糊联想存贮器所需的矩阵－矢量最大－最大合成运算可得到光学实现。给出了实验结果。     

TLM: a trench leakage monitor for a four megabit SPT DRAMtechnology

The authors discuss a single trench capacitor macro-array structure used for trench dynamic random access memory (DRAM) device design and characterization, and as a manufacturing test vehicle. A nonaddressable array of trench-capacitor DRAM cells is used for quantification of trench DRAM leakage parameters, storage node parasitic device characterization, and silicon defects. Used with an addressable functional monitor, it is found to be a valuable semiconductor process development vehicle to achieve functionality and cell retention yield for a 4-Mb CMOS DRAM technology     

基于环形结构的联想记忆网络

本文针对ＢＡＭ和ＴＡＭ网络处理数据串联想时的困难和不足，提出了一种基于环形结构的联想记忆网络，称为环形联想记忆网络（ＣＡＭ），给出了网络的拓扑结构和网络的三种基本联想模式，讨论了存储网络连接权所需要的存储量，并与ＢＡＭ和ＴＡＭ联想记忆网络进行了比较，最后给出了实验研究的结果。     

时空混沌控制在联想记忆中的应用

本文提出了一种具有时空混沌控制的联想记忆网络.实验结果表明:具有目标信息的一部分知识的初始输入能在时空混沌的参数控制中成功地完成联想记忆,根据提出的学习算法,该网络的记忆搜索性能和记忆容量比Hopfield模型有较大改善.同时发现联想记忆成功率与强化因子、样本数、信息率、学习阈值以及初始混沌参数有关.     

分形细胞神经网络用于联想记忆

本文提出了分形细胞神经网络，并成功地应用于联想记忆，从模拟结果看，分形细胞神经网络的联想记忆能力好于Ｂａｒａｍ提出的分形神经网络。     

双向联想记忆中的互余编码问题

互余编码及连续性要求对双向联想记忆的容量及回忆有着很大影响，Ｓｉｍｐｓｏｎ，Ｊｅｎｇｅｔ．ａｌ．提出了各自的解决方法（ＩＢＡＭ，ＭＩＢＡＭ），他们的方案的实质就是增加层内神经元间的连接，本文首先证明了ＩＢＡＭ没能解决互余编码问题，借助计算机模拟发现ＭＩＢＡＭ容量也非常有限，且只是在一定程度上能克服互余编码，通过对ＭＩＢＡＭ引入高阶，我们提出了ＨＯＭＩＢＡＭ，它能有效地解决前述两问题，从而有着较大的容量与较好的回忆性能     

连续双向联想记忆模型的稳定性分析

对于连续型Ｈｏｐｆｉｅｌｄ模型的平衡态特征，目前人们已经得到了很多富有意义的成果，本文说明，连续Ｈｏｐｆｉｅｌｄ模型的大部分结论都可以推广到连续双向联想记忆模型，我们重点讨论了平衡态条件、渐近稳定性以及围绕一稳定平衡点的吸引域等问题，所得到的结论对于ＢＡＭ的设计和应用都是很有意义的。     

Hopfield型联想记忆神经网络一种新的分析方法

本文通过定义一种新的能量函数，分析了Ｈｏｐｆｉｅｌｄ型神经网络的渐近稳定性与联想记忆问题，得到了四组保证网络平衡点是渐近稳定平衡点的充分条件，应用这些条件，便可设计联想记忆神经网络，文中给出了应用这些结论设计联想记忆神经网络的实验结果及分析。     

A multibit test trigger circuit for megabit SRAMs

A multibit test (MBT) trigger circuit for megabit SRAM packages with no unused pins is discussed. The features of the MBT trigger circuit are a logic trigger mode without using any additional pins and practical use of counter circuits. The essence of trigger mode selection is that two pulses are for MBT set and three pulses are for MBT reset. In this way, a logic trigger mode that does not use NC pins is especially effective as a 4-Mb SRAM. In addition, the proposed scheme is able to act as a logic trigger for an MBT circuit. The scheme is simple and effective. The logic trigger mode is proposed for future standardization     

Digital Design of Discrete Exponential Bidirectional Associative Memory

The exponential bidirectional associative memory (eBAM) was proved to be a systematically stable high-capacity memory. Considering the difficulty of the implementation of such an eBAM by analog circuits and the compactability with binary logic circuits, we adopt the digital logic methodology to design such a neural network. Besides, we also count in other factors, e.g., scalability and speed, so that the complete digital design of this neural network is feasible. In order to realize the eBAM by digital circuitry only, some special design is required such that the exponential function can be implemented without the loss of operating speed. For example, a high-speed 8-to-9 exponent value generator is required in the design. In addition, because the traditional add/sub accumulator costs too much area when the dimension of patterns is large, a cascaded increment/decrement accumulator (IDA) is proposed in the design, which can also speed up the addition or subtraction besides the saving of chip area. For the sake of area saving, regenerated IDA is also proposed to reduce the cost of chip area. At last, thorough simulations by MAGIC and IRSIM are proceeded to verify the performance of the design.     

多重加权改进型指数双向联想记忆网络及其决策性能

C C Wang等作者利用指数双向联想记忆模型(eBAM),构造了由多个eBAM构成的多重eBAM(Multi-eBAM)信念组合模型,使之可模拟多个专家的投票表决决策,并获得了Multi-eBAM在各eBAM具有同等权威度条件下的决策性能.本文在此基础上,通过对各eBAM引入不同的权值来模拟各专家不同的权威度,推广了Multi-eBAM.进一步借助陈所提出的改进型eBAM(IeBAM),构建了相应的多重加权改进型eBAM(Multi-WIeBAM)信念组合模型,获得了此推理模型在同、异步方式下的决策性能及多专家不同权威度下的多数投票因子,使之更符合实际的多数表决决策.理论分析表明Multi-WIeBAM所获得的多数投票因子优于Multi-WeBAM的多数投票因子,即前者较后者具有更紧致的下界.实验结果也表明了Multi-WIeBAM的性能要优于Multi-WeBAM.     

网络参数对混沌联想记忆特性的影响

由于混沌具有随机性、对初始值敏感等特点,网络参数的调整会对其动力学行为产生很大的影响,本文提出了改进的混沌联想记忆神经网络模型,详细探讨了网络参数对混沌神经网络联想记忆特性的影响,分析了这些影响的范围和规律,并且用计算机仿真实验证明了本文的结论.