250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture

A 3.3-V 512-k×18-b×2-bank synchronous DRAM (SDRAM) has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250-Mbyte/s synchronous DRAM with die size of 113.7-mm², which is the same die size as the conventional DRAM, has been achieved with 0.50-μm CMOS process technology     

基于FPGA的SDRAM控制器设计与实现

针对SDRAM(Synchronous Dynamic Random Access Memory)在缓存图像数据时时序的控制比较复杂的问题,在研究SDRAM的特点和原理的基础上,提出了一种基于现场可编程逻辑器件FPGA(Field Programmable Gate Array)为核心的SDRAM控制器的设计方案。采用分模块的思想,把SDRAM的控制分成不同的功能模块,各模块之间通过信号状态线相互关联,并且相关模块利用状态机来控制整个时序的过程。另外,为了提高SDRAM的缓存速度,选择了SDRAM工作在页突发操作模式下,使SDRAM的读写速度有了大幅的提升。整个控制系统经过仿真和在线逻辑分析仪验证表明:控制器能准确地对SDRAM进行读写控制,稳定可靠,可应用于不同的高速缓存系统。     

A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control

An 8 M /spl times/ 32 GDDR (graphic DDR) SDRAM operating up to 800-MHz clock (CLK) frequency is described. The GDDR SDRAM demands an effective control of CAS latency due to the large and wide number of CAS latencies at the CLK frequency. A wave-pipelined CAS latency control circuit is proposed to provide stable operation for the large and wide number of CAS latencies. The increase of CAS latency also causes a degradation of data bus efficiency at high-speed operation due to the large gap between input data (DINs) and output data (DOUTs) at the operation of write followed by read. A gapless write to read scheme improves the data bus efficiency by separating write data-path from read data-path for different banks accesses. Partial array activation commands can reduce the peak current, preventing the reduction of the data retention time of DRAM cells at high-speed operation. The GDDR SDRAM operates successfully at the CLK frequency of 800 MHz at 2.1 V and 700 MHz at 1.8 V, respectively. The power consumption is measured to be /spl sim/2 W at 1.9 V.     

A 146-mm/sup 2/ 8-gb multi-level NAND flash memory with 70-nm CMOS technology

An 8-Gb multi-level NAND Flash memory with 4-level programmed cells has been developed successfully. The cost-effective small chip has been fabricated in 70-nm CMOS technology. To decrease the chip size, a one-sided pad arrangement with compacted core architecture and a block address expansion scheme without block redundancy replacement have been introduced. With these methods, the chip size has been reduced to 146 mm/sup 2/, which is 4.9% smaller than the conventional chip. In terms of performance, the program throughput reaches 6 MB/s at 4-KB page operation, which is significantly faster than previously reported and very competitive with binary Flash memories. This high performance has been achieved by the combination of the multi-level cell (MLC) programming with write caches and with the program voltage compensation technique for neighboring select transistors. The read throughput reaches 60 MB/s using 16I/O configuration.     

An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme

This paper proposes a deca-data rate clocking scheme and relevant I/O circuit techniques for a multi-Gb/s/pin memory interface. A deca-data rate scheme transmits 10 bits in one external clock cycle to transfer an error control code along with original data seamlessly without a timing bubble. A 288 Mb SDRAM has been designed using the proposed scheme combined with fast cycling core techniques to have both high I/O bandwidth and fast random cycling. Measured results show that the chip exhibits per-pin data rate of 8 Gb/s and row cycle time of 9.6 ns     

A 12-ns ECL I/O 256 K×1-bit SRAM using a 1-μm BiCMOStechnology

An ECL (emitter-coupled-logic) I/O 256K×1-bit SRAM (static random-access memory) has been developed using a 1-μm BiCMOS technology. The double-level-poly, double-level-metal process produces 0.8-μm CMOS effective gate lengths and polysilicon emitter bipolar transistors. A zero-DC-power ECL-to-CMOS translation scheme has been implemented to interface the ECL periphery circuits to the CMOS decode and NMOS matrix. Low-impedance bit-line loads were used to minimize read access time. Minimization of bit-line recovery time after a write cycle is achieved through the use of a bipolar/CMOS write recovery method. Full-die simulations were performed using HSPICE on a CRAY-1     

基于EPM1240的SDRAM控制器的设计

SDRAM的读写逻辑复杂,最高时钟频率达100 MHz以上,普通单片机无法实现复杂的SDRAM控制操作。复杂可编程逻辑器件CPLD具有编程方便,集成度高,速度快,价格低等优点。因此选用CPLD设计SDRAM接口控制模块,简化主机对SDRAM的读写控制。通过设计基于CPLD的SDRAM控制器接口,可以在STM系列、ARM系列、STC系列等单片机和DSP等微处理器的外部连接SDRAM,增加系统的存储空间。     

一种基于超大容量Cache的VOD系统

视频服务器是VOD系统的核心所在。衡量一个视频服务器性能最重要的指标是它所能支持的最大并发的媒体流的数量,而硬盘的I/O的带宽已经成为进一步提高性能的瓶颈。提出了一种新的基于SDRAM的Cache方案有效地解决了这个问题。     

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer

This paper describes three circuit techniques for a DDR1/DDR2-compatible chip architecture designed for both high-speed and high-density DRAMs: 1) a dual-clock input-latch scheme, which reduces the excessive timing margin for random input commands by using a pair of latch circuits controlled by dual-phase one-shot clock signals, achieves a 0.9-ns reduction in cycle time from 3.05 to 2.15 ns; 2) a hybrid multi-oxide output buffer reduces the area penalty of the output buffer caused by compatible chip design from 1.35% to 0.3%; and 3) a quasi-shielded distributed data transfer scheme enables a 2.6-ns reduction in access time to 10.25 ns in both 2-b and 4-b prefetch operations. By using these techniques, we developed a 175.3-mm/sup 2/ 1-Gb SDRAM that operates as an 800-Mb/s/pin DDR2 or 400-Mb/s/pin DDR1.     

A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOSregister file

A two-write-port, six-read-port, 32×64-bit register file has been designed for 2.5-V 0.5-μm CMOS technology, using primary self-resetting CMOS (SRCMOS) circuit techniques. The register cell are completely level-sensitive scan design test compatible. The fabricated register file occupies an area of 1.84×1.55 mm², and the cell size is 21.6×30 μm². The high-performance register file is implemented in a multiblock structure consisting of subarrays and associated multiplexing circuits. For a given read port, the outputs of all multiplexer circuits are dotted together to form a single global output. A quasi-global approach is used for reset pulse generation and timing control circuits to reduce area overhead. The output pulse width is controlled by a chopper circuit. The write-port operation is achieved by the combination of static data input and dynamic control circuits. The write-path circuits employ the advantages of the input isolation technique. Individual write-enable pulses applied to respective input ports of a multiport register-file cell are effective to establish a priority among those input ports. The present design provides an effective input isolation/decoupling circuit technique that allows the input pulse widths to vary over a wide range. This allows the write operation to be insensitive to control pulse widths, resulting in an effective input isolation scheme. Testing has shown all eight ports to be functional. The measured read access time was 1.1 ns, and read operation has been obtained at cycle times as short as 1.9 ns. The register file has been shown to be tolerant to a very wide range of input pulse widths yet delivers tightly controlled outputs     

90% write power-saving SRAM using sense-amplifying memory cell

This paper describes a low-power write scheme which reduces SRAM power by 90% by using seven-transistor sense-amplifying memory cells. By reducing the bitline swing to V/sub DD//6 and amplifying the voltage swing by a sense-amplifier structure in a memory cell, the charging and discharging component of the power of the bit/data lines is reduced. A 64-kb test chip has been fabricated and correct read/write operation has been verified. It is also shown that the scheme can also have the capability of leakage power reduction with small modifications. Achievable leakage power reduction is estimated to be two orders of magnitude from SPICE simulation results.     

SDRAM控制器简易化设计

SDRAM存储芯片拥有快速读写的性能,可以应用以回波模拟系统作为数据高速缓存器。SDRAM芯片是由SDRAM控制器控制的,SDRAM控制器有严格的控制时序和工作状态,可以使用有限状态机理论和VerilogHDL语言对FPGA进行模块化开发设计。笔者基于FPGA给出了一种SDRAM控制器简易化设计方法,实验结果表明该方法简化了SDRAM控制器的设计。     

FPGA中嵌入式块存储器的IP软核设计

以集成电路的快速发展与广泛应用为契机,针对FPGA开发过程中IP软核可复用的特点,提出一种提升FPGA嵌入式块存储器工作频率的IP软核设计方法。利用软件对不同读写类型和不同输入位宽的数据进行预处理,获取所需的硬件资源开销,并生成相应的硬件描述语言。IP软核设计时,在使用固定硬件资源的情况下,通过优化数据预处理方法,以及改变在综合阶段布局布线的处理结果,提高了工作频率。对设计的IP软核进行测试验证,结果表明,该设计方法生成的IP软核的功能和性能指标均符合设计要求,其工作频率最高可提升25.56%。     

A 220-mm2, four- and eight-bank, 256-Mb SDRAM withsingle-sided stitched WL architecture

A 220-mm², 256-Mb SDRAM has been fabricated in fully planarized 0.22-μm CMOS technology with buried strap trench cell. The single-sided stitched word-line (WL) architecture employs asymmetric block activation and shared row decoders to realize 86.7% cell/chip-length efficiency (57.3% cell/chip efficiency). A staggered WL driver arrangement makes it possible to build the drivers on a 0.484-μm WL pitch in limited space. An intraunit address increment pipeline scheme having two logical 8-Mb arrays within one physical 16-Mb unit results in a burst frequency up to 200 MHz for single data rate, while allowing four- and eight-bank organizations. A data rate of 270 Mbits/s was confirmed with a 135-MHz frequency doubling test mode. Single-ended addresses and a single ended read-write-drive bus reduce the ICC₄ current to ~90 mA for 100-MHz seamless burst operation. A detailed shmoo analysis demonstrates address-access time of 13.5 ns and clock-access time of 5 ns. This design also uses a selectable row domain and divided column redundancy scheme that repairs up to ~1400 faults/chip with only 8% chip overhead     

3D显示器视频转换系统设计及其FPGA实现

针对SXGA(1280×1024)格式高速视频信号的传输特性,结合FPGA技术设计了适用于43cm(17in)自由立体液晶显示器的3D视频信号转换系统。以FPGA芯片作为显示控制器,采用乒乓操作的设计思想协调两组SDRAM完成不同3D模式下对视频信号的实时读写控制,从而实现多制式的立体显示。该设计方案具有不降低显示刷新率、电路结构简单、设计灵活性高的特点,只要通过适当修改代码即可应用于更大尺寸的立体显示器。对系统硬件组成及工作原理进行了分析,并着重介绍了基于乒乓操作的SDRAM控制器的设计与实现。     

An innovative two-stage data compression scheme using adaptive block merging technique

Test data has increased enormously owing to the rising on-chip complexity of integrated circuits. It further increases the test data transportation time and tester memory. The non-correlated test bits increase the issue of the test power. This paper presents a two-stage block merging based test data minimization scheme which reduces the test bits, test time and test power. A test data is partitioned into blocks of fixed sizes which are compressed using two-stage encoding technique. In stage one, successive blocks are merged to retain a representative block. In stage two, the retained pattern block is further encoding based on the existence of ten different subcases between the sub-block formed by splitting the retained pattern block into two halves. Non-compatible blocks are also split into two sub-blocks and tried for encoded using lesser bits. Decompression architecture to retrieve the original test data is presented. Simulation results obtained corresponding to different ISCAS′89 benchmarks circuits reflect its effectiveness in achieving better compression.     

A 256-Mb DRAM with 100 MHz serial I/O ports for storage of movingpictures

A 256-Mb DRAM with refresh-free-FIFO function for storage of moving pictures has been developed using 0.25-μm CMOS technology. An operating current of 73 mA (reduction of 52% compared with a conventional circuit) has been achieved at 100 MHz based on introducing (1) a suppressed High(H)-level differential data transfer scheme which ran be operated at 0.6 V, (2) a new pre-charge method which features a 1/2 VCC precharge level in read cycle and VSS pre-charge level in write cycle, and (3) a divided operation of array circuits for serial access     

A 390-mm2, 16-bank, 1-Gb DDR SDRAM with hybrid bitlinearchitecture

A 390-mm², 16-bank, 1-Gb, double-data-rate (DDR) synchronous dynamic random access memory (SDRAM) has been fabricated in fully planarized 0.175-μm, 8F² trench cell technology. The 1-Gb SDRAM employs a hybrid bitline architecture with 512 cells/local-bitline (LBL). Four LBL pairs are connected through multiplexers to each sense amplifier (SA). Two of the LBL pairs are coupled to the SA by wiring over two other LBL pairs using hierarchical bitlines. This results in a reduction of the number of the SA's to 1/4, reducing the chip size by 6%. A hierarchical column-select-line scheme is incorporated with a hierarchical dataline (MDQ) architecture. This makes 16-bank organization possible while sharing hierarchical column decoders and second sense amplifiers. A hierarchical 8-b prefetch scheme employs four MDQ's for each read-write drive (RWD) and two RWD's for each DQ. This reduces the frequencies of the MDQ's and the RWD's to 1/8 and 1/2, respectively. A 1-V swing signaling on the RWD is used to reduce the burst current by 18 mA. The 1-V swing signaling is successfully converted to 2.1 V with self-timed first-in, first-out circuitry. The hardware data demonstrate 400-Mb/s/pin operation with a 16-mm TSOP-II package. Seamless burst operation at various frequencies has also been confirmed. These features result in a 1.6-Gb/s data rate for ×32 200-MHz DDR operation with a cell/chip area efficiency of 67.5%     

基于SDRAM基本结构、操作及相关时序参数的研究

本文从SDRAM的基本结构入手，研究了SDRAM的读写等操作的详细过程和相关时序参数的取值依据。     

A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/sbandwidth

This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V _cc=2.0 V and 25°C. The chip employs (1) a merged multibank architecture to minimize die area; (2) an extended small swing read operation and a single I/O line driving write scheme to reduce power consumption; (3) a self-strobing I/O schemes to achieve high bandwidth with low power dissipation; and (4) a block redundancy scheme with increased flexibility. The nonstitched chip with an area of 652 mm ² has been fabricated using 0.16 μm four-poly, four-metal CMOS process technology