用Delphi实现基于小波变换的JPEG2000压缩

对Delphi实现基于小波变换的JPEG2000压缩进行了研究.从Delphi的一般应用方法入手,给出了实现基于小波变换的JPEG2000压缩方法,对小波变换的理论进行了详细的阐述,对实现过程中的技巧给予了详细的论述.     

用于图象压缩的小波变换电路研究

小波变换已经被新一代图象压缩国际标准JPEG2000所采用.如何有效地实现小波变换电路是影响其推广应用的关键技术之一.本文提出一种通用型基于提升滤波和分时处理的流水线式电路结构,它可以用较少的运怂算电路实现小波变换.其中,在图象块的边界处理上,设计了一种简捷的延时、选通结构.对于JPEG2000无损压缩选用的(5,3)小波变换,本文在FPGA电路平台上进行了实验,实现了无损变换.     

5/3小波提升方法的FPGA仿真

离散小波变换是当今许多图像处理和压缩技术的基础，并被最新的ISO／IEC静态图像压缩标准JPEG2000所采用。5／3小波提升方法在JPEG2000中主要用于无损图像压缩，该文为该算法提出一种硬件结构，并在FPGA上仿真实现。     

提升小波变换的FPGA设计与实现

根据1996年Sweldens等人提出的提升小波变换方法,设计了一种有效的JPEG2000 CDF(2,2)整数小波变换的VL-SI实现结构,并对小波系数的变化范围进行了分析.用VHDL对该结构进行基于FPGA实现的可综合描述,并用EDA软件进行了仿真和综合,硬件仿真结果和软件Matlab实现结果完全一致.     

提升小波变换的FPGA设计与实现

根据1996年Sweldens等人提出的提升小波变换方法,设计了一种有效的JPEG2000CDF(2,2)整数小波变换的VL-SI实现结构,并对小波系数的变化范围进行了分析。用VHDL对该结构进行基于FPGA实现的可综合描述,并用EDA软件进行了仿真和综合,硬件仿真结果和软件Matlab实现结果完全一致。     

应用提升格式实现的基于行小波变换的图像压缩算法

内存需求量大、计算复杂度高等问题很大程度上限制了JPEG2000的应用。基于行小波变换的图像压缩算法以累进方式完成列向小波变换,在不影响变换结果的前提下降低了对存储容量的需求。应用三项加法单元形式的提升格式代替原基于行的小波变换算法中的Mallat算法,充分利用了提升格式的全替换特性,加快了计算速度,节省了内存。同时针对基于行的小波变换的特点,设计了相应的上下文模板,可以简洁、高效地进行概率估计。应用该方法对JPEG2000进行改进,可大大提高其实用性。     

基于JPEG2000的雷达卡技术研究

介绍了一种应用目前最新静态图像压缩算法JPEG2000实现的雷达卡的方法,首先说明了雷达卡的硬件实现平台;接着重点说明JPEG2000压缩算法,在JPEG2000编码器里详细说明了DC层进和分量变换、离散小波变换、内嵌编码与最佳截断这三大要点,并给出了相应的程序流程图;再说明了JPEG2000算法从PC到DSP的移植与优化;最后给出了雷达图像采集压缩系统的性能测试。     

有效的JPEG2000小波变换VLSI结构设计

基于提升的小波变换算法,提出了一种有效的JPEG2000小波变换的VLSI实现结构。采用了时分复用技术优化结构设计,实现了数据变换的细节分量和近似分量交替输出,以及有效减少了所用乘法器、加法器运算单元和寄存器单元数量,从而有效减少系统占用面积和功耗。该结构实现简单、规则,具有很好的扩展性,非常适合于VLSI设计实现。     

JPEG2000在低比特率图像压缩的研究

介绍了JPEG2000的主要特点和基本架构,以及JPEG2000编码器的两个重要部分:小波变换和熵编码.简明分析了小波变换DWT与离散余弦变换DCT的区别和小渡变换的优点.详细介绍了JPEG2000的核心编码算法EBCOT.着重介绍了JPEG2000在图像低比特率情况下的应用,并进行了实际应用的实验:在图像压缩比很高时,JPEG2000与JPEG的压缩效果对比图.     

JPEG2000压缩算法研究

由于JPEG2000采用零树编码方式实现压缩,编码过程中零树的形成个数与压缩效率CE密切相关;对小波滤波器及JPEG2000零树熵编码进行研究,发现高的小波变换层数和5／3滤波器的使用有利于增加零树个数,从而提高压缩率;实现基于拼接块小波变换的JPEG2000压缩算法,结果显示图像分成拼接块会影响编码效率和解码保真度;对JPEG和JPEG2000进行比较,得出在超低码率下,JPEG2000解码图像虽然没有采用JPEG时出现的“方块”效应,但有“飞萤”效应。     

一种用于JPEG2000的小波变换VLSI结构设计方法

为了快速地进行小波变换,提出了一种应用于JPEG2000的基于提升格式5/3,9/7统一的离散小波滤波单元;同时对于行列并行滤波,提出了一种控制机制,其在缓存5行的条件下,可完成高速行列并行滤波操作。该方法在保证精度条件下,可以取得较高的硬件利用率,且中间数据暂存空间需求低。然后在提升结构基础上,完成了硬件模块设计,并进行了仿真和FPGA实现。最后用Verilog HDL对系统进行了硬件描述,并在Altera DE2的验证板上的cyclone2 EP2C35FC672芯片上,在Quartus 6.0环境下实现了该结构功能。     

Efficient parallel architecture for multi-level forward discrete wavelet transform processors

A resource efficient and high-performance architecture for a two-dimensional multi-level discrete wavelet transform processor is presented in this paper. The JPEG2000 standard integer lossless 5-3 filter has been implemented. It achieves optimal hardware utilisation with minimal combinational logic block slices and high frequency of operation. To reduce the hardware complexity and to achieve high performance the proposed architecture implements lifting scheme with a single multiplier-free processing element to perform both predict and update operations. Symmetric extension is used at image boundaries without requiring any extra clock cycle. The generic architecture is very flexible and can perform up to five levels of forward transform on any arbitrary image size. Synthesis of the 5-level architecture on Xilinx Virtex 5 FPGA shows that the processor can achieve a maximum frequency of operation of 221.44 MHz. The reduced hardware complexity and high frequency of operation render the design suitable for incorporation in image processing applications requiring fast operations. The 5-level design has been successfully implemented on a Xilinx Spartan 3E FPGA, utilising only 1104 slices for a 512-by-512 pixel test image, the lowest hardware requirements for a 5-level discrete wavelet transform processor reported to date.     

二维提升小波变换的FPGA结构设计

根据提升小波的框架结构，提出了一种基于JEPG2000的二维多级提升小波变换核的FPGA设计。 采用分时复用和流水结构，充分利用FPGA片内存储资源，实现了行列变换的并行执行。在保证精度的前提下采用优化的移位加操作代替浮点乘运算，加快了运算速率，减小了电路规模。同时通过乒乓操作完成FPGA和片外SDRAM间数据的无缝缓冲处理，保证了多级变换的高效实时并行，从而达到各级小波系数的快速并行输出。系统经验证完全满足图像实时处理的要求，为后续实时压缩编码和传输提供了有利条件。     

Energy efficient novel architectures for the lifting-based discrete wavelet transform

Energy efficient single-processor and fully pipelined architectures for the lifting-based JPEG2000's 5/3 two-dimensional (2D)-discrete wavelet transform are presented. The single processor performs both the row-and column-wise processing simultaneously, that is, full 2D transform with 100% hardware utilisation. In addition, the architecture uses minimum embedded memory. The fully pipelined architecture is obtained by replicating the single-processor block depending on the levels of decomposition with much lower memory requirement and higher throughput than the single processor involved in multi-level transforms. These architectures can be directly used in real-time image/video consumer applications to extend the battery life of portable systems.     

The instruction systolic array and its relation to other models of parallel computers

In this paper we investigate the relationships between three different models of parallel computers based on mesh-connected arrays: the processor array (PA), which is an MIMD-array of independent processors, the instruction broadcasting array (IBA), where the instructions are broadcast to all the processors of a column and executed according to selector information which is broadcast to all the processors of a row, and the instruction systolic array (ISA), where the instructions are pumped through the array row by row and combined with selector information which is pumped through the array column by column. For every two of these models we determine tight bounds on the worst-case delay introduced by a transformation of a program on one model into an equivalent program on the other. The results show that the ISA concept combines the advantages of standard systolic arrays with those of the MIMD concept. Since in addition the ISA architecture has smaller area requirements than a corresponding systolic array or MIMD machine it is strong practical relevance.     

A Novel VLSI Architecture for Real-Time Line-Based Wavelet Transform Using Lifting Scheme

In this paper, we propose a VLSI architecture that performs the line-based discrete wavelet transform （DWT） using a lifting scheme. The architecture consists of row processors, column processors, an intermediate buffer and a control module. Row processor and Column processor work as the horizontal and vertical filters respectively. Intermediate buffer is composed of five FIFOs to store temporary results of horizontal filter. Control module schedules the output order to external memory. Compared with existing ones, the presented architecture parallelizes all levels of wavelet transform to compute multilevel DWT within one image transmission time, and uses no external but one intermediate buffer to store several line results of horizontal filtering, which decreases resource required significantly and reduces memory efficiently. This architecture is suitable for various real-time image/video applications.     

并行DSP处理器上JPEG算法的实现研究

ＪＰＥＧ算法由于效率高和实用性强获得了广泛的应用;而并行处理器ＤＳＰ具有高效的并行处理能力,因而适合于图象的实时处理。提出了在ＴＩ的并行处理器ＤＳＰ－Ｃ８０上并行和快速实现ＪＰＥＧ算法的方法,实现了高速实时图象压缩。     

JPEG2000编码算法中上下文关系的改进

通过研究SPIHT和EBCOT（JPEG2000核心算法）编码算法,分析它们所用的小波系数的不同性质,本文提出了把SPIHT算法用到的小波系数父子关系特性也用在EBCOT编码中的思想,并提出一种上下文关系的改进方法。在JPEG2000框架下对改进算法进行了仿真实验。理论分析和实验结果显示,改进的上下文关系优于JPEG2000中采用的上下文关系。     

An efficient hardware implementation of parallel EBCOT algorithm for JPEG 2000

With the augmentation in multimedia technology, demand for high-speed real-time image compression systems has also increased. JPEG 2000 still image compression standard is developed to accommodate such application requirements. Embedded block coding with optimal truncation (EBCOT) is an essential and computationally very demanding part of the compression process of JPEG 2000 image compression standard. Various applications, such as satellite imagery, medical imaging, digital cinema, and others, require high speed and performance EBCOT architecture. In JPEG 2000 standard, the context formation block of EBCOT tier-1 contains high complexity computation and also becomes the bottleneck in this system. In this paper, we propose a fast and efficient VLSI hardware architecture design of context formation for EBCOT tier-1. A high-speed parallel bit-plane coding (BPC) hardware architecture for the EBCOT module in JPEG 2000 is proposed and implemented. Experimental results show that our design outperforms well-known techniques with respect to the processing time. It can reach 70 % reduction when compared to bit plane sequential processing.