Design of a low-power 3.5-GHz broad-band CMOS transimpedance amplifier for optical transceivers

This paper describes a novel low-power low-noise CMOS voltage-current feedback transimpedance amplifier design using a low-cost Agilent 0.5-/spl mu/m 3M1P CMOS process technology. Theoretical foundations for this transimpedance amplifier by way of gain, bandwidth and noise analysis are developed. The bandwidth of the amplifier was extended using the inductive peaking technique, and, simulation results indicated a -3-dB bandwidth of 3.5 GHz with a transimpedance gain of /spl ap/60 dBohms. The dynamic range of the amplifier was wide enough to enable an output peak-to-peak voltage swing of around 400 mV for a test input current swing of 100 /spl mu/A. The output noise voltage spectral density was 12 nV//spl radic/Hz (with a peak of /spl ap/25 nV//spl radic/Hz), while the input-referred noise current spectral density was below 20 pA//spl radic/Hz within the amplifier frequency band. The amplifier consumes only around 5 mA from a 3.3-V power supply. A test chip implementing the transimpedance amplifier was also fabricated using the low-cost CMOS process.     

Analysis of the equal-delay topology for transformers and hybrid networks

A complete scattering matrix representation for the ideal equal-delay topology for transformers and hybrid networks is presented. It is shown that while the operation of the hybrid as a 180/spl deg/ power combiner, current balun, or voltage balun is essentially frequency independent, the operation as a 0/spl deg/ power combiner or splitter is not. Instead, the isolation between the 0/spl deg/ and 180/spl deg/ ports is finite and frequency dependent. Moreover, the reflection coefficient at the sum port is nonzero and frequency dependent. These characteristics lead to the conclusion that while the equal-delay 180/spl deg/ power splitter/combiner is fundamentally frequency independent, its 0/spl deg/ counterpart is limited to operation well below the fundamental quarter-wave frequency of the constituent transmission lines. Full three-port scattering parameter representations, which are compatible with the calibration and analysis approach given in the CISPR 16-1 specification, are given for the three fundamental transformer and balun types derivable from the equal-delay hybrid: 1 the Guanella voltage balun, 2 the Guanella current balun, and 3 the 180/spl deg/ power divider or terminated hybrid balun, as specified in the CISPR 16-1 specification.     

A Wide-Band Quadrature Hybrid Coupler (Correspondence)

Wide-band quadrature hybrid proximity couplers consist of a conductor fabricated by thin-film techniques in microstrip the conductor side and a slot in the ground plane side. A 4 to 1 bandwidth was achieved using an alumina substrate of 99.6-percent purity with a surface finish of 10 /spl mu/in. A single-section quadrature hybrid has been fabricated and operates over a 2.5- to 10-GHz frequency range with a maximum VSWR of 1.43:1, a 20-dB typical isolation, and a phase difference between outputs of 90/spl deg/ /spl plus mn/ 3/spl deg/.     

Low-voltage high performance compact all cascode CMOS current mirror

A high performance and compact current mirror with extremely low input and high output resistances (R/sub in//spl sim/0.01/spl Omega/, R/sub out//spl sim/10 G/spl Omega/), high copying accuracy, very low input and output voltage requirements (V/sub in/, V/sub out//spl ges/V/sub DSsat/), high bandwidth (200 MHz using a 0.5 /spl mu/m CMOS technology) and low settling time (25 ns) is proposed. Simulations and experimental results are shown that validate the circuit.     

Low-voltage CMOS current-mode preamplifier: analysis and design

This paper presents the analysis and design of a new low-voltage fully balanced differential CMOS current-mode preamplifier for multi-Gbps series data communications. The minimum supply voltage of the proposed preamplifier is V/sub T/+V/sub sat/. The preamplifier employs a balanced configuration to achieve large bandwidth and to minimize the effect of bias-dependent mismatches. Two new bandwidth enhancement techniques, namely inductive series peaking and current feedback that are specific to low-voltage CMOS current-mode circuits, are introduced. The inductive series peaking technique utilizes the resonant characteristics of LC networks to achieve both a flat frequency response and maximum bandwidth. Current feedback extends bandwidth, lowers input impedance, and improves dynamic range. The employment of both techniques further increases the bandwidth, reduces the value of the series peaking inductor, and improves noise performance of the pre-amplifier at high frequencies. The preamplifier has been designed using a 0.18-/spl mu/m 6-metal 1-poly 1.8-V CMOS technology. Simulation results from Spectre with BSIM3.3 device models that account for device parasitics demonstrate that the preamplifier has a flat frequency response with 25.3 dB dc current gain or equivalently 60 dB/spl Omega/ transimpedance gain with a 50-/spl Omega/ load and bandwidth of 2.15 GHz.     

An integrated bandgap reference

Using well-known principles a configuration has been developed for an IC reference voltage source with good performance with respect to the temperature dependency and 1/f noise. A bread-board model of this configuration has been tested. In the temperature range of 0-70/spl deg/C, the output voltage variations were less than /spl plusmn/70 ppm at an output voltage of about 2.5 V and zero load current. Low-frequency noise in a bandwidth 0.003 Hz相似文献   

A compact 43-GHz monolithic differential VCO in 0.5-/spl mu/m InP DHBT technology

A compact monolithic integrated differential voltage controlled oscillator (VCO) using 0.5-/spl mu/m emitter width InP/InGaAs double-heterostructure bipolar transistors with a total chip size of 0.42 mm /spl times/ 0.46 mm is realized by using cross-coupled configuration for extremely high frequency satellite communications system applications. The device performance of F/sub max/ greater than 320 GHz at a current density of 5 mA//spl mu/m/sup 2/ and 5-V BVceo allows us to achieve a low phase noise 42.5-GHz fundamental VCO with -0.67-dBm output power. The VCO exhibits the phase noise of -106.8 dBc/Hz at 1-MHz offset and -122.3 dBc/Hz at 10-MHz offset from the carrier frequency.     

A 16-bit low-voltage CMOS A/D converter

A/D converters used in telemetry, instrumentation, and measurements require high accuracy, excellent linearity, and negligible DC offset, but need not be fast. A simple and robust instrumentation A/D converter, fabricated in a low-voltage 4-/spl mu/m CMOS technology, is described. The measured overall accuracy was 16 bits. Using a digital compensation for parasitic effects, both offset and nonlinearity were below 12 /spl mu/V. With analog compensation, the offset was 60 /spl mu/V and the nonlinearity below 15 /spl mu/V. These results indicate that even higher accuracy can be achieved using higher voltage technology.     

Performance enhancement of offset gated polysilicon thin-film transistors

Simple offset gated n-channel polysilicon thin film transistors (TFTs) of channel length L=10 /spl mu/m were investigated in relation to the intrinsic offset length /spl Delta/L and the polysilicon quality. For /spl Delta/L/spl les/1 /spl mu/m, the device parameters such as threshold voltage, subthreshold slope and field effect mobility are improved, while the leakage current remains unchanged. In TFTs with /spl Delta/L>1 /spl mu/m, the leakage current decreases with increasing the offset length. When the polysilicon layer is of high quality (large grain size and low intra-grain defect density), the leakage current is completely suppressed without sacrificing the on-current in TFT's with offset length of 2 /spl mu/m.     

Micro-power low-offset instrumentation amplifier IC design for biomedical system applications

This work presents a micro-power low-offset CMOS instrumentation amplifier integrated circuit with a large operating range for biomedical system applications. The equivalent input offset voltage is improved using a new circuit technique of offset cancellation that involves a two-phase clocking scheme with a frequency of 20 kHz. Channel charge injection is cancelled by the symmetrical circuit topology. With the wide-swing cascode bias circuit design, this amplifier realizes a very high power-supply rejection ratio (PSRR), and can be operated at single supply voltage in the range between 2.5-7.5 V. It was fabricated using 0.5-/spl mu/m double-poly double-metal n-well CMOS technology, and occupies a die area of 0.2 mm/sup 2/. This amplifier achieves a 160-/spl mu/V typical input offset voltage, 0.05% gain linearity, greater than 102-dB PSRR, an input-referred rms noise voltage of 45 /spl mu/V, and a current consumption of 61 /spl mu/A at a low supply voltage of 2.5 V. Experimental results indicate that the proposed amplifier can process the input electrocardiogram signal of a patient monitoring system and other portable biomedical devices.     

Design and analysis of separate-absorption-transport-charge-multiplication traveling-wave avalanche photodetectors

This paper proposes a novel type of avalanche photodiode-the separate-absorption-transport-charge-multiplication (SATCM) avalanche photodiode (APD). The novel design of photoabsorption and multiplication layers of APDs can avoid the photoabsorption layer breakdown and hole-transport problems, exhibit low operation voltage, and achieve ultra-high-gain bandwidth product performances. To achieve low excess noise and ultra-high-speed performance in the fiber communication regime (1.3/spl sim/1.55 /spl mu/m), the simulated APD is Si-based with an SiGe-Si superlattice (SL) as the photoabsorption layer and traveling-wave geometric structures. The frequency response is simulated by means of a photo-distributed current model, which includes all the bandwidth-limiting factors, such as the dispersion of microwave propagation loss, velocity mismatch, boundary reflection, and multiplication/transport of photogenerated carriers. By properly choosing the thicknesses of the transport and multiplication layers, microwave propagation effects in the traveling-wave structure can be minimized without increasing the operation voltage significantly. A near 30-Gb/s electrical bandwidth and 10/spl times/ avalanche gain can be achieved simultaneously, even with a long device absorption length (150 /spl mu/m) and low operation voltage (/spl sim/12 V). In addition, the ultrahigh output saturation power bandwidth product of this simulated TWAPD structure can also be expected due to the large photoabsorption volume and superior microwave-guiding structure.     

A 12 /spl times/ 12 In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As avalanche photodiode array

We report a 12 /spl times/ 12 In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As avalanche photodiode (APD) array. The mean breakdown voltage of the APD was 57.9 V and the standard deviation was less than 0.1 V. The mean dark current was /spl sim/2 and /spl sim/300 nA, and the standard deviation was /spl sim/0.19 and /spl sim/60 nA at unity gain (V/sub bias/ = 13.5 V) and at 90% of the breakdown voltage, respectively. External quantum efficiency was above 40% in the wavelength range from 1.0 to 1.6 /spl mu/m. It was /spl sim/57% and /spl sim/45% at 1.3 and 1.55 /spl mu/m, respectively. A bandwidth of 13 GHz was achieved at low gain.     

CMOS voltage references using lateral bipolar transistors

Two bandgap references are presented which make use of CMOS compatible lateral bipolar transistors. The circuits are designed to be insensitive to the low beta and alpha current gains of these devices. Their accuracy is not degraded by any amplifier offset. The first reference has an intrinsic low output impedance. Experimental results yield an output voltage which is constant within 2 mV, over the commercial temperature range (0 to 70/spl deg/C), when all the circuits of the same batch are trimmed at a single temperature. The load regulation is 3.5 /spl mu/V//spl mu/A, and the power supply rejection ratio (PSRR) at 100 Hz is 60 dB. Measurements on a second reference yield a PSRR of minimum 77 dB at 100 Hz. Temperature behaviour is identical to the first circuit presented. This circuit requires a supply voltage of only 1.7 V.     

A Latching Ring-And-Post Ferrite Waveguide Circulator

This paper presents the performance and normalized design parameters for a latching ring-and-post ferrite circulator in waveguide. A C-band circulator has provided an insertion loss of 0.35 dB and a 20-dB isolation bandwidth of 17 percent. When the circulator was matched for higher maximum isolation (50 dB) but narrower bandwidth (10 percent) at room temperature, the 20-dB isolation bandwidth was 7.8 percent across the -40/spl deg/ to +75/spl deg/C temperature range. Low-loss operation was obtained at pulsed powers up to 7.5 kilowatts, and at least 20 dB of isolation was maintained up to 100 kilowatts. This performance, in conjunction with a switching speed of a fraction of a microsecond, permits the use of these circulators for transmitting-receiving functions in high-reliability RADARs.     

An NMOS comparator for a bubble memory

A low-noise low-offset comparator was designed for a bubble memory system. The measured noise performance was 25 /spl mu/V rms or 13 nV//spl radic/Hz and the worst case offset voltage was determined to be 158 /spl mu/V. This results in a 1.30 mV comparator gray region.     

A 32-GHz non-uniform distributed amplifier in 0.18-/spl mu/m CMOS

This letter presents a fully integrated distributed amplifier in a standard 0.18-/spl mu/m CMOS technology. By employing a nonuniform architecture for the synthetic transmission lines, the proposed distributed amplifier exhibits enhanced performance in terms of gain and bandwidth. Drawing a dc current of 45mA from a 2.2-V supply voltage, the fabricated circuit exhibits 9.5-dB pass-band gain with a bandwidth of 32GHz while maintaining good input and output return losses over the entire frequency band. With a compact layout technique, the chip size of the distributed amplifier including the testing pads is 940/spl times/860/spl mu/m/sup 2/.     

Low-voltage high-drive CMOS current feedback op-amp

A novel CMOS current feedback op-amp is presented. The solution works using a low supply voltage and provides a wide input/output swing as well as a high current driving capability. Experimental results from a prototype implemented in a 0.35-/spl mu/m technology and powered with 1.5 V are also given. The circuit exhibits a better than 500 kHz closed-loop bandwidth and a /spl plusmn/1 mA current drive capability.     

A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability

This brief describes an adaptive bandwidth bus architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode (CM) signaling. An experimental adaptive bandwidth bus test chip fabricated in AMI 1.6-/spl mu/m Bulk CMOS indicates a reduction in power dissipation of approximately 62% over CM sensing and an increase in maximum data rate of 40% over voltage-mode signaling.     

Current gain high-frequency CMOS operational amplifiers

The performance of high unity gain-bandwidth current gain-based CMOS operational amplifiers fabricated in a 1.5-/spl mu/m CMOS digital process is discussed. High unity-gain bandwidth was achieved by using short-channel MOS transistors operating in the current gain mode. Stacked current mirrors have been utilized as current gain stages to minimize the effects of the channel-length modulation in short-channel MOS transistors. Open-circuit gain of 60 to 70 dB, a unity-gain bandwidth of 70 to 100 MHz, and slew-rate of 200 V//spl mu/s were demonstrated at a DC power dissipation of 1-2 mW.     

A novel InP/InGaAs TEBT for ultralow current operations

A novel InP/InGaAs tunneling emitter bipolar transistor (TEBT) is fabricated and demonstrated. The studied device exhibits a very small collector-emitter offset voltage of 40 mV and an extremely wide operation regime. The operation region is larger than 11 decades in magnitude of collector current (10/sup -12/ to 10/sup -1/A). A current gain of 3 is obtained even if the device is operated at an ultralow collector current of 3.9 /spl times/ 10/sup -12/A (1.56 /spl times/ 10/sup -7/A/cm/sup 2/). Furthermore, the common-emitter breakdown voltage of the studied device is higher than 2 V. Consequently, the studied device shows a promise for low supply voltage, and low-power consumption circuit applications.