3D graphics processor chip set

Increasingly, 3D graphics is becoming the rule rather than the exception in applications such as games, CAD/CAM, and video production. Some LSIs provide rendering capabilities, but require an additional CPU to perform essential geometry transformations. Fujitsu's chip set solves that problem using two processors to render 300,000 polygons per second (for flat-shaded triangles with texture)-performance comparable to that of advanced game machines     

A pixel pipeline architecture with selective z-test scheme for 3D graphics processors

We propose pixel pipeline architecture with a selective z-test scheme that focuses on reducing the data processed in the pixel pipeline by employing preprocessing. Reduction of data can reduce the data transmission between the 3D graphics processor and the memory and also reduce the power consumption of memory access, which is a critical point in the case of mobile devices. In 3D graphics processor, most of the memory transmissions are occurred in rasterization stage, especially in pixel pipelines. To reduce memory transmission, the proposed architecture exploits the coherency among pixel fragments to predict the visibility of each pixel fragment. Through this, the proposed architecture eliminates invisible fragments before texture mapping using a single z-test, which would require two z-tests in the mid-texturing architecture. According to the simulations, the proposed architecture reduces data transmission by 19.9–22.6% as compared to the mid-texturing architecture at the expense of a 5% reduction in performance. Further, the proposed architecture also reduces the cell area of the depth cache by 26.4% and the area of overall architecture by 6% as compared to that in the mid-texturing architecture.     

An instruction-systolic programmable shader architecture for multi-threaded 3D graphics processing

In order to guarantee both performance and programmability demands in 3D graphics applications, vector and multithreaded SIMD architectures have been employed in recent graphics processing units. This paper introduces a novel instruction-systolic array architecture, which transfers an instruction stream in a pipelined fashion to efficiently share the expensive functional resources of a graphics processor. Specifically, cache misses and dynamic branches can cause additional latencies and complicated management in these parallel architectures. To address this problem, we combine a systolic execution scheme with on-demand warp activation that handles cache miss latency and branch divergence efficiently without significantly increasing hardware resources, either in terms of logic or register space. Simulation indicates that the proposed architecture offers 25% better performance than a traditional SIMD architecture with the same resources, and requires significantly fewer resources to match the performance of a typical modern vector multi-threaded GPU architecture.     

A scalable high-performance graphics processor: GVIP

The GVIP (geometric and TV image processor) graphics processor, which creates and synthesizes computer graphics and TV images and meets the requirements of multi-media systems, is described. The hardware modules that make up this graphics processor include: a 32-bit embedded RISC processor, a Phong and Gouraud shading processor, a texture mapping processor, a hidden surface removal processor, an HDTV video image processor, a BitBlt processor, an imageprocessing module, and an outline font fill generator. These hardware modules fabricated using 0.8 m CMOS standard cells have been placed in three integrated circuit chips. The total number of gates used for one set of chips is approximately 350000.     

A general purpose,expandable processor for real-time computer graphics

A class of critical computer requirements for real-time scan T.V. computer graphics is examined in relation to commercially available CPU architectures. Finding general purpose processors not suited, a new processor is proposed which is designed around the concept of ‘instruction set partitioning.’ In this design, special hardware-implemented algorithms may be included in the machine instruction set, and these processors allowed to operate asynchronously from each other. The design is projected to generate a complete new frame of a color T.V. picture every 0.1-0.8 s depending on image complexity. Due to its inherent generality, the CPU may be similarly expanded to encompass a wide variety of other specialized, or real-time tasks with minimal additional hardware. The 32-bit parallel processor has a design cycle time of 100 ns and is in the price class of a minicomputer.     

The 3DP: a processor architecture for three-dimensionalapplications

The 3DP (3-Dimensional Processor), a parallel-computing architecture that targets problems that have a 3-D numerical structure and require numerous calculations on 3-D vectors, is described. The 3DP architecture differs from traditional scalar architectures in that it operates directly on vectors. It differs from general parallel architectures in that it can solve problems that predict the behavior of highly coupled systems, and it differs from vector architectures in that it runs efficiently on length-3 vectors. Object-oriented programming on the 3DP and programming the 3DP in C++ are discussed. 3DP performance is reviewed, and the current implementation of the 3DP architecture, as an attached processor that plugs directly into Sun host VMEbus, is described     

GRASP—A 3D graphics system for Pascal users

This paper describes a 3D graphics package ‘GRASP’ implemented in Pascal language and interfaced with the Pascal compiler developed for the DEC PDP-10 machine, by Urs Amman et al. GRASP supports storage tube and raster scan graphics terminals and pen plotters. The package is incorporated as a set of standard procedures into the enhanced Pascal compiler. The various features of the package are presented here and a comparison is made vis-a-vis the other existing 3D graphics packages. GRASP is simple to use and provides a valuable tool for the development of application programs written in Pascal and requiring a graphics capability.     

A moving threads processor architecture MTPA

Moving threads is a new kind of approach for multicore processor architectures. Traditionally, each thread stays in the core where it is created, and data is moved from the main memory via caches to each core and thread. In the moving threads approach, each core can access only a certain portion of the main memory via its local memory block, and thus extremely lightweight threads are moved between the cores. As a consequence, all kinds of cache coherence problems and need for read reply messages are eliminated. Also Lamport’s sequential consistency of shared memory multiprocessor systems is achieved for free. In this paper, we propose a processor architecture (MTPA) for the moving threads paradigm. We describe the overall structure, operation, instruction set, and thread management mechanism as well as evaluate the proposed architecture with different functional unit settings with simulations and give early silicon area and power consumption estimates.     

A continuation-based noninterruptible multithreading processor architecture

Current trend of research on multithreading processors is toward the chip multithreading (CMT), which exploits thread level parallelism (TLP) and improves performance of softwares built on traditional threading components, e.g., Pthread. There exist commercially available processors that support simultaneous multithreading (SMT) on multicore processors. But they are basically based on the conventional sequential execution model, and execute multiple threads in parallel under the control of OS that handles interruptions. Moreover, there exist few languages or programming techniques to utilize the multicore processors effectively. We are taking another approach to develop a multithreading processor, which is dedicated to TLP. Our processor, named Fuce, is based on the continuation-based multithreading. A thread is defined as a block of sequentially ordered instructions which are executed without interruption. Every thread execution is triggered only by the event called continuation. This paper first introduces the continuation-based multithread execution model and its processor architecture then gives multithreaded programming techniques and the continuation-based multithreading language system CML. Last, the performance of the Fuce processor is evaluated by means of the clock-level software simulation.     

Perceptually optimized 3D graphics

The author uses models of visual perception to remove nonperceptible components of a 3D computer graphics scene and optimize the system's performance. He considers how much detail can be removed from the scene without the user noticing, and how much added benefit these optimizations actually bring     

A model for integrating multimedia information around 3D graphics hierarchies

We present a model for organizing multimedia information especially suitable for applications with three-dimensional content. The model relies on the hierarchical nature of 3D objects, which are utilized as centralizing structure to give coherence to the organization and access of all other medium types. Techniques have been developed to facilitate the manipulation of all medium types through a consistent user interace paradigm. The modeling of space and time constraints as applied to the animation of graphical objects and their synchronization with video has also been explored. Two industrial training applications have been developed to demonstrate the usability of the system.     

A pipeline virtual environment architecture for multicore processor systems

We present a novel architecture to develop Virtual Environments (VEs) for multicore CPU systems. An object-centric method provides a uniform representation of VEs. The representation enables VEs to be processed in parallel using a multistage, dual-frame pipeline. Dynamic work distribution and load balancing is accomplished using a thread migration strategy with minimal overhead. This paper describes our approach, and shows it is efficient and scalable with performance experiments. Near linear speed-ups have been observed in experiments involving up to 1,000 deformable objects on a six-core i7 CPU. This approach’s practicality is demonstrated with the development of a medical simulation trainer for a craniotomy procedure.     

Evaluating graphics displays for complex 3D models

This article summarizes a user study of viewing 3D geometry on large-screen display devices. The geometry models the structure of a complex physical object. Our results show that the crispness of a display device (intraframe performance) must be considered along with the speed at which new frames can be computed (interframe performance). It's important to consider crispness from the user's perspective, using values that aren't often published in device specifications. Equally important is the framework for different types of 3D data and the categorization of display technology and techniques     

A JPEG-like texture compression with adaptive quantization for 3D graphics application

Published online: 2 October 2001     

The Panda3D graphics engine

Disney's VR Studio developed Panda3D, a graphics engine and programming environment, to be flexible enough to support everything from real-time graphics applications to the development of high-end virtual reality theme park attractions or video games. The acronym itself lists Panda's primary features as platform-agnostic, networked, display architecture. As a result of its powerful and flexible design, much of the Panda system's architecture reflects the occasionally opposing goals of performance and versatility.     

Index rendering: hardware-efficient architecture for 3-D graphics in multimedia system

Real-time three-dimensional (3D) graphics is emerging rapidly in multimedia applications, but it suffers from requirements for huge computation, high bandwidth, and large buffer. In order to achieve hardware efficiency for 3D graphics rendering, we propose a novel approach named index rendering. The basic concept of index rendering is to realize a 3D rendering pipeline by using asynchronous multi-dataflows. Triangle information can be divided into several parts with each part capable of being transferred independently and asynchronously. Finally, all data are converged by the index to generate the final image. The index rendering approach can eliminate unnecessary operations in the traditional 3D graphics pipeline, the unnecessary operations are caused by the invisible pixels and triangles in the 3D scene. Previous work, deferred shading, eliminates the operations relating to invisible pixels, but it requires huge tradeoffs in bandwidth and buffer size. With index rendering, we can eliminate operations on both invisible pixels and triangles with fewer tradeoffs as compared with the deferred shading approach. The simulation and analysis results show that the index rendering approach can reduce 10%-70% of lighting operations when using the flat and Gouraud shading process and decrease 30%-95% when using Phong shading. Furthermore, it saves 70% of buffer size and 50%-70% of bandwidth compared with the deferred shading approach. The result also indicates that this approach of index rendering is especially suitable for low-cost portable rendering devices. Hence, index rendering is a hardware-efficient architecture for 3D graphics, and it makes rendering hardware more easily integrated into multimedia systems, especially system-on-a-chip (SOC) designs.     

Low-cost hardware platform for developing realtime 3D graphics

BRAD3D, a low-cost hardware platform for the development of a realtime 3D graphics software is presented. The BRAD3D configuration is derived from a generalization of 3D image synthesis. Three basic processes have been identified: the geometric process, dealing with the measurements of the scene; the topologic process, extracting visible information from the polygonal structure; and the scan-conversion process, producing pixel values on a frame buffer. BRAD3D is implemented as a three-stage pipeline and accommodates depth-list and scan-line hidden-surface-removal algorithms. Each stage of the pipeline can be implemented using different hardware solutions. A microprocessor-based solution is presented as a general prototyping approach.