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1.
This letter reports the development of a high-performance power 4H-SiC bipolar junction transistor (BJT) with, simultaneously, a high blocking voltage and a low specific on-resistance (R/spl I.bar//sub ON/). A single BJT cell with an active area of 0.61 mm/sup 2/ achieves an open base collector-to-emitter blocking voltage (V/sub ceo/) of 1677 V and conducts up to 3.2 A at a forward voltage drop of V/sub CE/=3.0 V, corresponding to a low R/spl I.bar//sub ON/ of 5.7 m/spl Omega//spl middot/cm/sup 2/ up to Jc=525 A/cm/sup 2/ and a record high value of V/sub B//sup 2//R/sub SP/spl I.bar/ON/ of 493 MW/cm/sup 2/. 相似文献
2.
This letter reports a newly achieved best result on the specific ON-resistance (R/sub SP/spl I.bar/ON/) of power 4H-SiC bipolar junction transistors (BJTs). A 4H-SiC BJT based on a 12-/spl mu/m drift layer shows a record-low specific-ON resistance of only 2.9 m/spl Omega//spl middot/cm/sup 2/, with an open-base collector-to-emitter blocking voltage (V/sub ceo/) of 757 V, and a current gain of 18.8. The active area of this 4H-SiC BJT is 0.61 mm/sup 2/, and it has a fully interdigitated design. This high-performance 4H-SiC BJT conducts up to 5.24 A at a forward voltage drop of V/sub CE/=2.5 V, corresponding to a low R/sub SP-ON/ of 2.9 m/spl Omega//spl middot/cm/sup 2/ up to J/sub c/=859 A/cm/sup 2/. This is the lowest specific ON-resistance ever reported for high-power 4H-SiC BJTs. 相似文献
3.
Design and fabrication of 4H-SiC(0001) lateral MOSFETs with a two-zone reduced surface field structure have been investigated. The dose dependencies of experimental breakdown voltage show good agreement with simulation. Through the optimization of implant dose, high-temperature (1700/spl deg/C) annealing after ion implantation, and reduction of channel length, a breakdown voltage of 1330 V and a low on-resistance of 67 m/spl Omega//spl middot/cm/sup 2/ have been obtained. The figure-of-merit (V/sub B//sup 2//R/sub on/) of the present device reaches 26 MW/cm/sup 2/, being the best performance among lateral MOSFETs reported. The temperature dependence of static characteristics is also presented. 相似文献
4.
《Electron Devices, IEEE Transactions on》2006,53(7):1657-1668
The authors demonstrate high-performing n-channel transistors with a HfO/sub 2//TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 /spl Aring/, a leakage current of 1.5 A/cm/sup 2/ at V/sub G/=1 V, a peak mobility of 190 cm/sup 2//V/spl middot/s, and a drive-current of 815 /spl mu/A//spl mu/m at an off-state current of 0.1 /spl mu/A//spl mu/m for V/sub DD/=1.2 V. Identical gate stacks processed with a 1000-/spl deg/C spike anneal have a higher peak mobility at 275 cm/sup 2//V/spl middot/s, but a 5-/spl Aring/ higher EOT and a reduced drive current at 610 /spl mu/A//spl mu/m. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 /spl deg/C) for a ten-year lifetime, whereas positive-bias temperature-instability measurements indicate a sufficient lifetime for operating voltages below 0.75 V. 相似文献
5.
Nakamura T. Miyanagi T. Kamata I. Jikimoto T. Tsuchida H. 《Electron Device Letters, IEEE》2005,26(2):99-101
In this letter, we report the fabrication of high-voltage and low-loss 4H-SiC Schottky-barrier diodes (SBDs) with a performance close to the theoretical limit using a Mo contact annealed at high-temperature. High-temperature annealing for the Mo contact was found to be effective in controlling the Schottky-barrier height at 1.2-1.3 eV without degradation of n-factor and reverse characteristics. We successfully obtained a 1-mm/sup 2/ Mo-4H-SiC SBD with a breakdown voltage (V/sub b/) of 4.15 kV and a specific on resistance (R/sub on/) of 9.07 m/spl Omega//spl middot/cm/sup 2/, achieving a best V/sub b//sup 2//R/sub on/ value of 1898 MW/cm/sup 2/. We also obtained a 9-mm/sup 2/ Mo-4H-SiC SBD with V/sub b/ of 4.40 kV and R/sub on/ of 12.20 m/spl Omega//spl middot/cm/sup 2/. 相似文献
6.
Sei-Hyung Ryu Krishnaswami S. O'Loughlin M. Richmond J. Agarwal A. Palmour J. Hefner A.R. 《Electron Device Letters, IEEE》2004,25(8):556-558
10-kV, 123-m/spl Omega//spl middot/cm/sup 2/ power DMOSFETs in 4H-SiC are demonstrated. A 42% reduction in R/sub on,sp/, compared to a previously reported value, was achieved by using an 8 /spl times/ 10/sup 14/ cm/sup -3/ doped, 85-/spl mu/m-thick drift epilayer. An effective channel mobility of 22 cm/sup 2//Vs was measured from a test MOSFET. A specific on-resistance of 123 m/spl Omega//spl middot/cm/sup 2/ were measured with a gate bias of 18 V, which corresponds to an E/sub ox/ of 3 MV/cm. A leakage current of 197 /spl mu/A was measured at a drain bias of 10 kV from a 4H-SiC DMOSFET with an active area of 4.24 /spl times/ 10/sup -3/ cm/sup 2/. A switching time of 100 ns was measured in 4.6-kV, 1.3-A switching measurements. This shows that the 4H-SiC power DMOSFETS are ideal for high-voltage, high-speed switching applications. 相似文献
7.
The design, fabrication and characterisation of a high performance 4H-SiC diode of 1789 V-6.6 A with a low differential specific-on resistance (R/sub SP/spl I.bar/ON/) of 6.68 m/spl Omega/ /spl middot/ cm/sup 2/, based on a 10.3 /spl mu/m 4H-SiC blocking layer doped to 6.6/spl times/10/sup 15/ cm/sup -3/, is reported. The corresponding figure-of-merit of V/sub B//sup 2//R/sub SP/spl I.bar/ON/ for this diode is 479 MW/cm/sup 2/, which substantially surpasses previous records for all other MPS diodes. 相似文献
8.
We describe the on-state performance of trench oxide-protected SiC UMOSFETs on 115-/spl mu/m-thick n-type 4H-SiC epilayers designed for blocking voltages up to 14 kV. An on-state current density of 137 A/cm/sup 2/ and specific on-resistance of 228 m/spl Omega//spl middot/cm/sup 2/ are achieved at a gate bias of 40 V (oxide field of 2.67 MV/cm). The effect of current spreading on the specific on-resistance for finite-dimension devices is investigated, and appropriate corrections are made. 相似文献
9.
Lateral reduced surface field (RESURF) metal-oxide-semiconductor field-effect transistors (MOSFETs) have been fabricated on 4H-SiC(0001/sup ~/) carbon face (C-face) substrates. The channel mobility of a lateral test MOSFET on a C-face was 41 cm/sup 2//V/spl middot/s, which was much higher than 5 cm/sup 2//V/spl middot/s for that on a Si-face. The specific on-resistance of the lateral RESURF MOSFET on a C-face was 79/spl Omega/ /spl middot/ cm/sup 2/, at a gate voltage of 25 V and drain voltage of 1 V. The breakdown voltage was 460 V, which was 79% of the designed breakdown voltage of 600 V. We measured the temperature dependence of R/sub on, sp/ for the RESURF MOSFET on the C-face. The R/sub on, sp/ increased with the increase in temperature. 相似文献
10.
Harada S. Okamoto M. Yatsuo T. Adachi K. Fukuda K. Arai K. 《Electron Device Letters, IEEE》2004,25(5):292-294
The most important issue in realizing a 4H-SiC vertical MOSFET is to improve the poor channel mobility at the MOS interface, which is related to high on-resistance. This letter focuses on a novel 4H-SiC vertical MOSFET device structure where a low acceptor concentration epitaxial layer is used as a channel. We call this structure a double-epitaxial MOSFET (DEMOSFET). In the structure, the p-well is composed of two p-type epitaxial layers, while an n-type region between the p-wells is formed by low-dose n-type ion implantation. A buried channel is formed at the surface of the upper p/sup $/epitaxial layer. A fabricated DEMOSFET showed an on-resistance of 8.5 m/spl Omega//spl middot/cm/sup 2/ at a gate voltage of 15 V and a blocking voltage of 600 V. This on-resistance is the lowest so far reported for a vertical MOSFET with a blocking voltage of 600 V. 相似文献
11.
This letter reports the demonstration of a 4H-SiC trenched and implanted vertical-junction field-effect transistor (TI-VJFET). The p/sup +/n junction gates are created on the sidewalls of deep trenches by angled Al implantation, which eliminates the need for epitaxial regrowth during the JFET fabrication. Blocking voltages up to 1710 V has been achieved with a voltage supporting drift layer of only 9.5 /spl mu/m by using a two-step junction termination extension. The TI-VJFET shows a low specific on-resistance R/sub ON-sp/ of 2.77m/spl Omega/cm/sup 2/, corresponding to a record high value of V/sub B//R/sub ON-sp/ equal to 1056 MW/cm/sup 2/. 相似文献
12.
A new plate biasing scheme is described which allowed the use of 65% higher supply voltage without increasing the leakage current for the UV-O/sub 3/ and O/sub 2/ annealed chemical-vapor-deposited tantalum pentaoxide dielectric film capacitors in stacked DRAM cells. Dielectric leakage was reduced by biasing the capacitor plate electrode to a voltage lower than the conventionally used value of V/sub cc//2. Ta/sub 2/O/sub 5/ films with 3.9 nm effective gate oxide, 8.5 fF//spl mu/m/sup 2/ capacitance and <0.3 /spl mu/A/cm/sup 2/ leakage at 100/spl deg/C and 3.3 V supply are demonstrated.<> 相似文献
13.
Sun Jung Kim Byung Jin Cho Ming-Fu Li Shi-Jin Ding Chunxiang Zhu Ming Bin Yu Narayanan B. Chin A. Dim-Lee Kwong 《Electron Device Letters, IEEE》2004,25(8):538-540
It is demonstrated that the voltage coefficients of capacitance (VCC) in high-/spl kappa/ metal-insulator-metal (MIM) capacitors can be actively engineered and voltage linearity can be significantly improved maintaining high capacitance density, by using a stacked insulator structure of high-/spl kappa/ and SiO/sub 2/ dielectrics. A MIM capacitor with capacitance density of 6 fF/spl mu/m/sup 2/ and quadratic VCC of only 14 ppm/V/sup 2/ has been demonstrated together with excellent frequency and temperature dependence (temperature coefficients of capacitance of 54 ppm /spl deg/C) as well as low leakage current of less than 10 nA/cm/sup 2/ up to 4 V at 125 /spl deg/C. 相似文献
14.
Griffith Z. Rodwell M.J.W. Xiao-Ming Fang Loubychev D. Ying Wu Fastenau J.M. Liu A.W.K. 《Electron Device Letters, IEEE》2005,26(8):530-532
InP/In/sub 0.53/Ga/sub 0.47/As/InP double heterojunction bipolar transistors (DHBT) have been designed for increased bandwidth digital and analog circuits, and fabricated using a conventional mesa structure. These devices exhibit a maximum 450 GHz f/sub /spl tau// and 490 GHz f/sub max/, which is the highest simultaneous f/sub /spl tau// and f/sub max/ for any HBT. The devices have been scaled vertically for reduced electron collector transit time and aggressively scaled laterally to minimize the base-collector capacitance associated with thinner collectors. The dc current gain /spl beta/ is /spl ap/ 40 and V/sub BR,CEO/=3.9 V. The devices operate up to 25 mW//spl mu/m/sup 2/ dissipation (failing at J/sub e/=10 mA//spl mu/m/sup 2/, V/sub ce/=2.5 V, /spl Delta/T/sub failure/=301 K) and there is no evidence of current blocking up to J/sub e//spl ges/12 mA//spl mu/m/sup 2/ at V/sub ce/=2.0 V from the base-collector grade. The devices reported here employ a 30-nm highly doped InGaAs base, and a 120-nm collector containing an InGaAs/InAlAs superlattice grade at the base-collector junction. 相似文献
15.
We have demonstrated the advantages of silicon interlayer passivation on germanium MOS devices, with CVD HfO/sub 2/ as the high-/spl kappa/ dielectric and PVD TaN as the gate electrode. A silicon interlayer between a germanium substrate and a high-/spl kappa/ dielectric, deposited using SiH/sub 4/ gas at 580/spl deg/C, significantly improved the electrical characteristics of germanium devices in terms of low D/sub it/ (7/spl times/10/sup 10//cm/sup 2/-eV), less C- V hysteresis and frequency dispersion. Low leakage current density of 5/spl times/10/sup -7/ A/cm/sup 2/ at 1 V bias with EOT of 12.4 /spl Aring/ was achieved. Post-metallization annealing caused continuing V/sub fb/ positive shift and J/sub g/ increase with increased annealing temperature, which was possibly attributed to Ge diffusion into the dielectric during annealing. 相似文献
16.
Liao E.B. Guo L.H. Kumar R. Lo G.Q. Balasubramanian N. Kwong D.L. 《Electron Device Letters, IEEE》2005,26(12):885-887
For the first time, transferring the prefabricated capacitors on a silicon wafer onto FR-4 has been used to realize high-density metal-insulator-metal (MIM) capacitors on an organic substrate. A high capacitance density /spl sim/85 nF/cm/sup 2/ was achieved on FR-4 substrate with PECVD silicon nitride as the dielectric layer. Excellent voltage coefficient (/spl sim/2.2 ppm/V/sup 2/) and temperature coefficient (/spl sim/38 ppm//spl deg/C) were obtained for capacitors on FR-4. Dielectric leakage and breakdown characteristics have been assessed, and the results demonstrated acceptable performance. Thus, this technology provides a new method to embed/integrate high-density capacitors on organic substrates for the system-in-package applications. 相似文献
17.
A CMOS voltage reference, which is based on the weighted difference of the gate-source voltages of an NMOST and a PMOST operating in saturation region, is presented. The voltage reference is designed for CMOS low-dropout linear regulators and has been implemented in a standard 0.6-/spl mu/m CMOS technology (V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0/spl deg/C). The occupied chip area is 0.055 mm/sup 2/. The minimum supply voltage is 1.4 V, and the maximum supply current is 9.7 /spl mu/A. A typical mean uncalibrated temperature coefficient of 36.9 ppm//spl deg/C is achieved, and the typical mean line regulation is /spl plusmn/0.083%/V. The power-supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz are -47 and -20 dB, respectively. Moreover, the measured noise density with a 100-nF filtering capacitor at 100 Hz is 152 nV//spl radic/(Hz) and that at 100 kHz is 1.6 nV//spl radic/(Hz). 相似文献
18.
Tone K. Zhao J.H. Fursin L. Alexandrov P. Weiner M. 《Electron Device Letters, IEEE》2003,24(7):463-465
4H-silicon carbide (SiC) normally-off vertical junction field-effect transistor (JFET) is developed in a purely vertical configuration without internal lateral JFET gates. The 2.1-/spl mu/m vertical p/sup +/n junction gates are created on the side walls of deep trenches by tilted aluminum (Al) implantation. Normally-off operation with blocking voltage V/sub bl/ of 1 726 V is demonstrated with an on-state current density of 300 A/cm/sup 2/ at a drain voltage of 3 V. The low specific on-resistance R/sub on-sp/ of 3.6 m/spl Omega/cm/sup 2/ gives the V/sub bl//sup 2//R/sub on-sp/ value of 830 MW/cm/sup 2/, surpassing the past records of both unipolar and bipolar 4H-SiC power switches. 相似文献
19.
Lai C.H. Chin A. Hung B.F. Cheng C.F. Won Jong Yoo Li M.F. Chunxiang Zhu McAlister S.P. Dim-Lee Kwong 《Electron Device Letters, IEEE》2005,26(3):148-150
We demonstrate a programmable-erasable MIS capacitor with a single layer high-/spl kappa/ AlN dielectric on Si having a high capacitance density of /spl sim/5 fF//spl mu/m/sup 2/. It has low program and erase voltages of +4 and -4 V, respectively. Such an erase function is not available in other single layer Al/sub 2/O/sub 3/, AlON, or other known high-/spl kappa/ dielectric capacitors, where the threshold voltage (V/sub th/) shifts continuously with voltage. This device exhibits good data retention with a V/sub th/ change of only 0.06 V after 10 000 s. 相似文献
20.
Xiongfei Yu Chunxiang Zhu Hang Hu Chin A. Li M.F. Byung Jin Cho Dim-Lee Kwong Foo P.D. Ming Bin Yu 《Electron Device Letters, IEEE》2003,24(2):63-65
Metal-insulator-metal (MIM) capacitors with different HfO/sub 2/ thickness have been investigated. The results show that both the capacitance density and voltage coefficients of capacitance (VCCs) increase with decreasing HfO/sub 2/ thickness. In addition, it is found that the VCCs decrease logarithmically with increasing thickness. Furthermore, the MIM capacitor with 10-nm HfO/sub 2/ shows a record high capacitance density of 13 fF//spl mu/m/sup 2/ and a VCC of 607 ppm/V, which can meet the requirement of the International Technology Roadmap for Semiconductors. It can also provide a low leakage current of 5.95 /spl times/ 10/sup -8/A/cm/sup 2/ at room temperature at 1 V, low tangent values below 0.05, and a small frequency dependence. These results indicate that the devices are suitable for use in silicon integrated circuit applications. 相似文献