汽车电子芯片EMC测试标准研究

在汽车电子产品所采用的电磁兼容测试标准的基础上,以功率驱动芯片为例,提出了汽车电子芯片级电磁兼容测试的必要性,并重点介绍了集成电路电磁发射测试标准IEC61967和集成电路电磁抗扰度测试标准IEC62132。     

REGINA test mask: research on EMC guidelines for integrated automotive circuits

This paper presents the results obtained with a specific test mask designed at Motorola for the study of the electromagnetic parasitic emissions in integrated circuits (IC). First, origins of parasitic emissions are presented for CMOS circuits, and electromagnetic compatibility (EMC) measurements of IC emissions are detailed: a radiated measurement method with respect to the IEC61967-2 standard and a conducted one with respect to the IEC61967-4 standard. The REGINA test chip is then described, with a focus on particular structures allowing to test and verify some design guidelines for EMC, like delay cell, emissive structure or on-chip sensor. The printed circuit board that is use to implement the test chip and the experiment test bench are also described. A set of measurements is presented and some guidelines are deduced and recommended as design rules.     

EMC awareness for multi chip modules

As more and more complex functions are realized in modern IC designs, there is also an increasing need to design the IC in order to satisfy the Electromagnetic Compatibility (EMC) requirements. Without a proper design, the high operating frequencies of modern integrated circuits often result in high emissions. Due to the cost pressure on mobile phones and other portable devices, shielding on the PCB is avoided and as a result, the electromagnetic emission of integrated circuits must be reduced. This article provides an overview of design methodologies for achieving EMC of devices implemented in systems in package (SiP) technologies. It exhibits the importance to imply EMC issues in the early design phase to reduce electromagnetic emissions.     

An overview of standards in electromagnetic compatibility for integrated circuits

The characterization of the electromagnetic compatibility (EMC) performance of integrated circuits (ICs) is receiving increasing focus as new applications and technology trends combine to raise the complexity of EMC compliance. The increased focus is driving the need for standardized measurement procedures to enable consistent evaluation and comparison of different devices. This paper discusses the need for standardization, describes the work in process by IEC TC47/SC47A Working Group 9 to standardize emissions and immunity EMC test methods for ICs, and examines trends in IC EMC.     

Characterization of the Evolution of IC Emissions After Accelerated Aging

With the evolving technological development of integrated circuits, ensuring electromagnetic compatibility (EMC) is becoming a serious challenge for electronic circuit and system manufacturers. Although electronic components must pass a set of EMC tests to ensure safe operations, the evolution of EMC over time is not characterized and cannot be accurately forecast. This paper presents an original study about the consequences of the aging of circuits on electromagnetic emissions. Different types of standard applicative and accelerated life tests are applied on a mixed power circuit dedicated to automotive applications. Its conducted emissions are measured before and after these tests, showing variations in EMC performance. Comparisons between each type of aging procedure show that the emission level of the circuit under test is differently affected.      

Micromachined planar spiral inductor in standard GaAs HEMT MMICtechnology

A novel free-standing planar spiral inductor with reduced parasitic capacitances is proposed by suspending individually the strips, through a maskless front-side bulk micromachining compatible with a commercial GaAs HEMT monolithic microwave integrated circuit (MMIC) technology. Suspended structures have been fabricated and characterized at frequencies up to 15 GHz, showing quality factors of up to 16 and self-resonant frequency superior to 16 GHz for a 4.8 nH inductor. Moreover, since the standard IC process as well as the unconcerned electronic circuits are not influenced by micromachining, such devices are directly useful to enhance RF circuits, like matching networks, filters, and low-noise amplifiers     

Performance comparison of substrate coupling effect between silicon and SOI substrates in RF-CMOS technology

Substrate coupling may severely degrade the electrical performances of high-speed and RF integrated circuits. An isolation technique study of parasitic effects due to substrate coupling between two blocks of integrated circuits in an RF CMOS 90 nm technology is presented. Isolation performances are compared for both bulk silicon (Si) and silicon-on-insulator (SOI) substrate. For every substrate, a compact electrical model matching well with measurement results is proposed for test structures composed of 50times50 mum cells surrounded with an appropriate guard ring. An isolation improvement of 10 dB is reached by an additional P-type guard ring placed around one cell and an isolation level of 45 dB is achieved at 1 GHz for bulk Si substrate     

Ferrite Polymer Composite for Improving the Electromagnetic Compatibility of Semiconductor Packaging

The complex permittivity and permeability of ferrite-filled polymer composites were studied at 50 MHz to 1 GHz, and their effects on the electromagnetic compatibility (EMC) of an integrated circuit (IC) package mounted on a printed wiring board (PWB) in the far- and near-field modes were investigated. Incorporating the ferrite particles into the polymer increased the real part of the complex permeability to 10–11 at 50 MHz, and the real part exhibited a frequency dependency over the applied frequency range (50 MHz to 1 GHz). The ferrite particle increased the magnetic loss (μ″ = 3–5) as well, which can absorb the magnetic energy of the incident electromagnetic wave. By coating the test IC package with the ferrite-polymer composite materials, the EMC level of the PWB was dramatically improved. This improvement may be due to the high magnetic loss of the ferrite-polymer composite.     

High Q microwave inductors on silicon by surface tensionself-assembly

A new technique is presented for the fabrication of three-dimensional metal structures by surface tension-induced folding of flat structures. This fully parallel, low temperature method is suitable for post-processing on integrated circuits, and in a first application is used to decouple inductors for radio and microwave-frequency integrated circuits from their substrates, to reduce losses and parasitic capacitance. Meandered microwave inductors have been fabricated on a low resistivity silicon substrate. A peak Q of 10 was measured at 1 GHz, for a 2 nH inductor standing vertically, compared to a peak Q of 4 for the same structure before self assembly     

Identifying electrical mechanisms responsible for functional failures during harsh external ESD and EMC aggression

For particular applications, system level stresses such as EMC stress or ESD (IEC61000-4-2) are directly applied to the integrated circuits with no external protections. Consequently, the integrated circuits have to be designed for reliability in order to stay alive but also to guarantee the normal operations during severe electrical aggressions. Unfortunately, the simulation of functional failures during severe ESD or EMC events remains very challenging for analog products due the frequency domain and to the high current injection mechanisms. This paper describes a test method to identify the design functions and the physical mechanisms that lead to functional failures when integrated circuits are submitted to system level stress.     

A Direct Power Injection Model for Immunity Prediction in Integrated Circuits

This paper introduces a complete simulation model of a direct power injection (DPI) setup, used to measure the immunity of integrated circuits to conducted continuous-wave interference. This model encompasses the whole measurement setup itself as well as the integrated circuit under test and its environment (printed circuit board, power supply). Furthermore, power losses are theoretically computed, and the most significant ones are included in the model. Therefore, the injected power level causing a malfunction of an integrated circuit, according to a given criterion, can be identified and predicted at any frequency up to 1 GHz. In addition to that, the relationship between immunity and impedance is illustrated. Simulation results obtained from the model are compared with measurement results, and these demonstrate the validity of this approach.     

High speed test interface module using MEMS technology

At frequencies above a few gigahertz, testing integrated circuits becomes a challenging task. Test signal integrity degradation due to parasitic effects of interconnects and electromagnetic coupling undermine the test results and increase the yield loss of integrated circuits at high speeds. A new test interface module based on MEMS technology is proposed in this paper. High-speed micro test-channels are designed to establish connectivity between the device under test and the tester at the die level. Experimental results indicate that the proposed architecture can be used to test integrated circuits up to 50 GHz without much loss or distortion.     

Low-noise high electron mobility transistors for monolithic microwave integrated circuits

High electron mobility transistors (HEMT's) for monolithic microwave integrated circuits have been fabricated that have demonstrated excellent performance. External transconductance of 300 mS/mm is observed and noise figures of 1 and 1.8 dB with associated gains of 16.1 and 11.3 dB at 8 and 18 GHz, respectively, have been measured. These are comparable to the best reported noise figures for either HEMT's or MESFET's and are the highest associated gains reported for such low-noise figures. Analysis of these devices indicates that further improvements in these results is possible through optimization of HEMT layers and fabrication technology to reduce gate-source parasitic resistance.     

Status of Lumped Elements in Microwave Integrated Circuits---Present and Future

The use of lumped elements in microwave integrated circuits (MICS) is discussed. The design, fabrication, and performance of networks used in both active and passive circuits are described. Studies on amplifier impedance matching and transforming networks have resulted in the achievement of a 35-dB-gain 6-W-CW 26-percent-efficient amplifier at 2.25 GHz using only lumped elements. Construction of lumped-element low-pass filters and 3-dB quadrature hybrids at S band have produced circuits much smaller than, but with performance comparable to, microstrip distributed circuits. At C band a large-impedance transformer operating as a filter had less than 0.4-dB loss for an impedance transformation close to 20:1. The performance of lumped-element circuits through X band is compared with that of distributed circuits from the standpoint of size, economy, and technological applications. Lumped-element circuits are competitive with distributed circuits through 6 GHz and are practical through 12 GHz.     

High-efficiency monolithic GaAs IMPATT diodes

Impedance-matching circuits were integrated on the same chip as the IMPATT diodes to produce monolithic impatt diodes for millimetre-wave applications. A drastic reduction of device-to-circuit parasitic elements was achieved by placing the external circuitry very close to the device. Oscillators fabricated in this fashion gave the highest efficiencies reported so far in the 30?35 GHz range with 28% conversion efficiency using hybrid-Read structures.     

Full-swing BiCMOS logic circuits with complementaryemitter-follower driver configuration

Various full-swing BiCMOS logic circuits with complementary emitter-follower driver configurations are described. The performance of the circuits is demonstrated in a 1.2 μm complementary BiCMOS technology with a 6 GHz n-p-n and a 2 GHz p-n-p transistor. For the basic circuit, gate delay (fan-in=2, fan-out=1) is 366 ps and driving capability is 288 ps/pF at 4 V. Delay-power tradeoffs that depend on characteristics of the clamping diode between two base nodes of the complementary emitter-follower driver, parasitic capacitances at the two base nodes, and a technique that can be used to achieve full swing have been identified for these circuits. These circuits show leverage over the conventional BiCMOS circuit for reduced power-supply voltages     

Artificial-line-division distributed ICs with 0.1-μm-gate-lengthGaAs MESFET and three-dimensional transmission lines

0.1-μm-gate-length GaAs MESFET distributed baseband integrated circuits (ICs) that utilize an artificial-line-division technique and three-dimensional transmission lines are described. The technique reduces return loss of the distributed circuits at high frequencies, and four-layer transmission-line structure reduces parasitic impedance caused by the IC pattern shape and is suitable for the flip-chip bonding module format. A gate-line-division distributed baseband amplifier IC achieved input return loss of less than -13 dB and gain of 11.7 dB in the 0-56 GHz band. A source-line-division distributed level-shift IC achieved output return loss of less than -9.6 dB at high frequencies and insertion loss of 2.7 dB in the 0-79 GHz band. Both results better the performance of all reported GaAs MESFET distributed ICs     

高温CMOS集成电路闩锁效应分析

本文详细地分析了LDD结构高温CMOS集成电路闩锁效应.文中提出了亚微米和深亚微米CMOS集成电路闩锁效应的模型.在该模型中,针对器件的尺寸和在芯片上分布情况,我们认为CMOS IC闩锁效应的维持电流有两种模式:大尺寸MOST的寄生双极晶体管是长基区,基区输运因子起主要作用;VLSI和ULSI中MOST的寄生双极晶体管是短基区,发射效率起主要作用.但是他们的维持电流都与温度是负指数幂关系.文章给出了这两种模式下的维持电流与温度关系,公式在25℃至300℃之间能与实验结果符合.     

Characterisation of electromagnetic susceptibility of integrated circuits using near-field scan

A susceptibility characterisation test for integrated circuits using a miniature magnetic near-field probe is described. The method is efficient up to a frequency of 6 GHz and maps immunity to radiated fields     

Simulation and experimental study of chaos generation in microwave band using Colpitts circuit

Chaotic Colpitts circuits with fundamental frequency f^＊ beyond 1GHz are studied by both circuit simulation and experiment using Philips＇ broadband transistor with threshold frequency of 25GHz. For the basic configuration of Colpitts circuit with f^＊ of about 1,6GHz, broadband continuous power spectra could be obtained from both circuit simulations and experiments. The harmonics of the observed signal from Agilent PSA/ESA spectrum analyzer are as noticeable as far as 12GHz. A modified Colpitts circuit structure employing the parasitic inductance of BJT （Bipolar Junction Transistor） is also proposed and investigated. By circuit simulation, chaotic attractor and broadband continuous power spectra could be obtained from the modified Colpitts circuit with f^＊ of about 3.5GHz. Because the parasitic effects of the prototype board, the experiment result of the modified Colpitts circuit does not agree well with the simulation result. The gap between the simulation and experimental result could be bridged by replacing the lumped circuit elements with distributed ones.