Identification of gate electrode discontinuities in submicron CMOStechnologies, and effect on circuit performance

An experiment to determine the effect of gate electrode resistivity on circuit speed gave unexpected results: circuits with the lowest sheet resistance had the poorest circuit speed. Explanation of this behaviour required development of a new high-frequency method of measuring the impedance of the gate electrode. This method revealed that the circuits with a composite gate electrode had been formed with a partial discontinuity. The measurement technique is described, and the evidence of the discontinuity is shown. The effect of the discontinuity on device and circuit speed is demonstrated     

Current transport in fluorine implanted GaAs

Effects of fluorine implantation in GaAs have been investigated by electrical characterization. Ion implantation at 100 keV energy was conducted with doses of 10¹¹ and 10¹²/cm². The effect of fluorine implantation on current-voltage (I-V) characteristics of Schottky diodes was significant. Carrier compensation was observed after implantation by the improved I-V characteristics. The lower dose implanted samples showed thermionic emission dominated characteristics in the measurement temperature range of 300 to 100K. The starting wafer and the low dose implanted samples after rapid thermal annealing (RTA) showed similar I-V properties with excess current in the lower temperature range dominated by recombination. The higher dose implanted samples showed increased excess current in the whole temperature range which may result from the severe damage-induced surface recombination. These samples after RTA treatment did not recover from implantation damage as in the low dose implantation case. However, very good I-V characteristics were seen in the higher dose implanted samples after RTA. The influence of the higher dose ion implantation was to produce more thermal stability. The results show the potential application of fluorine implantation in GaAs device fabrication.     

The effect of boron,oxygen, and fluorine in ion implanted GaAs

Effects of boron, fluorine, and oxygen in GaAs have been investigated by electrical characterization using current-voltage, capacitance-voltage and deep level transient spectroscopy techniques. Ion implantation at 100 keV energy was conducted with doses of 10¹¹ and 10¹²/cm². Carrier compensation was observed in each implanted sample. The compensation effect strongly depended on ion implantation condition and ion species. More free carriers were compensated for higher dose and heavier species; however, severe surface damage would also be induced that degrade electrical performance. Rapid thermal annealing treatment showed the heavier ion implanted samples to be more thermally stable. Defect levels for each implanted species were compared and identified. A native shallow defect E4 was easily removed by ion implantation. In higher dose and heavier ion implantation, both electron and hole traps were induced. However, in some cases, heavier ion implantation also removed native defects. Acceptor-type surface states were created by implantation that degrade material electrical characteristics and also reduce the effect of compensation. The damage induced traps were mostly point-defects or point-defect/impurity complexes as evidenced by sensitivity to heat treatment.     

On the number of fast interface states of standard CMOStechnologies

In recent publications about MOS devices, a fast interface state (IS) density has been found for standard thermal oxides, which is much higher than previously expected. This high number of fast interface states was shown to have a strong impact on the effective mobility in state of-the-art MOSFET's with high channel doping concentrations. This calls into question the validity of the standard procedure for mobility data extraction and of all device simulations in which fast interface states are neglected. In contrast to those results our investigations of standard MOS devices fabricated by three different manufactures do not yield such a high interface state density. Our results show that fast interface states can still be neglected for modeling state-of-the-art CMOS technologies and previously extracted mobility data are still valid although fast interface states have been ignored     

Advantages of collocation methods over finite differences in one-dimensional Monte Carlo simulations of submicron devices

Collocation methods are very useful when one-dimensional Monte Carlo simulations of semiconductor submicron devices require a very accurate solution of Poisson's equation. Potential and electric field may be solved simultaneously with better accuracy than using finite differences. The extension to two dimensions is also outlined. We present the results obtained for Monte Carlo simulation of submicron W/Si and AuGaAs Schottky barrier diodes under forward bias conditions. The accurate solution for the electric field at the ohmic contact boundary allows us to model the injected current and to account for depletion of carriers. Tunnelling effects across the barrier are also included in the simulation.     

Direct sampling methodology for statistical analysis of scaled CMOStechnologies

The continued scaling of CMOS technologies introduces new difficulties to statistical circuit analysis and invalidates many of the methodologies developed earlier. The analysis of device parameter distributions reveals multiple sources of parameter correlations, some of which exhibit mutually opposing trends. We found that applying principal component analysis (PCA) to such heterogeneous statistical data may lead to confounding of data and result in underestimation of the total parameter variance. This imposes considerable constraints on the use of several methods of statistical circuit analysis based on PCA. Also the highly nonlinear relationships between the device parameters become more pronounced and cannot be approximated as linear even in the differential range. As a result, the response surface models based on the linear expansion of the performance variable around the nominal point of the device model parameters may lead to significant prediction errors. To address these difficulties, we propose a conceptually simple and accurate approach of direct sampling that treats the extracted SPICE parameter sets and their physical locations as an inseparable set and thus bypasses the dangerous stage of statistical inferences. We illustrate the methodology by applying it to the statistical analysis of a production CMOS process     

Charge-coupled structures with self-aligned submicron gaps

A technique for fabricating charge-coupled devices with submicron gaps is described. The method relies on a "shadowing" effect produced by oblique deposition of the metal in an otherwise standard vacuum evaporation process. The biggest advantage of the technique is its extreme simplicity, particularly for one-dimensional CCD structures. The feasibility of the technique has been demonstrated for two-and three-phase devices; the two-phase structure was a 32-bit shift register which has been operated at up to 10 MHz. With some additional processing, the technique can be used to make bidirectional CCD arrays as required in area imagers and serpentine shift registers.     

Charge-coupled devices with submicron electrode separations

A technique is described for fabricating a 2-phase charge-coupled structure in which the electrodes are separated by only 0.1?0.3 ?m. Stringent photolithographic processing is not required for producing the submicron gaps.     

动态电子束探针检测技术在亚微米和深亚微米IC失效分析中的应用研究

对扫描电子显微镜静态/动态/电容耦合电压衬度像、电子束感生电流像、电阻衬度像在亚微米和深亚微米超大规模集成电路中的成像方法和成像特点进行了研究,对各种分析技术在失效分析中的应用进行了深入的探讨,为电子束探针检测技术在亚微米和深亚微米集成电路故障定位和失效机理分析中的应用提供了理论基础和实践依据.     

Reliability issues in submicron MOSFETs with oxynitride gate dielectrics

A review of critical reliability issues in submicron MOSFETs with oxynitride gate dielectrics is presented. We have focussed our attention on: substrate and gate currents in short channel MOSFETs, hot carrier induced MOSFET degradation under DC and AC stress, gate-induced drain leakage current and its enhancement due to stress, neutral trap generation due to electrical stress and degradation of analog MOSFET parameters. We have also discussed the problems of radiation induced neutral trap generation and boron penetration through the gate dielectric, which arise due to the advanced processing techniques utilized in submicron MOSFET processing. It is concluded that the use of oxynitride gate dielectrics can effectively solve several reliability issues encountered in scaling down MOSFETs to submicron dimensions.     

GaAs microwave devices and circuits with submicron electron-beam defined features

This paper describes the fabrication and application of GaAs FET's, both as discrete microwave devices and as the key active components in monolithic microwave integrated circuits. The performance of these devices and circuits is discussed for frequencies ranging from 3 to 25 GHz. The crucial fabrication step is the formation of the submicron gate by electron-beam lithography.     

Impulse responses of submicron GaAs photodetectors

Metal–semiconductor–metal photodetectors with different submicron spacings (d = 100, 300, 500, 700 and 900 nm) were fabricated on GaAs with a carrier recombination time of 100 ps by electron beam lithography. Temporal responses of the detectors were measured by photoconductive sampling in order to identify factors which limits the response speeds. At a low excitation of <100 μW, the response speeds of 100, 300 and 500 nm spacing detectors are limited by parasitic capacitances of the submicron structures. The speeds of 700 and 900 nm spacing detectors are limited by an electron/hole transport in the semiconductor. At a high excitation of >100 μW, the response speeds of the all spacing detectors are limited by field screening caused by electron–hole plasma.     

Projecting lifetime of deep submicron MOSFETs

A detailed examination of hot-carrier-induced degradation in MOSFETs from a 0.25-μm and a 0.1-μm technology is performed. Although the worst case stress condition depends on the stress voltage, channel length, and oxide thickness, I_b,peak is projected to be the worst case stress condition at the operating voltage for both nMOSFETs and pMOSFETs. Post-metallization anneal (PMA) in deuterium can significantly improve the device lifetime if the primary degradation mechanism at the stress condition is interface trap generation due to interface depassivation by energetic electrons     

使用带有双组闪存的MCU优点

分析了带有双组闪存的MCU优点,并介绍了飞思卡尔双组闪存方案。     

Finite-element simulation of GaAs MESFET's with lateral doping profiles and submicron gates

Results of a two-dimensional finite-element simulation of a GaAs MESFET are presented. The simulation is used to determine the drain current and transconductance as well as the two-dimensional voltage, electron density, and electric-field distributions. It is shown that placement of a compensated doping region in the high electric-field region between gate and drain increases the drain current and transconductance by reducing the velocity-saturation effect. The transconductance and drain conductance of the MESFET in the saturation region of devices having different channel heights are compared with previous analysis.     

High-speed and high-power GaInAsP/InP junction field-effecttransistor with submicron gate

Depletion-mode GaInAsP/InP junction field-effect transistors have been fabricated on Fe-doped semi-insulating InP substrates using liquid-phase epitaxial growth techniques. The authors achieved transconductance of 24 mS (160 mS/mm), drain-source saturation current at an on gate bias of 486 mA/mm and current cutoff frequency of 18.8 GHz using a GaInAsP channel layer owing to the gate length reduction     

Design of wireless on-wafer submicron characterization system

A wireless technique for the testing of very large scale ICs and wafers is presented. This test technique uses standard CMOS to achieve wireless parametric testing. This technique has virtually no area overhead, minimal power requirements, and no process or design changes are required. Most compelling is that wafer contact is not required, thereby enabling the in-line process control/monitoring of the manufacture of VLSI wafers or chips. Simulations of representative VLSI antenna designs are presented along with experimental results from the implementation of the antenna coupling and communications link. Also presented are specific circuit simulations showing the characteristics of operation under a range of conditions. The technique is demonstrated experimentally in discrete form with operation at voltages as low as 1 V with submilliwatt power levels. This technique can be implemented with a requirement of 1/10 000th the area of a Pentium-class VLSI circuit, allowing contactless testing of wafers before packaging     

Modeling the wiring of deep submicron ICs

The semiconductor industry has fuelled the enormous growth of the electronics industry with an unending flow of even better, faster, cheaper chips. These chip improvements, in turn, have been stoked by steady progress in semiconductor process technology, which, as Moore's law predicts, doubles IC transistor counts every 18 months. Supporting this progress is the infrastructure provided by design tools, which today, however, comes up short against the process advances crucial to tomorrow's chips. Why? Because present design tools and methodologies presuppose that chip performance is determined by the transistor. That supposition may have been true a few years ago, but no more. Chip performance now depends on the interconnect. The new significance of interconnect performance is driving changes throughout the logic design flow because logic synthesis engines and other tools assume that timing can be predicted before the physical layout is done. But pre-layout and post-layout timing values no longer converge, and design tools must evolve to match this change in process technology. The first step is for vendors to create tools that accurately predict the performance of designs in this interconnect-dominated technology. The author discusses the importance of timing, 2D and 3D modelling of the interconnects, and deep submicron effects     

Study of RF transistor with submicron T-shaped gate fabricated by nanoimprint lithography

The results devoted to the development of a method for creating an RF transistor, in which a T-shaped gate is formed by nanoimprint lithography, are presented. The characteristics of GaAs p-HEMT transistors have been studied. The developed transistor has a gate “foot” length of the order of 250 nm and a maximum transconductance of more than 350 mS/mm. The maximum frequency of current amplification f _t is 40 GHz at the drain-source voltage V _DS = 1.4 V and the maximum frequency of the power gain f _max is 50 GHz at V _DS = 3 V.