共查询到17条相似文献,搜索用时 125 毫秒
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提出一种基于搜索空间自动缩减的路径覆盖测试数据进化生成方法,首先,确定目标路径与输入变量之间的关系,将可分目标路径分离出与部分分量相关的子路径;然后,固定被穿越子路径对应的输入分量,并缩小交叉和变异操作的范围,使种群在不断缩小的空间里寻找测试数据,以提高测试数据生成的效率;最后,将提出的方法用于基准程序的路径覆盖测试数据生成,并与传统方法和随机法比较.结果表明,本文方法在生成测试数据需要的进化代数、运行时间和成功率等指标上均具有优越性. 相似文献
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为了提高多路径覆盖测试数据的生成效率,研究了一种基于蚁群算法的多路径覆盖测试数据生成方法.首先给出蚁群算法的一种改进方法,该算法以蚂蚁对生成测试数据的重要性作为蚂蚁状态转移和蚂蚁路径变异的依据,以引导更多蚂蚁穿越小概率节点,提高测试数据生成效率.其次,根据改进的蚁群算法分别提出了基于单信息素表和多信息素表的多路径覆盖测试数据生成方法.在基于多信息素表的方法中,每条目标路径的信息素表均被用于其它路径测试数据的求解,而且蚁群算法运行一次即可求解多条目标路径的覆盖测试数据.最后对所提出方法的有效性和复杂度进行了理论分析.实验结果表明,与其它方法相比,基于多信息素表的测试数据生成方法能够有效地生成多路径覆盖测试数据. 相似文献
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为了提高路径覆盖测试数据生成效率,研究了路径自动分割方法并结合人工鱼群算法提出了一种路径覆盖测试数据生成方法.首先在分析变量与节点关系、变量与路径关系的基础上提出了路径分割的自动判定及分离算法,实现了变量对子路径有无影响的自动判定;其次引入Levy飞行策略和共轭梯度法对人工鱼群算法进行了改进;然后结合路径分离的结果和改进的人工鱼群算法实现路径覆盖测试数据的生成.在利用人工鱼生成测试数据的过程中,判断是否有人工鱼穿越分离的子路径.如果有,则记录人工鱼中穿越子路径相应的分量并在人工鱼的觅食、聚群及追尾等行为中固定这些分量,从而使得搜索空间不断减少.最后将提出的方法实现程序的测试数据生成,并与相关方法进行了比较.实验结果表明,本文方法在时间开销、成功率及算法稳定性等方面均具有优越性. 相似文献
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本文提出了一种有效、自动的基本路径集的生成方法,它能在一定程度上提高软件测试的效率.该方法首先设计搜索算法生成基本路径集;再根据基本块之间的依赖性分析来识别不可达路径并将其删除;然后向路径集中添加未覆盖边所在的可达独立路径;最后向路径集中添加未找到可达路径的未覆盖边所在的不可达独立路径,及线性运算所需的不可达独立路径.实验结果表明,该基本路径集生成方法能有效地生成包含尽可能多的可达路径的基本路径集. 相似文献
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文中提出了通过CHAM描述的SA规格说明生成LTS,并根据测试需求进行测试覆盖准则的选取,然后利用全路径测试方法,生成基于此覆盖准则的测试路径.最后以B/ S结构为例,验证了该方法在生成SA级的测试路径上是可行的. 相似文献
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基于回溯与引导的关键代码区域覆盖的二进制程序测试技术研究 总被引:1,自引:0,他引:1
基于路径覆盖的测试方法是软件测试中比较重要的一种测试方法,但程序的路径数量往往呈指数增长,对程序的每一条路径都进行测试覆盖基本上是不可能的。从软件安全测试的观点看,更关心程序中的关键代码区域(调用危险函数的语句、圈复杂度高的函数、循环写内存的代码片断)的执行情况。该文提出了覆盖关键代码区域的测试数据自动生成方法,该方法基于二进制程序,不依赖于源码。通过回溯路径获取所有可达关键代码区域的程序路径,并通过路径引导自动为获得的路径生成相应的测试数据。路径引导策略基于程序的符号执行与实际执行,逐步调整输入,使用约束求解器生成相应的测试用例。理论分析与实验结果显示该文给出的方法可以降低生成测试数据所需要的运行次数,与传统的覆盖路径测试数据生成方法相比,所需要的运行次数显著降低,提高了生成测试数据的效率。 相似文献
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Program analysis is the prime method to program property analysis,which is widely used in the domain of parameter dependent relation,path coverage and test case generation,and a lot of progress has been made.Current program analysis is based on the method of symbolic execution,but symbolic execution is usually tackled with the problems of logic expression generation of path condition and low efficiency of constrain solver,which will affect the results of program analysis.Aiming at enhancing the path analysis efficiency,the path conditions of different paths were collected,the common symbolic expression was extracted and the efficiency of symbolic analysis was enhanced,then the logic expression set was generated,the dependent relation algorithm was used to enhance the efficiency of symbolic analysis.Experimental results demonstrate that the proposed method has the advantages of accurate time complexity and better analysis efficiency compare to traditional program analysis method. 相似文献
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Li Huakang Lv Kehong Qiu Jing Chen Bailiang 《International Journal of Electronics》2018,105(6):1011-1024
The test path of solder joint intermittent connection faults under direct-current stimulus is examined in this paper. According to the physical structure of the circuit, a network model is established first. A network node is utilised to represent the test node. The path edge refers to the number of intermittent connection faults in the path. Then, the selection criteria of the test path based on the node degree index are proposed and the solder joint intermittent connection faults are covered using fewer test paths. Finally, three circuits are selected to verify the method. To test if the intermittent fault is covered by the test paths, the intermittent fault is simulated by a switch. The results show that the proposed method can detect the solder joint intermittent connection fault using fewer test paths. Additionally, the number of detection steps is greatly reduced without compromising fault coverage. 相似文献
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Vemuri R. Kalyanaraman R. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1995,3(2):201-214
A method for generation of design verification tests from behavior-level VHDL programs is presented. The method generates stimuli to execute desired control-flow paths in the given VHDL program. This method is based on path enumeration, constraint generation and constraint solving techniques that have been traditionally used for software testing. Behavioral VHDL programs contain multiple communicating processes, signal assignment statements, and wait statements which are not found in traditional software programming languages. Our model of constraint generation is specifically developed for VHDL programs with such constructs. Control-flow paths for which design verification tests are desired are specified through certain annotations attached to the control statements in the VHDL programs. These annotations are used to enumerate the desired paths. Each enumerated path is translated into a set of mathematical constraints corresponding to the statements in the path. Methods for generating constraint variables corresponding to various types of carriers in VHDL and for mapping various VHDL statements into mathematical relationships among these constraint variables are developed. These methods treat spatial and temporal incarnations of VHDL carriers as unique constraint variables thereby preserving the semantics of the behavioral VHDL programs. Constraints are generated in the constraint programming language CLP(R) and are solved using the CLP(R) system. A solution to the set of constraints so generated yields a design verification test sequence which can be applied for executing the corresponding control path when the design is simulated. If no solution exists, then it implies that the corresponding path can never be executed. Experimental studies pertaining to the quality of path coverage and fault coverage of the verification tests are presented 相似文献
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UML协作图描述了系统的一个协作过程中参与对象之间的结构关系和交互行为,确认它们是否被正确实现是集成测试的工作.本文提出了一个基于UML协作图生成集成测试用例的方法,将表示设计的协作图作为测试模型,首先通过遍历每条消息的直接后继识别协作图中的表示用例实现的所有可能的场景路径,然后在遍历每条场景路径的过程中获取相应协作执行的路径条件、参数变量和预期方法调用序列,最后使用范畴-划分方法确定场景路径上的输入、输出、环境条件的合理组合作为覆盖该场景路径的测试用例,用于测试一个协作场景路径上的交互行为.该方法,集成了白盒方法和黑盒方法,在覆盖所有的测试需求的前提下,生成的测试用例较少. 相似文献