The degradation of TDDB characteristics of Si02/Si3N4/Si02 stacked films caused by surfaceroughness of Si3N4 films [DRAMs]

The effect of surface roughness of Si₃N₄ films on time-dependent dielectric breakdown (TDDB) characteristics of SiO₂/Si₃N₄/SiO₂ (ONO) stacked films was investigated. The surface roughness of Si₃N ₄ films-was found to become higher with increasing deposition temperature and to cause the degradation of TDDB characteristics of ONO films in DRAMs. A local thinning of ONO films, evaluated from the TDDB characteristics, agreed with the surface roughness measured by atomic force microscopy (AFM) and cross-sectional transmission electron microscopy (XTEM). Dependence of time to breakdown of ONO films on the deposition conditions was interpreted by electric field intensification due to the surface roughness of Si₃N₄ films     

Highly reliable SiO2/Si3N4 stackeddielectric on rapid-thermal-nitrided rugged polysilicon for high-densityDRAM's

Experimental results are presented demonstrating that by using rapid thermal nitridation (RTN) of rugged poly-Si surface prior to Si ₃N₄ deposition, the quality and reliability of reoxidized Si₃N₄ dielectric (ON dielectric with an effective oxide thickness of about 35 Å) can be significantly improved over ON films on rugged poly-Si without RTN treatment. These improvements include significantly reduced defect-related dielectric breakdown, 10³ × increase in TDDB lifetime, lower leakage current, and suppressed electron-hole trapping and capacitance loss during stress     

Mechanism of selective Si3N4 etching over SiO2 in hydrogen-containing fluorocarbon plasma

This paper describes the mechanism of selective Si₃N₄ etching over SiO₂ in capacitively-coupled plasmas of hydrogen-containing fluorocarbon gas, including CHF₃, CH₂F₂ and CH₃F. The etch rate of Si₃N₄ and SiO₂ is investigated as a function of O₂ percentage in all plasma gases. Addition of O₂ in feed gases causes plasma gas phase change especially H density. The SiO₂ etch rate decreases with increase of O₂ percentage due to the decline of CF_x etchant. The Si₃N₄ etch rate is found to be strong correlated to the H density in plasma gas phase. H can react with CN by forming HCN to reduce polymer thickness on Si₃N₄ surface and promote the removal of N atoms from the substrate. Thus the Si₃N₄ etch rate increases with H intensity. As a result, a relative high selectivity of Si₃N₄ over SiO₂ can be achieved with addition of suitable amount of O₂ which corresponds to the maximum of H density.     

Effects of surface pretreatment of polysilicon electrode prior toSi3N4 deposition on the electrical characteristicsof Si3N4 dielectric films

Effects of various surface pretreatments of polysilicon electrode prior to Si₃N₄ deposition on leakage current, time-dependent dielectric breakdown (TDDB) and charge trapping characteristics of thin Si₃N₄ films deposited on rugged and smooth poly-Si are investigated. Surface pretreatments consist of different combinations of HF clean, rapid thermal H₂ -Ar clean, and rapid thermal NH₃-nitridation (RTN) and are intended to modify the surface of bottom poly-Si electrode. Results show that RTN treatments lead to lower leakage current, reduced charge trapping, and superior TDDB characteristics as compared to rapid thermal H₂-Ar clean     

Electrical characterisation of Si3N4/SiO2 double layers on p-type 6H–SiC

MNOS, MNS and MOS devices have been fabricated on p-type 6H–SiC substrates without epitaxial layers. They have been characterised using high frequency CV, GV, and IV measurements. The high frequency CV characteristics of p-type 6H–SiC MNOS structures indicate a very similar interface quality to p-type 6H–SiC MOS devices. A lower effective fixed insulator charge Q_I is found in MNOS devices with a higher oxide thickness x_ox. An x_ox of 10 nm is effective in avoiding charge instability. The effective fixed insulator charge Q_I can be modified in the 10 nm oxide SiC MNOS devices by injecting carriers into the nitride. Similar leakage current characteristics compared to p-type 6H–SiC MNS structures have been found for p-type 6H–SiC MNOS devices, but the SiO₂/Si₃N₄ insulator current is lower, particularly for positive electric fields. At the oxide breakdown limit (−10 MV/cm), Poole–Frenkel conduction is observed in the nitride for negative electric fields due to direct tunnelling of holes into the nitride.     

pH, pK and pNa detection properties of SiO2/Si3N4 ISFET chemical sensors

This article reports the technological fabrication and the electrical characterisation of SiO₂/Si₃N₄ ion sensitive field effect transistors (ISFET) for the detection of H⁺, K⁺ and Na⁺ ions. ISFET chemical sensors show quasi-nernstian pH response with sensitivities around 54 mV/pH. pK and pNa measurements are also investigated, evidencing sensitivities lower than 20 mV/pH and non-nernstian pH-dependent phenomena for the highest K⁺ or Na⁺ concentrations (pK and pNa, respectively, lower than 4 and 3). It is shown that the detection properties of H⁺, K⁺ and Na⁺ ions are dependent on each other, being responsible for saturation effects for the highest concentrations. It is finally concluded that SiO₂/Si₃N₄ ISFETs are well adapted for the pH measurement, can be used for the pK or pNa measurements in the case of buffered solutions but are not fully suitable for multi-ion detection in the case of medical analysis.     

激光合成非晶态Si3N4粉末

本文描述了大功率CO2激光辐照SiH4+NH3的快速流动气体合成Si3H4超细粉末的实验,揭示了激光谱线变化对合成反应的影响。讨论了粉末红外吸收光谱的畸变现象等。     

Electrical Characteristics of Memory Devices With a High- k HfO2 Trapping Layer and Dual SiO2/Si3N4 Tunneling Layer

A novel device structure with a high-k HfO₂ charge storage layer and dual tunneling layer (DTL) (SiO₂/Si₃N₄) is presented in this paper. Combining advantages of the high trapping efficiency of high-k materials and enhanced charge injection from the substrate through the DTL, the device achieves a fast program/erase speed and a large memory window. The device demonstrates excellent retention due to its physically thick DTL and also improved endurance without any increase of programming V_th throughout the cyclic test as compared with SONOS Flash memory devices using an Si₃N₄ trapping layer.     

Trapping, conduction, and dielectric breakdown in Si3N4 films on as-deposition rugged polysilicon

Rugged polysilicon stacked capacitors recently emerged as the storage structures of choice for the manufacture of advanced DRAMs. The authors present the charge-trapping characteristics of such capacitors showing a capacitance increase of more than 50%. It is observed that electron trapping is dominant on rugged structures, whereas hole trapping is observed on smooth structures. Conduction and breakdown properties are also reported. Measurements show that rugged polysilicon capacitors provide the low leakage current, the sharp breakdown distributions, and the trapping characteristics needed for advanced DRAM applications     

Improved characteristics for Pd nanocrystal memory with stacked HfAlO–SiO2 tunnel layer

Stacked HfAlO-SiO₂ tunnel layers are designed for Pd nanocrystal nonvolatile memories. For the sample with 1.5 nm-HfAlO/3.5 nm-SiO₂ tunnel layer, a smaller initial memory window is obtained compared to the sample with 3.5 nm-HfAlO/1.5 nm-SiO₂ tunnel layer. Owing to the thermally induced traps in HfAlO-SiO₂ films are located at a farther distance from the Si substrate and more effective blocking of charge leakage by asymmetric tunnel barrier, a larger final memory window and better retention characteristic can be obtained for Al/blocking oxide SiO₂/Pd NCs/1.5 nm-HfAlO/3.5 nm-SiO₂/Si structure. A N₂ plasma treatment can further improve the memory characteristics. Better memory characteristics can be obtained for Pd-nanocrystal-based nonvolatile memory with an adequate thickness ratio of HfAlO to SiO₂.     

Charge trapping in silicon-rich Si3N4 thin films

Silicon-rich silicon nitride (SRN) films were grown by low pressure chemical vapour deposition (LPCVD) with excess silicon concentrations varying from 8.8 to 12.8%. All films were found to be predominantly -Si₃N₄ with free silicon crystallites being found in the films with the greatest silicon content.

MIS capacitors were fabricated from the films and transient flat band measurements were performed on these devices. For positive (negative) applied bias voltages, the flat band shift was in a positive (negative) direction implying a net increase in negative (positive) charge within the SRN film. A logarithmic time dependence was found for the transient flat band shift while for long periods of time (i.e. t > 1 s) the curren transient was found to be inversely proportional to time. A charge trapping model is presented which predicts a logarithmic increase in the flat band shift with time. The model is based on the simple assumption that there is electron tunnelling between the silicon valence and conduction bands and the deep defect levels in the SRN films. Very good agreement was found between the data and the model for low electric fields. At high fields, the situation becomes complicated by other transport processes which lead to a saturation of the flat band shift with time. The current transients are similarily affected. For these SRN films the density of trapping centres near the SRN-silicon interface was found to be of the order of 3 × 10¹⁹ cm⁻³.     

可调谐氮化硅波导微环谐振腔滤波器研究

设计并制备了一种基于热光效应的集成可调谐氮化 硅(Si₃N₄)波导微环谐振腔滤波器,通过采用马赫-曾德干涉仪(MZI)构成的可调谐 耦合器控制耦合区耦合比,以实现滤波器消光比的调谐。设计并优化了微环谐振 腔的波导截面尺寸、弯曲半径和耦合区波导间隔等参数,并通过光刻、反应离子刻蚀(RIE )等工艺制备 了两种不同弯曲半径的Si₃N₄波导微环谐振腔。实验结果表明,本文器件在波长1550nm附近处的自由光谱 范围(FSR)为68pm,3dB带宽约为16pm,品质因子Q达到了9.68×10 4,消光比可调范围约为17dB。     

Avalanche electron injection in 4-nmSi3N4/8-nm SiO2 dielectric structure:turn-around phenomenon and Si-SiO2 interface degradation

Charge trapping and interface-state generation in very thin nitride/oxide (4-nm Si₃N₄+8-nm SiO₂) composite gate insulators are studied as a function of gate electrode work function and bottom oxide thickness. The behavior of the trapped positive charge under bias-temperature stress after avalanche electron injection (AEI) is investigated. Evidence is presented that secondary hole injection from the anode (gate/Si₃N₄ interface) and subsequent trapping near the SiO₂-Si interface result in a turnaround of the flatband voltage shift during AEI from the substrate. Just like the thermal oxides on Si, slow-state generation near the SiO₂-Si interface and boron acceptor passivation in the surface-space charge layer of the Si substrate are also observed after AEI in these nitride/oxide capacitors, and they are found to be strongly related to the secondary hole injection and trapping. Finally, interface-state generation can take place with little secondary anode hole injection and is enhanced by the occurrence of hole trapping     

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO2/high-k gate stacked dielectric

A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor(DGJLT) for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO₂. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset, workfunction difference and k-values on the tunneling current of the DGJLT.     

Reactor characterization for a process to etchSi3N4 formed on thin SiO2

A plasma etching process for patterning LPCVD (low-pressure chemical vapor deposition) Si₃N₄ which has been formed on thin thermally grown SiO₂ has been developed and characterized with an Applied Materials 8110 batch system using 100-mm-diameter silicon wafers. To fulfill the primary process objectives of minimal critical dimension (CD) loss (~0.08 μm), vertical profiles after etch, retention of some of the underlying thermal SiO₂, and batch etch uniformity, the reactor has been characterized by evaluating the effects of variation of reactor pressure (15 to 65 mTorr), O₂ concentration by flow rate (30 to 70%) of an O₂/CHF₂ mixture, and DC bias voltage (-200 to -550 V). Analysis of the resulting etch rate, etch uniformity, dimensional, and profile data suggests that satisfactory processing may be achieved at low reactor pressure (~25 mTorr), 50-60% O₂ by flow rate in O₂/CHF₃, and low DC bias (-200 to -250 V)     

Walk-out phenomena in 6H-SiC mesa diodes with SiO2/Si3N4 passivation and charge trapping in dry and wet oxides on N-type 6H-SiC

The drift or “walk-out” of the breakdown voltage in 6H-SiC mesa diodes passivated by a double layer of 1000 Å SiO₂ and 3000 Å Si₃N₄ was studied and related to the charge trapping in the oxide. The first-order trapping kinetics using four distinct electron traps with trapping cross-sections in the range 10⁻¹⁶ to 10⁻¹⁹ cm² were found to best describe the breakdown voltage drift curves. The wet oxide trapping cross-sections are 2 to 10 times larger compared to the dry oxide ones, resulting in about one order of magnitude faster charging of the traps. No significant differences in the amount of drift and saturation level of breakdown voltage were found between the different passivations. The influence of UV illumination, supplied by a HeCd laser with wavelength 325 nm, on the walk-out characteristics and on the reverse current was also investigated. The build-up of the surface states was observed in wet oxide under UV illumination and DC stress. The results are consistent with the coexistence of large concentrations of positive charge and acceptor type deep interface electron traps. The walk-out is a result of the acceptor states being filled by hot electrons supplied by the mechanism of avalanche injection. The suitability of the walk-out measurements as a tool for characterisation of the charge trapping properties of the passivation is demonstrated.     

Excellent low-pressure-oxidized Si3N4 filmson roughened poly-Si for high-density DRAMs

High-reliability and good-performance stacked storage capacitors with high capacitance value of 17.8 fF/μm² has been realized using low-pressure-oxidized thin nitride films deposited on roughened poly-Si electrodes. These novel electrodes are fabricated by H ₃PO₄-etching and are RCA-cleaned. The leakage current density at +2.5 and -2.5 V are 0.07×10^-9 and -2.4×10^-8 A/cm², respectively, fulfilling the requirements of 256 Mb DRAM's. Weibull plots of time-dependent-dielectric-breakdown (TDDB) characteristics under constant current stress and constant voltage stress also show tight distribution and good electrical properties. Hence, this easy and simple technique is promising for future high-density DRAM's applications     

Superior low-pressure-oxidized Si3N4 films onrapid-thermal-nitrided poly-Si for high-density DRAM's

High-performance stacked storage capacitors with small effective-oxide-thickness (t_ox,eff) as thin as 37 Å has been achieved using low-pressure-oxidized nitride films deposited on NH ₃-nitrided poly-Si electrodes. The capacitors exhibit excellent leakage property and time-dependent dielectric-breakdown (TDDB) characteristics. Furthermore, this technique is promising for the 64- and 256-Mb dynamic-random-access-memory (DRAM) applications because the process temperatures never exceed 850°C     

基于氮化硅陶瓷毛细芯的低温回路热管研究

利用氮化硅陶瓷多孔材料作为毛细芯设计了一种以乙烷为工质的低温回路热管样机, 并对其降温及传热性能进行了研究。试验结果表明,通过在蒸发器上施加4 W的热量, 这种低温回路热管能够在常温下实现启动,并能顺利实现降温;在降温过程中,通过不断增大加热功率,可以加快低温回路 热管的降温;当蒸发器的温度为190 K时,该样机可以稳定传输30 W的热量。     

Oxidized Ta2O5/Si3N4dielectric films on poly-crystalline Si for dRAMs

A dielectric film technology characterized by a novel multilayer structure formed by oxidation of Ta₂O₅/Si₃ N₄ films on polysilicon has been developed to realize high-density dRAMs. The dry oxidation of the Ta₂O₅/Si₃N₄ layers was performed at temperatures higher than 900°C. This film has a capacitance per unit area from 5.5 to 6.0 fF/ μm², which is equivalent to that of a 6.0- to 6.5-nm-thick SiO₂. The leakage current at an effective electric field of 5 MV/cm is less than 10^-9 A/cm². Under such an electric field, the extrapolated time to failure for 50% cumulative failure can be as high as 1000 years