A 21-GHz 8-Modulus Prescaler and a 20-GHz Phase-Locked Loop Fabricated in 130-nm CMOS

A 1.5-V 256-263 8-modulus prescaler and a 1.5-V integer-N phase-locked loop (PLL) with eight different output frequencies have been implemented in a 0.13-mum foundry CMOS process. The synchronous divide-by-4/5 circuit uses current mode logic (CML) D-flip-flops with resistive loads to achieve 21-GHz maximum operating frequency at input power of 0 dBm. The divider is used to implement an 8-modulus prescaler consuming 6-mA current and 9-mW power. This extremely low power consumption is achieved by radically decreasing the sizes of transistors in the divider. Utilizing the prescaler, a charge-pump integer-N PLL has been demonstrated with 20-GHz output frequency. The in-band phase noise of the PLL at 60-kHz offset and out-of-band phase noise at 10-MHz offset are ~-80 dBc/Hz and -116.1 dBc/Hz, respectively. The locking range is from 20.05 to 21 GHz. The PLL consumes 15-mA current and 22.5-mW power from a 1.5-V power supply.     

A 50-GHz Phase-Locked Loop in 0.13-μ m CMOS

A 50-GHz charge pump phase-locked loop (PLL) utilizing an LC-oscillator-based injection-locked frequency divider (ILFD) was fabricated in 0.13-mum logic CMOS process. The PLL can be locked from 45.9 to 50.5 GHz and output power level is around -10 dBm. The operating frequency range is increased by tracking the self-oscillation frequencies of the voltage-controlled oscillator (VCO) and the frequency divider. The PLL including buffers consumes 57 mW from 1.5/0.8-V supplies. The phase noise at 50 kHz, 1 MHz, and 10 MHz offset from the carrier is -63.5, -72, and -99 dBc/Hz, respectively. The PLL also outputs second-order harmonics at frequencies between 91.8 and 101 GHz. The output frequency of 101 GHz is the highest for signals locked by a PLL fabricated using the silicon integrated circuits technology.     

A 9–31-GHz Subharmonic Passive Mixer in 90-nm CMOS Technology

A subharmonic down-conversion passive mixer is designed and fabricated in a 90-nm CMOS technology. It utilizes a single active device and operates in the LO source-pumped mode, i.e., the LO signal is applied to the source and the RF signal to the gate. When driven by an LO signal whose frequency is only half of the fundamental mixer, the mixer exhibits a conversion loss as low as 8–11 dB over a wide RF frequency range of 9–31GHz. This performance is superior to the mixer operating in the gate-pumped mode where the mixer shows a conversion loss of 12–15dB over an RF frequency range of 6.5–20 GHz. Moreover, this mixer can also operate with an LO signal whose frequency is only 1/3 of the fundamental one, and achieves a conversion loss of 12–15dB within an RF frequency range of 12–33 GHz. The IF signal is always extracted from the drain via a low-pass filter which supports an IF frequency range from DC to 2 GHz. These results, for the first time, demonstrate the feasibility of implementation of high-frequency wideband subharmonic passive mixers in a low-cost CMOS technology.     

A 140-GHz fundamental mode voltage-controlled oscillator in 90-nm CMOS technology

Fundamental mode voltage-controlled oscillators in F-band (90-140GHz) were fabricated using the UMC 90-nm logic CMOS process. The maximum operating frequencies of these three oscillators are 110, 123, and 140GHz, respectively. The 140-GHz voltage controlled oscillator provides -22 to -19-dBm output power, a frequency tuning range of 1.2GHz and phase noise of -85dBc/Hz at 2-MHz offset from the carrier, while consuming 8mA from a 1.2-V supply.     

A 25–75 GHz Broadband Gilbert-Cell Mixer Using 90-nm CMOS Technology

A compact and broadband 25-75-GHz fully integrated double-balance Gilbert-cell mixer using 90-nm standard mixed-signal/radio frequency (RF) CMOS technology is presented in this letter. A broadband matching network, LC ladder, for Gilbert-cell mixer transconductance stage design is introduced to achieve the flatness of conversion gain and good RF port impedance match over broad bandwidth. This Gilbert-cell mixer exhibits 3plusmn2dB measured conversion gain (to 50-Omega load) from 25 to 75GHz with a compact chip size of 0.30mm². The OP_{1 dB} of the mixer is 1dBm and -4dBm at 40 and 60GHz, respectively. To the best of our knowledge, this monolithic microwave integrated circuit is the highest frequency CMOS Gilbert-cell mixer to date     

A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS

A fully integrated 5-GHz low-power ESD-protected low-noise amplifier (LNA), designed and fabricated in a 90-nm RF CMOS technology, is presented. This 9.7-mW LNA features a 13.3-dB power gain at 5.5 GHz with a noise figure of 2.9 dB, while maintaining an input return loss of -14 dB. An on-chip inductor, added as "plug-and-play," i.e., without altering the original LNA design, is used as ESD protection for the RF pins to achieve sufficient ESD protection. The LNA has an ESD protection level up to 1.4 A transmission line pulse (TLP) current, corresponding to 2-kV Human Body Model (HBM) stress. Experimental results show that only minor RF performance degradation is observed by adding the inductor as a bi-directional ESD protection device to the reference LNA.     

Fully integrated 60-GHz single-ended resistive mixer in 90-nm CMOS technology

This letter presents the design and characterization of a fully integrated 60-GHz single-ended resistive mixer in a 90-nm CMOS technology. A conversion loss of 11.6dB, 1-dB compression point of 6dBm and IIP3 of 16.5dBm were measured with a local oscillator (LO) power of 4dBm and zero drain bias. The possibility of improvement in IIP3 with selective drain bias has been verified. A 3-dB improvement in IIP3 was obtained with 150-mV dc voltage applied at the drain. Microstrip transmission lines are used to realize matching and filtering at LO and radio frequency ports.     

An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS

A software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in use today, a wideband RF front-end, including the low-noise amplifier (LNA) and a wide tuning-range synthesizer, spanning over 800 MHz to 6 GHz is designed. The wideband LNA provides 18-20 dB of maximum gain and 3-3.5 dB of noise figure over 800 MHz to 6 GHz. A low 1/f noise and high-linearity mixer is designed which utilizes the passive mixer core properties and provides around +70 dBm IIP2 over the bandwidth of operation. The entire receiver circuits are implemented in 90-nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards     

具有30dB增益和1-16GHz带宽的CMOS低噪声中频放大器

This paper presents a high-gain wideband low-noise IF amplifier aimed for the ALMA front end system using 90-nm LP CMOS technology.A topology of three optimized cascading stages is proposed to achieve a flat and wideband gain.Incorporating an input inductor and a gate-inductive gain-peaking inductor,the active shunt feedback technique is employed to extend the matching bandwidth and optimize the noise figure.The circuit achieves a flat gain of 30.5 dB with 3 dB bandwidth of 1-16 GHz and a minimum noise figure of 3.76 dB.Under 1.2 V supply voltage,the proposed IF amplifier consumes 42 mW DC power.The chip die including pads takes up 0.53 mm~2,while the active area is only 0.022 mm~2.     

A digitally controlled 2.4-GHz oscillator in 65-nm CMOS

This article presents a 2.4-GHz digitally controlled oscillator (DCO) for the ISM band. The circuit is designed using a 65-nm CMOS technology with an operating voltage of 1.2 V. The DCO comprises an LC oscillator core and the digital interface logic. The measured total frequency range is from 2.26 to 3.04 GHz. Its frequency quantization step is approximately 20 kHz, and using a digital ΣΔ-modulator (SDM), its effective frequency resolution is better than 1 kHz. Current consumption of the oscillator core is tunable through a 6-bit digital word. The measured phase noise is −122 dBc/Hz at 1-MHz offset frequency with 4.8-mA current consumption.     

一种用于CMOS图像传感器的锁相环设计

设计了一种用于CMOS图像传感器时钟产生的电荷泵锁相环(CPPLL)电路.基于0.18μm CMOS工艺,系统采用常规鉴频鉴相器、电流型电荷泵、二阶无源阻抗型低通滤波器、差分环形压控振荡器以及真单相时钟结构分频器与CMOS图像传感器片内集成.系统电路结构简洁实用、功耗低,满足CMOS图像传感器对锁相环低功耗、低噪声、输出频率高及稳定的要求.在输入参考频率为5 MHz时,压控振荡器(VOC)输出频率范围为40～217 MHz,系统锁定频率为160MHz,锁定时间为16.6μs,功耗为2.5 mW,环路带宽为567 kHz,相位裕度为57°,相位噪声为一105 dBc/Hz@1 MHz.     

A 60-GHz 38-pJ/bit 3.5-Gb/s 90-nm CMOS OOK Digital Radio

A 60-GHz fully integrated bits-in bits-out on–off keying (OOK) digital radio has been designed in a standard 90-nm CMOS process technology. The transmitter provides 2 dBm of output power at a 3.5-Gb/s data rate while consuming 156 mW of dc power, including the on-chip 60-GHz frequency synthesizer. A pulse-shaping filter has been integrated to support high data rates while maintaining spectral efficiency. The receiver performs direct-conversion noncoherent demodulation at data rates up to 3.5 Gb/s while consuming 108 mW of dc power, for a total average transceiver energy consumption of 38 pJ/bit in time division duplex operation. To the best of the authors' knowledge, this is the lowest energy per bit reported to date in the 60-GHz band for fully integrated single-chip CMOS OOK radios.      

A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process

This paper presents an integrated CMOS power amplifier and a technique for correcting AM-PM distortion in power amplifiers. The linearization technique uses a varactor as part of a tuned circuit to introduce a phase shift that counteracts the AM-PM distortion of the power amplifier. The varactor is controlled by the amplitude of the IQ baseband data in a feedforward fashion. The technique has been demonstrated in a 5-GHz class-AB CMOS power amplifier designed for WLAN applications and implemented in a 90-nm CMOS process. The power amplifier delivers 16 dBm of average power while transmitting at 54 Mb/s (64 QAM). The proposed linearization technique is shown to improve the efficiency of the power amplifier by a factor of 2.8.     

26.5–30-GHz Resistive Mixer in 90-nm VLSI SOI CMOS Technology With High Linearity for WLAN

A resistive mixer with high linearity for wireless local area networks is presented in this paper. The fully integrated circuit is fabricated with a 90-nm very large scale integration silicon-on-insulator (SOI) CMOS technology and has a very compact size of 0.38 mm$, times,$0.32 mm. Design guidelines are given to optimize the circuit performance. Analytical calculations and simulations with an SOI large-signal Berkeley simulation model show good agreement with measurements. At an RF of 27 GHz, an IF of 2.5 GHz and zero dc power consumption, a conversion loss of 9.7 dB, a single-sideband noise figure of 11.4 dB, and a high third-order intercept point at the input of 20 dBm are measured at a local-oscillator (LO) power of 10 dBm. At lower LO power of 0-dBm LO power, the loss is 10.3 dB. To the knowledge of the author, the circuit has by far the highest operation frequency reported to date for a resistive CMOS mixer. Furthermore, it provides the highest linearity for a CMOS mixer operating at such high frequencies.     

A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS

This paper describes a single-cycle 64-bit integer execution ALU fabricated in 90-nm dual-Vt CMOS technology, operating at 4 GHz in the 64-bit mode with a 32-bit mode frequency of 7 GHz (measured at 1.3 V, 25/spl deg/ C). The lower- and upper-order 32-bit domains operate on separate off-chip supply voltages, enabling conditional turn-on/off of the 64-bit ALU mode operation and efficient power-performance optimization. High-speed single-rail dynamic circuit techniques and a sparse-tree semi-dynamic adder architecture enable a dense layout occupying 280 /spl times/ 260 /spl mu/m/sup 2/ while simultaneously achieving: (i) low carry-merge fan-outs and inter-stage wiring complexity; (ii) low active leakage and dynamic power consumption; (iii) high DC noise robustness with maximum low-Vt usage; (iv) single-rail dynamic-compatible ALU write-back bus; (v) simple 2/spl Phi/ 50% duty-cycle timing plan with seamless time-borrowing across phases; (vi) scalable 64-bit ALU performance up to 7 GHz measured at 2.1 V, 25/spl deg/ C; and (vii) scalable 32-bit ALU performance up to 9 GHz measured at 1.68 V, 25/spl deg/ C.     

A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS

This brief presents the design and implementation of a high-speed and high-accuracy power-switchable track-and-hold (T/H) in 90-nm CMOS that achieves a total harmonic distortion of $-$ 60 dB at 100 MS/s. With the proposed power-switching (P-S) technique, the T/H amplifier obtains not only further power optimization but also enhanced sampling speed and accuracy. The P-S technique requires no extra voltage headroom in the source-follower amplifier, thus allowing a relatively large input voltage swing of 0.8-$hbox{V}_{rm pp}$ in differential mode. A spurious-free dynamic range of 70 dB at 100 MS/s was measured with an input of 40.6 MHz and 0.8 $hbox{V}_{rm pp}$. While driving a 2.5-pF capacitive load, the T/H consumes 2.97 mW from the 1.2-V supply.      

A Multigigahertz Multimodulus Frequency Divider in 90-nm CMOS

This brief presents a multimodulus frequency divider with division ratio between 64 and 127 fabricated in 90-nm CMOS. By using a load-switching technique, high operating frequency, and low power static divider was achieved. The divider consists of six 2/3 divider stages. The maximum operating frequency is 4.7 GHz with current consumption 2.3 mA at low voltage supply 1.2 V and rms cycle-to-cycle jitter lower than 1 ps     

A Millimeter-Wave 90-nm CMOS Self-Mixing Frequency Divider

This letter presents a millimeter-wave 90 nm CMOS divide-by-four frequency divider using self-mixing technique. The output of the push-push oscillator mixes with the input signal, and the resulting intermediate frequency signal locks the fundamental oscillation frequency of the oscillator at exactly one-fourth of the input signal frequency. The frequency divider is implemented in TSMC 90 nm 1P9M digital CMOS technology and the overall die size is 0.91 mm $times,$ 0.53 mm. For low-power mode, the divider consumes only 0.8 mW with a 0.8 V supply voltage, and the measured locking range is 300 MHz. For normal mode, the divider consumes 2 mW with a 1 V supply, and the locking range is extended to 1100 MHz. The operating range of the divider covers from 46.1 to 52.8 GHz with varactor tuning and band switching.      

基于 PDSOI工艺的抗 SET锁相环设计

基于0．35μm PDSOI工艺设计了一款输出频率范围为700M Hz-1．0GHz的锁相环电路,利用Sentaurus TCAD工具对其进行单粒子瞬变（SET ）混合模拟仿真,确定其SET敏感部件并建立SET分析模型,分析了SET与锁相环系统参数之间的关系．通过增加由一个感应电阻、一对互补运算放大器和互补SET电流补偿晶体管组成的限流电路并利用多频带结构降低了VCO的增益,显著提升了锁相环的抗SET性能．仿真结果表明,CP中发生SET后VCO控制电压Vc的波动峰值、锁相环的恢复时间以及输出时钟的错误脉冲数明显降低,分别为未加固锁相环的43．9％、49．7％和29．1％,而辐射加固前后 VCO的基本结构变化不大,其SET轰击前后无明显变化．