一种轨到轨高速CMOS滞回比较器

本文介绍了一种预放大-锁存CMOS滞回比较器,在输入级采用轨到轨结构,使用一种新颖的电流求和电路,大大降低了输入级传输时延.器件采用sMIC0.18μm标准CMOS工艺库,在Cadence Spectre环境下仿真,结果表明:此较器的工作频率达到250MHz以上,静态工作电流为257μA,上升时延为1.94ns,下降时延为1.81ns,低频增益为89dB.     

一种D类功放中0.5 μm CMOS轨到轨比较器设计

文章设计了一种D类功放中的轨到轨比较器电路。相比于传统的比较器电路,该设计解决了共模信号输入范围大时性能不稳定的问题。仿真表明该比较器电路在-40～125℃和各种工艺角条件下,共模输入电压范围最大可以达到0～5.5V。在125℃高温和5.5V高压条件下,平均工作电流约为0.5mA,性能指标接近并部分超过一些商用芯片。该芯片已经通过0.5μm CMOS工艺流片验证,测试效果良好。     

一种高速高精度动态比较器

提出了一种应用于逐次逼近模数转换器的高速高精度比较器。该比较器由2级预放大器、1级锁存比较器以及缓冲电路构成。在前置预放大器中采用共源共栅结构、复位和箝位技术,提高了比较器的精度和速度,降低了功耗。在锁存比较器中引入额外的正反馈路径,提高了响应速度,降低了功耗。将锁存比较器输入对管与锁存结构隔离,降低了踢回噪声的影响,提高了比较器的精度。比较器基于SMIC 0.18 μm CMOS工艺进行设计与仿真。仿真结果表明,在1.8 V电源电压、800 MHz时钟下,比较器的精度为50 μV,传输延迟为458 ps,功耗为432 μW,芯片面积仅为0.009 mm²。     

基于单一PMOS差分对的轨到轨输入运算放大器设计

基于国内某CMOS工艺设计了一种单一PMOS差分对的轨到轨输入、恒跨导CMOS运算放大器。输入级电路采用折叠共源共栅结构,通过体效应动态调节输入管的阈值电压扩展共模输入范围到正负电源轨,恒定共模输入范围内的跨导,自级联电流镜有源负载将差分输入转换为单端输出;输出级电路采用AB类结构实现轨到轨输出,线性跨导环确定输出管的静态偏置电流。在5 V电源电压,2.5 V共模电压,1 MΩ负载条件下,经Spectre仿真验证,该运算放大器开环增益为119 dB,相位裕度为58°,共模输入范围为0.0027～4.995 V,共模范围内跨导变化小于3%,实现了轨到轨输入共模范围内的跨导恒定。     

轨到轨电压比较器的设计

比较器在模数转换及其他模拟功能模块中都是非常重要的器件,其速度和精度直接影响模块的功能.采用SMIC 0.18 CMOS混合信号工艺,设计了一种轨到轨电压比较器,电路结构主要包括前置放大器、锁存器和输出缓冲电路,此外,采用一种β倍增的自偏置基准电路提供偏置电流.结果表明,在3.3V的供电电压下,提供共模范围为300 mV～3.3 V的信号,可分辨输入信号的最小频率为200 MHz,单级运放相位裕度大于60°,输出信号占空比为40％～60％,比较阈值约为10 mV,输入输出延时小于5 ns,功耗小于18 mW,版图面积小于200 μm× 150 μm.该比较器的失真较小,在整个输入信号范围内有较高的共模抑制比,较大限度地提高了电路的性能.     

一种高速轨对轨折叠式共源共栅运算放大器设计

介绍了一种低电压、低功耗、动态摆幅大、高频带的运算放大器,电路采用恒定跨导的轨对轨输入级,偏置电路采用折叠共源共栅电流镜结构,采用0．35uM CMOS工艺实现,有较好的兼容性,可应用于基带数字通信芯片设计及其相关领域。     

数字可编程的宽电压范围比较器

提出的比较器采用基准电压源产生2.5 V的电压,用电阻串并结合数字译码器和模拟开关通过控制码可以产生参考电压范围从0.039～4.922 V的64个等级的比较器参考电压,利用PMOS差分对管和NMOS差分对管同时作为输入实现轨到轨的放大器作为预放大级,级联迟滞比较器实现电压比较.采用CSMC的0.5 μm工艺流片,测试结果显示,比较器可以通过数字编程在地电压到电源电压的范围内实现电压比较.     

一种改进输入级结构的轨至轨运算放大器设计

基于0.18μm CMOS标准工艺设计了一种改进输入级结构的轨至轨运算放大器电路。该电路由输入级电路、共源共栅放大电路、共源输出电路及偏置电路组成。通过引入正反馈的MOS耦合对管将输入级电路改进为预放大电路,然后对其进行了详细分析,利用Cadence软件对电路进行仿真。仿真结果表明本文结构的低频直流开环增益可以达到80 dB,比相同参数下的普通结构高20 dB左右。相位裕度达到73o,共模输入电压范围满足全幅摆动,共模抑制比低频时可以达到107 dB。     

一种高速轨到轨输出差分放大器设计

随着电子系统对功耗和电源电压的要求日益严苛,传统差分输出放大器的输出幅度、速度和驱动能力等受到严重限制。针对该问题,提出了一种高速轨到轨输出差分放大器。通过采用“H”桥结构,在有限的功耗下可以实现大带宽和压摆率;采用静态电流精确可控的AB类输出级,实现了接近轨到轨的输出幅度和大输出驱动能力;采用三级放大结构实现100 dB以上的高增益;嵌套式密勒(Nested Miller)频率补偿保证了系统的稳定性,共模反馈电路则设置了合适的静态工作点保证电路可以正常工作。测试结果表明,提出的高速轨到轨输出差分放大器实现了0.5 mV量级的输入失调电压,0.2~4.8 V的输出幅度,400 MHz的-3 dB带宽和1300 V/μs的压摆率。     

一种高速低失调比较器电路设计

本文分析了两级动态比较器的瞬态特性,设计了一种高速低失调的两级动态比较器电路。相比于传统的两级动态比较器,本设计只需要单相时钟信号,通过增加第一级动态预放大电路的有效增益,既降低了比较器的延迟时间,也减小了等效输入失调电压。本设计采用90nm CMOS工艺实现,所有的分析结果都通过了仿真验证。     

恒跨导高摆率轨对轨运算放大器的设计

本文在分析MOS管恒跨导输入级和AB类输出级运算放大器的基础上设计了一个高摆率、恒跨导的轨对轨运算放大器。在输入级中采用了齐纳二极管的稳压原理,保证Rail-to-Rail运算放大器的输入跨导恒定。为了实现高转换率,本文采用了一种新型的压摆率提高电路。另外,为了提高系统的稳定性,采用了控制零点的米勒补偿进行频率补偿。采...     

Low power time-domain rail-to-rail comparator with a new delay element for ADC applications

In this paper, a rail-to-rail time-domain comparator with low power supply voltage and low power consumption is introduced. The comparator can be employed in low-power converters and biomedical applications. In the proposed time-domain comparator, a rail-to-rail delay element has been employed to generate a significant voltage-to-time gain for the full range of input signals. This circuit is designed, laid out, and simulated in 0.18 μm TSMC technology and powered by 0.6 V and 1 V supply voltages. The simulation results show that the proposed comparator has a rail-to-rail dynamic range and the power consumption of the circuit is 0.6 μW and 19 μW at the clock frequency of 10 MHz and 100 MHz, respectively. The active area of 56 μm × 14 μm shows the compactness of the circuit comparing to the other similar works. The proposed comparator was used in an ADC to show its effectiveness to improve the performance of the ADC. An 8-bit 0.8 V 100 kS/s SAR-ADC is designed and simulated. It consumes 430 nW and the figure of merit is 19.3fJ/conversion-step.     

基于最小电流选择的运算放大器设计

设计了一种工作电压为3V恒跨导满幅CMOS运算放大器,针对轨对轨输入级中存在的跨导不恒定和简单AB类输出级性能偏差这2个问题,提出了利用最小电流选择电路来稳定输入级的总跨导;浮动电流源控制的无截止前馈AB类输出级实现了运放的满幅输出,同时减小了交越失真。该电路通过HSpice进行仿真验证,在0～3V输入共模范围内,输入级跨导的变化小于3.3%,开环增益为93dB,单位增益带宽为8MHz,相位裕量为66°。     

低压工作的轨到轨输入／输出缓冲级放大器

本文提出了一种低压工作的轨到轨输入／输出缓冲级放大器。利用电阻产生的输入共模电平移动,该放大器可以在低于传统轨到轨输入级所限制的最小电压下工作,并在整个输入共模电压范围内获得恒定的输入跨导;它的输出级由电流镜驱动,实现了轨到轨电压输出,具有较强的负载驱动能力。该放大器在CSMCO．6-μmCMOS数模混合工艺下进行了HSPICE仿真和流片测试,结果表明：当供电电压为5V,偏置电流为60uA,负载电容为10pF时,开环增益为87．7dB,功耗为579uw,单位增益带宽为3．3MHz;当该放大器作为缓冲级时,输入3VPP10kHz正弦信号,总谐波失真THD为53．2dB。     

Single-bit digital comparator circuit design using quantum-dot cellular automata nanotechnology

The large amount of secondary effects in complementary metal–oxide–semiconductor technology limits its application in the ultra-nanoscale region. Circuit designers explore a new technology for the ultra-nanoscale region, which is the quantum-dot cellular automata (QCA). Low-energy dissipation, high speed, and area efficiency are the key features of the QCA technology. This research proposes a novel, low-complexity, QCA-based one-bit digital comparator circuit for the ultra-nanoscale region. The performance of the proposed comparator circuit is presented in detail in this paper and compared with that of existing designs. The proposed QCA structure for the comparator circuit only consists of 19 QCA cells with two clock phases. QCA Designer-E and QCA Pro tools are applied to estimate the total energy dissipation. The proposed comparator saves 24.00% QCA cells, 25.00% cell area, 37.50% layout cost, and 78.11% energy dissipation compared with the best reported similar design.     

A 75 μW rail-to-rail class AB CMOS operational amplifier

A new class AB CMOS operational amplifier featuring rail-to-rail output swing is presented. The proposed circuit operates with an output voltage supply of 1 V only, while the overall power consumption is lower than 75 μW. The output stage shows a quiescent current of 15 μA, while it guarantees a peak current of 220 μA. The slew rate is 1.5 V μs⁻¹ (C₁ = 150 pF) and the THD is −63 dB, when a 0.98 V_pp−10.4 kHz sinewave is applied, as measured on an experimental prototype realised with a standard 0.8 μm CMOS process. The circuit presented is suitable for use in portable hand-set systems or in medical aids.     

Design of a window comparator with adaptive error threshold for online testing applications

This paper presents a novel window comparator circuit whose error threshold adjusts adaptively with respect to its input signal levels. Advantages of adaptive error thresholds over constant or relative error thresholds in analog testing applications are discussed. Analytical equations for guiding the design of the comparator circuitry are derived. The proposed comparator circuit has been designed and fabricated using a CMOS technology. Measurement results of the fabricated chip are presented.     

激光外差干涉仪相位计的设计

外差信号的比相处理是决定外差干涉仪精度、分辨率等性能的重要因素。为了解决比相计的分辨率和检测速度之间的矛盾,采用比相方法进行了测量原理、应用特点及局限性的理论分析,给出了相应的解决方案。结果表明,基于现场可编程门阵列的整周期采样可以提高自相关方法的测量精度,混频过零检测方法可以提高测量速度。     

A low-voltage complementary metal-oxide semiconductor adapter circuit suitable for input rail-to-rail operation

In this article, a low-voltage complementary metal-oxide semiconductor (CMOS) input signal adapter (ISA) suitable for input rail-to-rail operation of various types of analogue basic building blocks is presented. The adapter acts as a pre-stage with infinite input resistance and linear transfer characteristics. Its input signal is translated into the region fitting the operating range of the following stage. The generality of the proposed method is proven through the application of the ISA in different types of analogue basic building blocks designed in 0.5 μm CMOS technology. They are the following: below-negative-rail-to-above-positive-rail voltage-controlled transconductor, quasi rail-to-rail voltage-controlled resistor (VCR), rail-to-rail operational amplifier (OA) and quasi rail-to-rail second generation current conveyor. The proposed negative resistance quasi rail-to-rail VCR and rail-to-rail OA have been used in a Sallen and Key band-pass filter. All of these analogue basic building blocks and their applications in the form of the Sallen and Key band-pass filter operate from a single supply of 1.5 V. Simulation results confirm the predictions of the analysis performed.     

可用于Class D的电流反馈比较器设计

设计一款可用于Class D的比较器。在考虑抗噪能力和分辨率的情况下,引入2路电流反馈,提高抗噪能力,从而可以提高分辨率。采用HHNEC BCD035工艺对该调制器进行电路级设计并用Cadence仿真,该电路可抑制输出电压的错误跳变,失调电压为0.2 mV,增益为38.42 dB,3 dB带宽达到20 MHz,满足高速率要求。