高精度低功耗电流采样电路设计

为了实现低功耗高精度电流检测,文中设计了一种基于运算放大器的具有对称结构的电阻采样结构,该结构不仅实现采样电压和采样电流的高线性度,而且能实现对微弱采样信号的可靠检测。设计的电路架构中包含5个电流-电压转换阶段,基于Hspice仿真,设计电路内部匹配电阻网络,以减小输入失调电压对采样的影响,拓展共模输入范围。该采样电路架构通过某0.35μm BCD工艺实现,版图面积仅为0.12 mm2,实测结果证明其工作电流小于1μA,采样电压检测精度高达5 mV,且具有高速响应能力。     

一种面向单片DC/DC的低压高效片上电流检测技术

本文提出并实现了一种面向电流模式单片开关DC/DC转换器的低压高效片上电流采样电路.该电路利用功率管等效电阻电流检测技术和无需OP放大器的源极输入差分电压放大技术,使电路的应用范围可低达2.3V;-3dB带宽12MHz;在最大负载电流情况下的静态电流峰值仅19μA,比常规采用功率管镜像电流检测技术的静态电流峰值低1.5个量级左右.转换器基于0.5μm 2P3M Mixed Signal CMOS工艺设计制作.测试结果表明,电流检测电路的最大检测电流1.1A,转换器的输入最低电压2.3V,重负载转换效率高于93%.     

用于电源测试的精确压控电流阱

为了检测潜在的电源缺陷,必须进行动态和静态测试。这里的简单电流阱可测试低到中功率电源和恒压源。在该应用中,在输入电压范围为0V～5V,电源电压最高为20V时,电流阱可吸收0A～1.5A的电流。该电路的基本部件为一个精密运放IC1,采用Texas Instruments的OPA277。该器件特点为：最大输入偏置电压仅为100μV,最大输入偏置电流为4nA,在-40℃-＋85℃温度范围内温漂较低（图1）。运放IC将其正输入电压与检测电阻RSENSE上的电压进行比较。     

一种瞬态增强的无外接电容LDO电路设计

设计了以增强型AB跟随器作为缓冲级的带瞬态增强电路的线性稳压器(LDO)。在保证LDO环路稳定性的同时,将增强型AB跟随器的偏置电流改为动态偏置电流,同时加入瞬态增强电路来改善系统重载到轻载来回跳变时的瞬态性能。仿真结果表明,该稳压器输入电压2.7~5 V,输出电压2.5 V,压差200 m V,电路空载时静态电流18μA,最大负载电流100 m A;在输出电容为100 pF时,负载电流以99×10~(–3)A/μs跳变,输出电压下冲和过冲分别为89 m V和110 m V,均在1.5μs内恢复稳定。     

可测定电容器和半导体开关漏电电流的简单夹具

图1a中的电路由一个电压跟随器IC1,和参考电压源IC2构成.IC1是Analog Devices的AD8661运算放大器,其输出偏置电流不超过1pA,其典型输入偏置电流为0.3pA(参考文献1).IC2为Ana-log Devices的ADR391精密电压基准(参考文献2).制造商将此运算放大器的输入偏置电压调整到不超过100μV,典型值为30μV.这些特性使这种放大器适合用于观测各种类型的电容器自放电.固体钽电容和采用高质量塑料电介质电容的漏电电流远远超过了电压跟随器IC1的输入偏置电流.     

微型高边检流放大器

MAX9937是高边检流放大器,采用外部电阻设置电压增益,大大提高了设计灵活性。其可提供电池反向（错误）连接保护,还具有-20～＋40V感应电压及瞬态（抛负载）保护。MAX9937的输入共模范围为4～28V,与VCC电源电压（2．7～5．5V）无关。当VCC为5V时,电源电流低至20μA。当VCC为0V时,检流电阻上的输入偏置电流仅为1μA,以使ECU关断期间电池消耗最小。器件的电压增益由两个外部电阻的分压比设置,精度与电阻有关。输入失调电压（VOS）非常小,仅为±1．2mV（最大值）。MAX9937提供微型、3mm×3Mm、5引脚SC70封装。     

任意比例系数的同相比例运算电路

给出了任意比例系数的同相比例运算电路,分析了比例系数与平衡电阻、反馈电阻的关系。探索了比例系数任意取值时同相比例运算电路构成形式的变化。在输入端电阻平衡时,输入信号比例系数在大于1、小于1及等于1情况下,同相比例运算电路还可简化。所述方法的创新点是将运放输入端电阻的平衡条件转化为与输入信号比例系数的关系,从而可直观确定简化电路形式,扩大了同相比例运算电路的应用范围。     

加减法运算电路的设计方法

给出了任意比例系数的加减法运算电路,分析了比例系数与平衡电阻、反馈电阻的关系。目的是探索比例系数任意取值时加减法运算电路构成形式的变化。结论是在输入端电阻平衡时,各加运算输入信号比例系数之和与各减运算输入信号比例系数之和的差值在大于1、小于1或等于1情况下,加减法运算电路还可简化。所述方法的创新点是将运放输入端电阻的平衡条件转化为与输入信号比例系数的关系,从而可直观确定简化电路形式;扩大了加减法运算电路的应用范围。     

一种新颖的电压模式通用二阶CFA滤波器设计

提出了一种仅用2个电流反馈放大器(CFA)实现的三输入单输出电压模式通用二阶滤波器电路。该电路由2个电流反馈放大器(CFA)、2个电容、3个电阻构成,他能实现二阶低通、带通、高通、陷波、全通滤波函数。分析了该电路的电压传输函数及电路参数,并用PSpice对该电路进行了仿真,仿真结果表明,该电路设计正确,电路结构简单,所用元器件少。     

一种无片外电容的快速响应FVF-LDO北大核心

提出了一种无片外电容、快速瞬态响应、宽输入电压范围的低压差线性稳压器(LDO)。该电路基于翻转电压跟随器(FVF)结构，不需额外增加辅助电路，仅使用两个电容作为检测模块，以动态调整瞬态响应，能够弥补传统LDO集成度低、面积大、功耗高、瞬态响应差的不足。电路基于TSMC 180 nm CMOS工艺。仿真结果表明，该LDO的压差为200 mV,静态电流为36μA,输入电压范围为2～4 V,低频时PSRR为-59 dB。在30 pF负载电容、0～10 mA负载电流、150 ns阶跃时间条件下，产生的上冲电压为50 mV,下冲电压为66 mV,瞬态电压恢复时间为300 ns。     

A bulk-driven quasi-floating gate FVF current mirror for low voltage,low power applications

This paper introduces a new low-voltage, low-power FVF current mirror circuit. The bulk-driven (BD) technique is employed to achieve extended input voltage swing and low supply voltage. Besides, the quasi-floating gate (QFG) is used to achieve high frequency performance. The merging of (BD) and (QFG) appear as a good and attractive solution to improve the circuit performance with reduced supply voltage. Benefiting from the interesting properties of (BD-QFG) MOSFET (MOST) technique, the proposed FVF current mirror circuit exhibits superior performance compared to other previously reported works. The workability of the proposed circuit has been verified through ELDO simulator based on a 0.18 μm USMC process. It achieves an enhanced bandwidth (2.7 GHz), low power consumption (79.33 μW), a low input impedance (130 Ω), and high output impedance (9.5 G Ω) from a low supply voltage (0.8 V). Monte Carlo simulation is also carried out, which proves the robust performance of the proposed circuit against mismatches. An application of the proposed current mirror is presented in the form of the current comparator to ensure the workability of the proposed BD-QFG current mirror.     

一种无运放低压低功耗CMOS带隙基准电压源的设计

采用无运放电路结构,通过改进反馈环路和调整电阻的方法,设计了一种低电压低功耗的带隙基准电压源.相比传统有运放结构,电路芯片面积更小和具有更低的电流损耗,并且大部分电流损耗都用于产生输出电压.基于CSMC 0.5 μmCMOS工艺对所研制带隙基准电压源进行流片,测试结果表明,当电源电压大于0.85 V时,能够产生稳定的输...     

Very Low Power, Low Voltage, High Accuracy, and High Performance Current Mirror

A novel low power and low voltage current mirror with a very low current copy error is presented and the principle of its operation is discussed.In this circuit,the gain boosting regulated cascode scheme is used to improve the output resistance,while using inverter as an amplifier.The simulation results with HSPICE in TSMC 0.18 μm CMOS technology are given,which verify the high performance of the proposed structure.Simulation results show an input resistance of 0.014 Ω and an output resistance of 3 GΩ.The current copy error is favorable as low as 0.002％ together with an input (the minimum input voltage of vin,min～ 0.24 V) and an output (the minimum output voltage of vout,min～ 0.16 V) compliances while working with the 1 V power supply and the 50 μA input current.The current copy error is near zero at the input current of 27 μA.It consumes only 76 μW and introduces a very low output offset current of 50 pA.     

低压工作的轨到轨输入／输出缓冲级放大器

本文提出了一种低压工作的轨到轨输入／输出缓冲级放大器。利用电阻产生的输入共模电平移动,该放大器可以在低于传统轨到轨输入级所限制的最小电压下工作,并在整个输入共模电压范围内获得恒定的输入跨导;它的输出级由电流镜驱动,实现了轨到轨电压输出,具有较强的负载驱动能力。该放大器在CSMCO．6-μmCMOS数模混合工艺下进行了HSPICE仿真和流片测试,结果表明：当供电电压为5V,偏置电流为60uA,负载电容为10pF时,开环增益为87．7dB,功耗为579uw,单位增益带宽为3．3MHz;当该放大器作为缓冲级时,输入3VPP10kHz正弦信号,总谐波失真THD为53．2dB。     

一种低温漂低功耗的简易带隙基准电压设计

电压基准在模拟电路中提供一个受电源或温度等影响较小的参考电压,以保证整个电路正常工作。设计了一种低温漂低功耗带隙基准电压源,采用不受电源影响的串联电流镜做偏置．利用PTAT电压的正向温度系数和基极发射极电压的负向温度系数特性,以适当的系数加权构造零温度系数的电压量。该设计避开了运放的应用．结构简易,原理清晰,便于入门级的同学在短时间内学习掌握。0-70℃范围内,温漂系数为16．4ppm／℃。供电电压在5-6V范围内变化时,电源抑制比达57．7dB。总输出噪声为140．3μV,功耗为300．6μW。     

一种新颖的多值基准输出缓冲器设计

对比分析了不同结构的传统多值基准输出缓冲器,提出了一种新颖的多值基准输出缓冲器结构.采用PMOS输出结构提高了输出电压摆幅,利用低输出阻抗结构加快了瞬态响应速度,解决了传统结构无法兼具高输出与快响应的矛盾,电路功耗低、易补偿.基于0.15 μm标准CMOS工艺,用Hspice软件对电路进行仿真.仿真结果表明,当电源电压...     

A novel ultra-high compliance, high output impedance low power very accurate high performance current mirror

In this paper a novel ultra-high compliance, low power, very accurate and high output impedance current mirror/source is proposed. Deliberately composed elements and a good combination (for a mutual auto control action) of negative and positive feedbacks in the proposed circuit made it unique in gathering ultra-high compliances, high output impedance and high accuracy ever demanded merits. The principle of operation of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by HSPICE simulation in TSMC 0.18 μm CMOS, BSIM3 and Level49 technology. Simulation results with 1 V power supply and 8 μA input current show an input and output minimum voltages of 0.058 and 0.055 V, respectively, which interestingly provide the highest yet reported compliances for current mirrors implemented by regular CMOS technology. Besides an input resistance of 13.3 Ω, an extremely high output resistance of 34.3 GΩ and −3 dB cutoff frequency of 210 MHz are achieved for the proposed circuit while it consumes only 42.5 μW and its current transfer error (at bias point) is the excellent value of 0.02%.     

A 0.8 V low power low phase-noise PLL

A low power and low phase noise phase-locked loop(PLL) design for low voltage(0.8 V) applications is presented.The voltage controlled oscillator(VCO) operates from a 0.5 V voltage supply,while the other blocks operate from a 0.8 V supply.A differential NMOS-only topology is adopted for the oscillator,a modified precharge topology is applied in the phase-frequency detector(PFD),and a new feedback structure is utilized in the charge pump(CP) for ultra-low voltage applications.The divider adopts the extende...     

A single current conveyor-based low voltage low power bootstrap circuit for ElectroCardioGraphy and ElectroEncephaloGraphy acquisition systems

In this letter we propose a novel low voltage and low power single-CCII bootstrap circuit specifically designed to be implemented as input stage in ElectroCardioGraphy (ECG) or ElectroEncephaloGraphy (EEG) acquisition systems. The proposed circuit implements only a second generation current conveyor that has been designed to obtain, at X and Z nodes, reduced parasitic impedances, so improving CCII performance. Moreover, simulation results are also presented for a two electrodes ECG system. The circuit, designed in a standard 0.35 μm CMOS technology, shows low voltage (1.5 V) low power (28 μW) characteristics, so it is particularly suitable for portable applications.     

A low power and low distortion rail-to-rail input/output amplifier using constant current technique

A rail-to-rail amplifier with constant transconductance,intended for audio processing,is presented.The constant transconductance is obtained by a constant current technique based on the input differential pairs operating in the weak inversion region.MOSFETs working in the weak inversion region have the advantages of low power and low distortion.The proposed rail-to-rail amplifier,fabricated in a standard 0.35μm CMOS process,occupies a core die area of 75×183μm~2.Measured results show that the maximum power consumption is 85.37μW with a supply voltage of 3.3 V and the total harmonic distortion level is 1.2%at 2 kHz.