Effective Schottky Barrier Height Reduction Using Sulfur or Selenium at the NiSi/n-Si (100) Interface for Low Resistance Contacts

We explore a novel integration approach that introduces valence-mending adsorbates such as sulfur (S) or selenium (Se) by ion implantation and prior to nickel silicidation for the effective reduction of contact resistance and Schottky barrier (SB) height at the NiSi/n-Si interface. While a low SB height of ~0.12 eV can be obtained for NiSi formed on S-implanted n-Si, the insertion of a 1000degC anneal prior to silicidation leads to S out-diffusion and loss of SB modulation effects. We demonstrate that Se-implanted Si does not suffer from Se outdiffusion even after a 1000degC anneal, and subsequent Ni silicidation formed an excellent ohmic contact with a low SB height of 0.13 eV. Se segregation at the NiSi/n-Si (100) interface occurred. Implantation of Se and its segregation at the NiSi/n-Si interface is a simple and promising approach for achieving reduced SB height and contact resistance in future high-performance n-channel field-effect transistors.     

Adjustment of NiSi/n-Si SBH by post-silicide of dopant segregation process

The post-silicide of dopant segregation process for adjusting NiSi/n-Si SBH (Schottky barrier height) is described. Adopting the analysis of the I-V characteristic curve and extrapolating the SBH of NiSi/n-Si Schottky junction diodes (NiSi/n-Si SJDs), the effects of different of process parameters dopant segregation, including segre gation anneal temperature and dopant implant dose, on the properties of the NiSi/n-Si SJDs have been studied, and the corresponding mechanisms are discussed.     

SBH adjustment characteristic of the dopant segregation process for NiSi/n-Si SJDs

By means of analyzing the Ⅰ-Ⅴ characteristic curve of NiSi/n-Si Schottky junction diodes(NiSi/n-Si SJDs), abstracting the effective Schottky barrier height (φB,eff) and the ideal factor of NiSi/n-Si SJDs and measuring the sheet resistance of NiSi films (RNiSi),we study the effects of different dopant segregation process parameters,including impurity implantation dose,segregation annealing temperature and segregation annealing time,on the φB,eff of NiSi/n-Si SJDs and the resistance characteristic of NiSi films.In addition,the changing rules of φB,eff and RNiSi are discussed.     

A p-Ge1-xCx/n-Si heterojunction diode grownby molecular beam epitaxy

We report on the fabrication and characterization of the first p-n diode made from a heterojunction of epitaxial p-type Ge_0.998C _0.002 on an n-type Si substrate. Epitaxial Ge_0.998C_0.002 was grown on a (100) Si substrate by solid source molecular beam epitaxy. The p-GeC/n-Si junction exhibits diode rectification. The I-V characteristics of the p-GeC/n-Si diode indicate a reasonable reverse saturation current of 89 pA/μm² at -1 V and a high reverse breakdown voltage in excess of -40 V. Photoresponse from the Ge_0.998C_0.002 p-n diode was observed from 1.3-μm laser excitation resulting in an external quantum efficiency of 1.4%     

Fabrication and electrical characterization of p-NiPc/n-Si heterojunction

Nickel-phthalocyanine (NiPc) thin film was prepared by thermal evaporation method on n-Si single-crystal substrate to fabricate p-NiPc/n-Si heterojunction. The electrical transport properties of the p-NiPc/n-Si heterojunctions were investigated by temperature-dependent current-voltage (I-V) measurements and room temperature capacitance-voltage (C-V) measurements. The temperature-dependent I-V characteristics revealed that the forward conduction was determined by thermionic-emission and space-charge-limited current (SCLC) mechanisms at low and high voltage, respectively⋅ On the other hand, the reverse current is limited by the carrier generation process. The 1/C²-V plot indicated the junction was abrupt and the junction built-in potential was 0.61 V at room temperature.     

Ni(Pt)Si硅化物温度稳定性的研究

对比研究了夹层结构N i/P t/N i分别与掺杂p型多晶硅和n型单晶硅进行快速热退火形成的硅化物薄膜的电学特性。实验结果表明,在600~800°C范围内,掺P t的N iS i薄膜电阻率低且均匀,比具有低电阻率的镍硅化物的温度范围扩大了100~150°C。依据吉布斯自由能理论,对在N i(P t)S i薄膜中掺有2%和4%的P t样品进行了分析。结果表明,掺少量的P t可以推迟N iS i向N iS i2的转化温度,提高了镍硅化物的热稳定性。最后,制作了I-V特性良好的N i(P t)S i/S i肖特基势垒二极管,更进一步证明了掺少量的P t改善了N iS i肖特基二极管的稳定性。     

A novel split-gate MOSFET design realized by a fully silicided gate process for the improvement of transconductance and output resistance

Work function tuning of nickel silicide (NiSi) gates was utilized to fabricate a novel split-gate MOSFET with improved device performance. The MOSFET with a NiSi split gate has been achieved by implanting antimony into the polysilicon gate from the drain side with a tilt angle, followed by a full nickel-silicidation process. The laterally nonuniform antimony implantation causes the NiSi gate work function to vary from the source side to the drain side due to the dopant segregation effect. Improved current drive and output resistance are observed in the MOSFET with such a NiSi split gate. Metal gate advantages and NiSi process simplicity were also realized in the split-gate process, and gate oxide quality did not degrade due to the low temperature process. This split-gate design is expected to be applicable in the nanoscale regime by optimizing process conditions.     

Reduction of Leakage and Low-Frequency Noise in MOS Transistors Through Two-Step RTA of NiSi-Silicide Technology

A two-step rapid thermal annealing (RTA) nickel salicidation process was employed to fabricate 0.1-$muhboxm$gate length CMOS transistors. Excess salicidation, common in the conventional one-step RTA NiSi process, is effectively suppressed by this approach, which is confirmed by transmission electron microscopy (TEM) images. More improvements due to two-step NiSi are observed in NMOS than in PMOS transistors: The$ n^+- p$junction diode with two-step NiSi exhibits lower reverse leakage and higher breakdown voltage than the one-step silicided diode. For the first time, it is found that two-step NiSi NMOS exhibits significant reduction in off-state leakage$(sim!hbox5times)$and low-frequency noise (up to two orders of magnitude) over one-step NiSi NMOS, although there is not much difference in PMOS transistors.     

Temperature dependence of current–voltage characteristics of MoS2/Si devices prepared by the chemical vapor deposition method

Layers of MoS₂ are directly deposited on the n-type Si (n-Si) substrate by chemical vapor deposition for fabricating a MoS₂/n-Si heterojunction device. The rectification current–voltage (I–V) characteristics of MoS₂/n-Si devices were measured in the temperature range from 80 to 300 K in steps of 20 K. The temperature-dependent forward-bias I–V characteristics can be explained on the basis of the thermionic emission theory by considering the presence of the interfacial inhomogeneous barriers at the MoS₂/n-Si interfaces. The dominance of the induced carrier capture/recombination by states at the MoS₂/n-Si interface that lead to the formation of the inhomogeneous barriers serves to influence the photo-response at room temperature. The fabricated MoS₂/n-Si devices exhibit reversible switching between high and low current densities, when the simulated sunlight is turned on and off. The sensitivity of the I–V characteristics to temperature provides an opportunity to realize stable and reliable rectification behaviors in the MoS₂/n-Si devices. It is found that the electron mobility in the n-Si layer reduces as temperature increases, which leads to the noticeably increased value of the series resistance of MoS₂/n-Si devices.     

NiSi/Si界面的剖面透射电镜研究

采用不同硅化工艺制备了NiSi薄膜并用剖面透射电镜(XTEM)对样品的NiSi/Si界面进行了研究.在未掺杂和掺杂(包括As和B)的硅衬底上通过物理溅射淀积Ni薄膜,经快速热处理过程(RTP)完成硅化反应.X射线衍射和喇曼散射谱分析表明在各种样品中都形成了NiSi.还研究了硅衬底掺杂和退火过程对NiSi/Si界面的影响.研究表明:使用一步RTP形成NiSi的硅化工艺,在未掺杂和掺As的硅衬底上,NiSi/Si界面较粗糙;而使用两步RTP形成NiSi所对应的NiSi/Si界面要比一步RTP的平坦得多.高分辨率XTEM分析表明,在所有样品中都形成了沿衬底硅〈111〉方向的轴延-NiSi薄膜中的一些特定晶面与衬底硅中的(111)面对准生长.同时讨论了轴延中的晶面失配问题.     

Ni(W)Si/Si肖特基势垒二极管电学特性研究

文中首次提出在Ni中掺入夹层W的方法来提高NiSi的热稳定性。具有此结构的薄膜,经600℃～800℃快速热退火后,薄层电阻保持较低值,小于2Ω/□。经Raman光谱分析表明,薄膜中只存在NiSi相,而没有NiSi2生成。Ni(W)Si的薄层电阻由低阻转变为高阻的温度在800℃以上,比没有掺W的镍硅化物的转变温度的上限提高了100℃。Ni(W)Si/Si肖特基势垒二极管能够经受650℃～800℃不同温度的快速热退火,肖特基接触特性良好,肖特基势垒高度为0.65eV,理想因子接近于1。     

Study of NiSi/Si Interface by Cross-Section Transmission Electron Microscopy

采用不同硅化工艺制备了NiSi薄膜并用剖面透射电镜(XTEM)对样品的NiSi/Si界面进行了研究.在未掺杂和掺杂(包括As和B)的硅衬底上通过物理溅射淀积Ni薄膜,经快速热处理过程(RTP)完成硅化反应.X射线衍射和喇曼散射谱分析表明在各种样品中都形成了NiSi.还研究了硅衬底掺杂和退火过程对NiSi/Si界面的影响.研究表明:使用一步RTP形成NiSi的硅化工艺,在未掺杂和掺As的硅衬底上,NiSi/Si界面较粗糙;而使用两步RTP形成NiSi所对应的NiSi/Si界面要比一步RTP的平坦得多.高分辨率XTEM分析表明,在所有样品中都形成了沿衬底硅〈111〉方向的轴延-NiSi薄膜中的一些特定晶面与衬底硅中的(111)面对准生长.同时讨论了轴延中的晶面失配问题.     

Reverse recovery transient characteristic of PEDOT:PSS/n-Si hybrid organic-inorganic heterojunction

We study the junction behavior of poly (3,4-ethylenedioxythiophene):polystyrenesulphonate/n-Si hybrid organic/inorganic heterojunction by reverse recovery transient (RRT) characterization. RRT response for PEDOT:PSS/n-Si hybrid junction is reported for various n-Si doping concentration and forward bias current injection level. The presence of settling time of 8.3–23.5 μs in the RRT response in contradiction to Schottky junction model commonly assumed for PEDOT:PSS/n-Si hybrid structure. The decrease in the minority carrier lifetime from 126.8 μs to 39.5 μs with increased n-Si doping concentration, suggests that minority carriers are stored at n-Si side of the junction, which is consistent with a p⁺-n junction model for the hybrid structure. The minority carrier lifetime is found to depend on forward bias current injection level, attributed to trap-saturation effect of the recombination-centers at the PEDOT:PSS/n-Si junction. The DC-IV characteristics of the PEDOT:PSS/n-Si hybrid junction are also consistent with the notion of diffusion and trap assisted recombination dominated dark current. The diffusion dominated transport of PEDOT:PSS/n-Si leads to an ideal p⁺-n junction behavior that leverages on the good transport properties of Si. Our findings are important in the modeling and optimization of the characteristics of electronic devices based on the organic/Si hybrid junction.     

Geometrical and crystal structures,optical absorption and device characterization of N-(5-{[antipyrinyl-hydrazono]-cyanomethyl}-[1,3,4]thiadiazol-2-yl)-benzamide

The molecular structure of the N-(5-{[antipyrinyl-hydrazono]-cyanomethyl}-[1,3,4]thiadiazol-2-yl)-benzamide (ACTB) is optimized theoretically in which the energies of highest occupied molecular orbital and lowest unoccupied molecular orbital are calculated. ACTB crystalizes in triclinic structure with a space group, P2. ACTB thin films were prepared by using thermal evaporation technique onto quartz and n-Si single crystal substrates. The optical properties of the films are investigated in terms of the spectrophotometric measurements of the transmittance and reflectance. The current–voltage (I–V) characteristics of the fabricated In/ACTB/n-Si/Au diode are studied in temperature range 298–398 K. The device showed rectification behavior. At low forward voltage, the thermionic theory is applied for determining the ideality factor and barrier height as a function of temperature. The series resistance of the device is found to decrease with increasing temperature. At relatively high forward voltage, the space charge limited current dominated by exponential distribution of traps is found to be the operating mechanism in which the trapping parameters and charge carriers mobility are estimated.     

Novel SiC/Si heterostructure negative-differential-resistance diodefor use as switch with high on/off current ratio and low powerdissipation

A novel p-SiC/n-Si heterostructure negative-differential-resistance (NDR) diode with special current-voltage (I-V) characteristics is reported. Under reverse biases, the I-V curve of this device possesses an N-shaped NDR with a high peak-to-valley current ratio (PVCR) and a broad high-impedance valley region. For use as a switch, it can easily achieve a very low off-state current and a high on/off current ratio, as compared to the conventional N-shaped NDR devices. Hence, performance with a more effective switching action and lower power dissipation can be expected. Furthermore, obvious NDR's can even be obtained at a temperature up to 300°C, indicating this device is also potential for high-temperature applications     

Image Charge and Dipole Combination Model for the Schottky Barrier Tuning at the Dopant Segregated Metal/Semiconductor Interface

First-principle-based calculations are given to explain the Schottky barrier height (SBH) modifications of nickel silicide/silicon contacts by dopant atoms. Dopant atoms, including B, Al, In, Mg, P, As, Sb, and S, are placed near the $hbox{NiSi}_{2}$/Si interface, and a systematic study of their effects on the band structure is considered. A new image charge and dipole combination model is proposed to explain the SBH tuning by these atoms, which is in good agreement with experimental observations. Both image charge and dipole moment provide the same p-SBH lowering direction for B atom and the same n-SBH lowering direction for Sb atom. Therefore, the total lowering of the SBH is enhanced for B and Sb; thus, they are good candidates for SBH modifications of nickel silicide/silicon contacts in CMOS applications.      

AsP/InSe Van der Waals Tunneling Heterojunctions with Ultrahigh Reverse Rectification Ratio and High Photosensitivity

Van der Waals heterojunctions made of 2D materials offer competitive opportunities in designing and achieving multifunctional and high‐performance electronic and optoelectronic devices. However, due to the significant reverse tunneling current in such thin p–n junctions, a low rectification ratio along with a large reverse current is often inevitable for the heterojunctions. Here, a vertically stacked van der Waals heterojunction (vdWH) tunneling device is reported consisting of black arsenic phosphorus (AsP) and indium selenide (InSe), which shows a record high reverse rectification ratio exceeding 10⁷ along with an unusual ultralow forward current below picoampere and a high current on/off ratio over 10⁸ simultaneously at room temperature under the proper band alignment design of both the Schottky junction and the heterojunction. Therefore, the vdWH tunneling device can function as an ultrasensitive photodetector with an ultrahigh light on/off ratio of 1 × 10⁷, a comparable responsivity of around 1 A W^?1, and a high detectivity over 1 × 10¹² Jones in the visible wavelength range. Furthermore, the device exhibits a clear photovoltaic effect and shows a spectral detection capability up to 1550 nm. The work sheds light on developing future electronic and optoelectronic multifunctional devices based on the van der Waals integration of 2D materials with designed band alignment.     

Effects of prolonged annealing on NiSi at low temperature (500°C)

The effects of prolonged annealing (10 h) at low temperature (500°C) have been studied in 20-nm Ni/Si (100) thin films using Rutherford backscattering spectroscopy (RBS), x-ray diffraction (XRD), scanning electron microscopy (SEM) in conjunction with energy-dispersive spectrometry (EDS), and four-point probe techniques. We observe that nickel monosilicide (NiSi) is stable up to 4 h annealing at 500°C. It is also found that, after 6 h and 10 h annealing, severe agglomeration sets in and NiSi thin films tear off and separate into different clusters of regions of NiSi and Si on the surface. Due to this severe agglomeration and tearing off of the NiSi films, sheet resistance is increased by a factor of 2 despite the fact that no NiSi to NiSi₂ transition occurs. It is also observed that, with increasing annealing time, the interface between NiSi and Si becomes rougher.     

Spike Annealing as Second Rapid Thermal Annealing to Prevent Pure Nickel Silicide From Decomposing on a Gate

To create a nickel-monosilicide (NiSi) film with superior electrical properties, two-step rapid thermal annealing (RTA) was optimized. Using in situ chemical dry cleaning and increasing initial RTA temperature makes it possible to macroscopically transform nickel into NiSi without causing oxygen contamination. Nevertheless, di-nickel silicide (Ni$_{2}$Si) remaining on the top surface of NiSi on ${rm p}^{+}$-doped gate degrades the electrical properties of the NiSi film. This top-surface Ni $_{2}$Si is formed by decomposition of NiSi by conventional second RTA and appears as a disconnection of the NiSi film on the logic test device or agglomeration of silicon and nickel on the blanket NiSi film with activation energy of 2.92 eV. Using “spike RTA” with higher temperature suppresses the decomposition of NiSi and activates transformation of Ni$_{2}$ Si to NiSi. It is concluded that the proposed two-step RTA significantly improves the uniformity of the electrical properties of NiSi in 65-nm-node logic devices.      

Towards implementation of a nickel silicide process for CMOS technologies

In this paper, we review some of the advantages and disadvantages of nickel silicide as a material for the electrical contacts to the source, drain and gate of current and future CMOS devices. We first present some of the limitations imposed on the current cobalt silicide process because of the constant scaling, of the introduction of new substrate geometries (i.e. thin silicon on insulator) and of the modifications to the substrate material (i.e. SiGe). We then discuss the advantages of NiSi and for each of the CoSi₂ limitations, we point out why Ni is believed to be superior from the point of view of material properties, miscibility of phases and formation mechanisms. Discussion follows on the expected limitations of NiSi and some of the possible solutions to palliate these limitations.