An expandable time-division circuit switching LSI and networkarchitecture for broadband ISDN

A broadband network architecture is proposed that integrates multimedia services, such as data, video, and telephony information, using 52-Mb/s based STM-paths at the user network interface (UNI). The user can access any new service via the STM-based access network via either synchronous transfer mode (STM) switching or asynchronous transfer mode (ATM) switching. STM circuit switching supports long duration, constant bandwidth data transfer services such as video and high-definition television (HDTV) distribution and will also be used for the crossconnect system. Circuit switching can provide transparent transmission during long connection periods. This paper also proposes an expandable time-division switch architecture, an expandable time-division switching LSI, and an expandable switching module for small to large size system applications. The proposed time-division switching LSI, module, and system handle 52-Mb/s bearer signals and have throughputs of 2.4 Gb/s, 10 Gb/s, and 40 Gb/s, respectively. The time-division switch realizes video distribution with 1:n connections. Finally, a local switching node that features an expandable 52-Mb/s time-division circuit switching network is shown for multimedia access networking     

1 Gbit/s, 32*32 high-speed space-division switching module for broadband ISDN using SST LSIs

A high-speed 32*32 space-division switching module for high-definition TV broadcasting and switching systems is described. It employs a newly developed Si-bipolar SST 8*8 switch LSI, high-speed peripheral ICs and a high-speed impedance-controlled board. The module is capable of a 1.0 Gbit/s signal speed using 1:1 and 1:n connections.<>     

A 1.8 Gb/s GaAs optoelectronic universal switch LSI withmonolithically integrated photodetector and laser driver

A high-speed monolithic optical interface switch LSI is developed using a GaAs MSM photodetector and large-scale integrated electric circuits. This LSI operates universally as a 1.8 Gb/s optical-input/optical-output four-channel time-division switch, a 1.8 Gb/s optical-input/electrical-output 1:4 demultiplexer, a 2.0 Gb/s electrical-output 4:1 multiplexer, and a 2.8 Gb/s electrical-input/electrical-output 4×4 space-division switch. It uses a new multistage 2×2 switch block with small hardware and high-speed operation. It can be expanded to a 16×16 optical-input/optical-output time-division switch operating at up to 1.8 Gb/s for broadband-ISDN     

Newly structured expandable 52-Mbit/s, 48-channel time-division switching LSI with 2.4 Gbit/s throughput

An expandable Si bipolar 2.4 Gbit/s throughput, 52 Mbit/s 48-channel time-division switching LSI system is described. A high-throughput of 2.4 Gbit/s and a power-dissipation of 5.3 W are achieved by adopting a low-voltage swing four-serial-gated differential bipolar circuit design and super self-aligned process (SST-1A) logic-in-memory LSI technology. This LSI is applicable to the digital video time-division switching and digital crossconnect systems of future B-ISDN.<>     

Digital Time Division Switching for Military Communications

This paper describes system designs and design techniques applied in the design of a digital time-division switching system for a military communication network. The digital switches are interconnected by bit interleaved digital time-division multiplexed trunk groups. The switching system uses an advanced non-blocking, bit interleaved, digital time-division switch matrix to switch synchronous voice and data communications. The nodes of the model network are timed by high accuracy atomic clocks and use first-in-first-out buffers to compensate for clock frequency differences. The digital switching system uses common channel digital message signaling to communicate signaling and supervision data between connected switching centers. Signaling channels use a comprehensive error control system to provide reliable signaling and maintain signaling throughput in adverse transmission noise environments. The switching system's stored program control provides a telephone switching system which can be applied to many different networks. The flexible stored program control enables the same hardware system to perform switching for networks with different network signaling and/or routing/numbering plans.     

A 1.5 Gb/s 8×8 cross-connect switch using a time reservationalgorithm

An input queuing type switching architecture that uses a high-performance contention resolution algorithm to achieve high-speed and large-capacity cross-connect switching is presented. The algorithm, called the time reservation algorithm, features time scheduling and pipeline processing. The performance of this switch is evaluated by computer simulation. The throughput of this switch is about 90%, without requiring high internal operation speeds. Three LSI designs are developed to verify the feasibility of the high-speed switch. They are the input buffer controller LSI, the contention-resolution module LSI, and the space-division switching LSI. The LSIs were constructed with an advanced Si-bipolar high-speed process. Also, 8×8 cross-connect switching boards are introduced. The measured maximum port speed is 1.55 Gb/s     

A 2 Gb/s expandable space-division switching LSI and networkarchitecture for gigabit-rate broad-band circuit switching

An expandable space-division (SD) switch architecture and a bipolar circuit design for gigabit-per-second crosspoint-switch LSIs are described. An expandable 2-Gb/s 16×16 crosspoint switch LSI which employs a novel switch structure, a novel circuit design, and a super self-aligned process (SST-1A) is developed. A switching module and partial 1:n nonblock, full 1:1 nonblock switching network architecture are also presented. Using the LSI and the switching network architecture, an experimental 620-Mb/s network system is demonstrated     

High-Speed Time Switch Using GaAs LSI Technology

A high-speed time switch using GaAs LSI technology is discussed. A new high-speed time switch structure consisting primarily of shift registers is proposed. This structure requires relatively minimal hardware in designing LSI. As the first stage of study, a GaAs 4-channel time switch LSI is manufactured using this structure. Switching speed of the LSI is 2 Gbits/s and the power consumption 0.64 W/chip. Largecapacity switch configurations using this time switch are proposed. This high-speed time switch makes possible the time-division switching of such services as T.V. and high-definition T.V.     

Optical TDM sorting networks for high-speed switching

The general time-space-time switching problem in telecommunications requires the use of multichannel time slot interchangers. We propose two multichannel time slot sorters which sort N² time-division multiplexed (TDM) optical inputs, arranged as N frames with N time slots per frame using O(Nlog²N) optical switch elements. The TDM optical inputs are sorted in place without expanding the space-time fabric into a space-division switch. The hardware components used are 2×2 optical switches (LiNbO₃ directional couplers) and optical delay lines connected in a feedforward fashion. Two space-time variants of the spatial odd-even merge algorithm are used to design the sorters. By maintaining the number of shift-exchange operations invariant at each stage, the proposed sorters use fewer switches than previously proposed sorters using switches with feedback line delays. The use of local control at each 2×2 switch makes the proposed sorters more practical for high-speed optical inputs than Benes-based time slot permuters with global control and high latency, which affects interframe distance. Both time slot sorters support pipelining of input frames and sorted outputs are available at each time slot after an initial frame delay. The proposed sorters find practical application in the time-domain equivalents of space-division, nonblocking, self-routing packet switches using the sort-banyan architecture, such as the Starlite switch, Sunshine switch, etc     

2 Gbit/s, 16*16 expandable high-speed space-division-switch LSI using SST

A Si bipolar 2 Gbit/s 16*16 high-speed space-division-switch LSI is described. High-speed operation of 2 Gbit/s and low-power dissipation of 2.8 W are achieved by adopting a new expandable structure, a very low voltage swing-differential bipolar circuit design and a super self-aligned process technology (SST-1A). This LSI is applicable to future B-ISDN HDTV switching systems.<>     

Semiconductor devices in photonic switching

Three types of photonic switching networks have been proposed, namely, optical space-division switching, optical wavelength-division switching. Optional function devices required for each switching network are as follows: optical switch matrix for space-division switching; optical memory and optical write/read gate for time-division switching; and tunable wavelength filter and wavelength converter for wavelength-division switching. Recent progress in semiconductor functional devices such as modulators, switching devices, bistable devices, and wavelength control devices, which would be key devices to build switching networks, is reviewed     

A 622-Mb/s 8×8 ATM switch chip set with shared multibufferarchitecture

An asynchronous transfer mode (ATM) switch chip set, which employs a shared multibuffer architecture, and its control method are described. This switch architecture features multiple-buffer memories located between two crosspoint switches. By controlling the input-side crosspoint switch so as to equalize the number of stored ATM cells in each buffer memory, these buffer memories can be treated as a single large shared buffer memory. Thus, buffers are used efficiently and the cell loss ratio is reduced to a minimum. Furthermore, no multiplexing or demultiplexing is required to store and restore the ATM cells by virtue of parallel access to the buffer memories via the crosspoint switches. Access time for the buffer memory is thus greatly reduced. This feature enables high-speed switch operation. A three-VLSI chip set using 0.8-μm BiCMOS process technology has been developed. Four aligner LSIs, nine bit-sliced buffer-switch LSIs, and one control LSI are combined to create a 622-Mb/s 8×8 ATM switching system that operates at 78 MHz. In the switch fabric, 155-Mb/s ATM cells can also be switched on the 622-Mb/s port using time-division multiplexing     

Newly structured 512 Mbit/s high-speed time-division switch

The letter describes the recently developed fastest time-division switch experimental system operating at 512 Mbit/s. The system adopts a new switch structure which can increase switching throughput by four times over the basic structure to ensure high-speed performance. Also employed in the switch are two types of peripheral logic developed using Si bipolar super-self-aligned process technology. This switch makes possible the ISDN time-division switches necessary for TV and high-definition TV communication.     

20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems

An 8×8 self-routing hardware switch providing 20.8 Gb/s throughput has been developed for asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. A new mechanism for data processing and distributing high-speed signals is proposed. This switching system consists of three LSIs using a 0.5-μm gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells with eight cell channels, a negotiation network for screening of cells destined for the same output port, and a demultiplexer LSI for converting the cell streams from the switching network LSI to the eight streams per channel. These LSIs are mounted in a 520-pin multichip module package. The total number of logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and its throughput is 20.8 Gb/s     

A 0.8-μm BiCMOS ATM switch on an 800 Mb/s asynchronous bufferedbanyan network

An experimental element switch LSI for asynchronous transfer mode (ATM) switching systems was realized using 0.8-μm BiCMOS technology. The element switch transfers cells asynchronously when used in a buffered banyan network. Three key features of the element switch architecture are CASO buffers to increase the throughput, a synchronization technique called SCDB (synchronization in a clocked dual port buffer) to make possible asynchronous cell transmission on the element switches with simple hardware, and an implementation technique for virtual cut through, called CELL-BYPASS, which lowers the latency. An implementation of elastic store is proposed to achieve high-speed synchronization with simple hardware. The element switch LSI adopts an emitter-coupled-logic (ECL) interface. The maximum operation frequency of the element switch LSI is 200 MHz (typical)     

Testing of three-stage switching networks for coupling faults

A coupling fault diagnosis procedure is proposed for digital switching networks constructed of uniform time-division switches. The procedure is executed in two phases. Each phase consists of eight test steps; the number of tests for detecting the most likely coupling faults inside a single switch is independent of the network size. The concept of primitive and convolutional test vectors is introduced in order to analyze test stimuli applied to successive switches during the test. The approach can be easily adapted for use in many modern digital exchanges     

High-Speed Time Division Switch for 32-Mbit/s Bearer Rate Signals

This paper describes the high-speed time division switch employed in a 32-Mbit/s bearer signal communications system. System performance is realized by using three technologies. The first is a switch structure referred to as a 2-RAM 2-bank structure which ensures high-speed performance by increasing switching throughput four times over that of the basic structure. The second is the inclusion in the switch of two types of peripheral logic developed using Si-bipolar super-self-aligned process technology. The third is high-speed synchronous transmission of data. A large channel capacity time division switching network is also discussed. In conjunction with the network, these technologies make it possible to realize the ISDN time division switches necessary for such services as TV and high-definition TV communications.     

Design of transmission and multiplexing systems for broadbandpacket networks

Dynamic time-division multiplexing (DTDM) is a flexible network transport technique capable of handling both continuous and bursty traffic effectively. By using three different multiplexing architectures in the network, DTDM permits graceful evolution of the existing circuit switching network into a flexible broadband packet communications network supporting integrated voice, data, and video traffic. The first multiplexing stage uses a packet assembler to multiplex different broadband services into a common DTDM-format serial bit stream. The second multiplexing stage uses a statistical packet multiplexer to concentrate network traffic for more efficient use of transmission facilities. The third multiplexing stage uses a synchronous time-division multiplexer for high-speed point-to-point transparent transmission. The multiplexer uses a simple tributary synchronization scheme based on positive and negative block justification, which combines the concept of controlled-slip and bit-stuffing techniques while maintaining information integrity. A generic CMOS LSI chip has been designed for use in the three-stage multiplexing system     

Ingénierie des systèmes de commutation optique et des réseaux locaux à large bande sur fibres optiques : analyses et perspectives

This paper first reviews how switching evolves in the ISDN environment with emphasize placed on changes in conventionnal time-division switches, then assesses techniques and technologies usable in optical switching and broadband networks : optical space-division switching systems (architecture, technologies based on dielectrics, semiconductors, photorepactive material) and optical time-division switching (optical memories based on delay lines and on bistable components multiplexing); multiple access networks (tdma, multiple access by code) ; switching using spread spectrum (bit switching); wavelength switching (multiplexer-demultiplexer, tunable laser and filters) ; packet switching in multi-wavelength networks (broadband networks standardization, local area networks with bus, passive star or multi-star configuration).     

Distributed Microprocessors Control Architecture for Versatile Business Communications

This paper describes the NEAX®2400 Information Management System (IMS), which is no longer a conventional telephone switching system, but is instead a switching hub for various office automation equipment. The NEAX2400 IMS not only provides various circuit-switching functions such as conventional voice communication (telephone) switching, low-speed and high-speed data switching, but also provides stored and forward capabilities for voice (voice mail) and data (text mail, facsimile mail, etc.). This paper especially emphasizes the basic EPBX features and functions of the NEAX2400 IMS. The standard 64 kbit/s PCM technique is used for digitalization of voice signals, and switched through a nonblocking architecture time-division digital network. All digital data signals are transmitted through the same time-division digital network at the 64 kbit/s rate intermixed with digital voice signals. The controls of the switching functions, station service features, and maintenance service are performed by functionally divided distributed microprocessers. The most outstanding attribute of the NEAX2400 IMS is the unique building-block architecture of the equipment configuration. Modules are stacked above the basic module as the number of line and trunk ports, or additional stored and forward features are required. Up to four additional modules can be stacked up as a single module group. This unique arrangement permits the NEAX2400 IMS to be very flexible in its system applications and expandability. Practically, the NEAX2400 IMS will economically service as few as 184 ports (mixture of voice/data, line/trunk) and can be continuously expanded to as many as 23 184 ports.