The tiling phenomenon in /spl Sigma//spl Delta/ modulation

The theoretical error signal analysis of a sigma-delta (/spl Sigma//spl Delta/) modulator is a difficult problem due to the presence of a nonlinear operation (the amplitude quantization) in a feedback loop. In this paper, new deterministic knowledge on the transfer function of a /spl Sigma//spl Delta/ modulator is established, thanks to some recently observed properties of its state variables. For a large class of typical /spl Sigma//spl Delta/ modulators with constant inputs, the state variables appear to remain in a tile. We show what characteristics in a /spl Sigma//spl Delta/ modulator are specifically responsible for this property and give some initial proof of it. Under a constant input, the tiling phenomenon has as fundamental consequence that the output is a fixed and memoryless modulo function of n successive integrated versions of the input. This gives the theoretical knowledge that the modulator has an equivalent feedforward circuit expression. We give some immediate theoretical consequences on error analysis including the case of time-varying inputs.     

A time-delay jitter-insensitive continuous-time bandpass /spl Delta//spl Sigma/ modulator architecture

In this paper, we present a new continuous-time bandpass delta-sigma (/spl Delta//spl Sigma/) modulator architecture with mixer inside the feedback loop. The proposed bandpass /spl Delta//spl Sigma/ modulator is insensitive to time-delay jitter in the digital-to-analog conversion feedback pulse, unlike conventional continuous-time bandpass /spl Delta//spl Sigma/ modulators. The sampling frequency of the proposed /spl Delta//spl Sigma/ modulator can be less than the center frequency of the input narrow-band signal.     

Continuous-time /spl Delta//spl Sigma/ modulators using distributed resonators

We derive a method for using distributed resonators in /spl Delta//spl Sigma/ modulators and demonstrate these /spl Delta//spl Sigma/ modulators have several advantages over existing /spl Delta//spl Sigma/ modulator architectures. Like continuous-time (CT) /spl Delta//spl Sigma/ modulators, the proposed /spl Delta//spl Sigma/ modulators do not require a high-precision track-and-hold, and additionally can take advantage of the high-Q of distributed resonators. Like discrete-time /spl Delta//spl Sigma/ modulators, the proposed /spl Delta//spl Sigma/ modulators are relatively insensitive to feedback loop delays and can subsample. We present simulations of several types of these /spl Delta//spl Sigma/ modulators and examine the challenges in their design.     

Hybrid /spl Sigma//spl Delta/ modulators with adaptive calibration

This paper describes an architecture for stable high-order /spl Sigma//spl Delta/ modulation. The architecture is based on a hybrid /spl Sigma//spl Delta/ modulator, wherein hybrid integrators replace conventional analog integrators. The hybrid integrator, which is a combination of an analog integrator and a digital integrator, offers an increased dynamic range and helps make the resulting high-order /spl Sigma//spl Delta/ modulator stable. However, the hybrid /spl Sigma//spl Delta/ modulator relies on precise matching of analog and digital paths. In this paper, a calibration technique to alleviate possible mismatch between analog and digital paths is proposed. The calibration adaptively adjusts the digital integrators so that their transfer functions match the transfer functions of corresponding analog integrators. Through behavioral-level simulations of fourth-order /spl Sigma//spl Delta/ modulators, the calibration technique is verified.     

Breaking the feedback loop of a class of /spl Sigma//spl Delta/ A/D converters

/spl Sigma//spl Delta/ modulation is the currently successful technique used to perform high resolution analog-to-digital conversion. In spite of its practical success, its theoretical signal analysis has remained limited because a /spl Sigma//spl Delta/ modulator contains of a feedback loop that includes a nonlinear operation, i.e., the amplitude discretization or quantization. The feedback allows us to use oversampling to compensate for the limitations of the quantizer in resolution and in precision, which are typical of analog circuits. However, because of the lack of signal analysis, it is still not clear how much resolution of conversion can be gained as a function of the oversampling. We show that for a large class of /spl Sigma//spl Delta/ modulators, the feedback loop theoretically yields an equivalent feedforward signal flow graph, at least for constant inputs. This is possible thanks to remarkable modulo properties of these modulators. This equivalence can be asymptotically extrapolated to time-varying inputs with increasing oversampling. Although the exact components of the equivalent graph are not currently known in general, the theoretical structure of the feedforward graph is sufficient to point out misconceptions in the current knowledge on the final resolution of an nth-order /spl Sigma//spl Delta/ modulator. Specifically, except when the modulator is "ideal", the global resolution of conversion increases by n bits per octave of oversampling, instead of the currently believed rate of n+(1/2) bits/octave.     

High-order electromechanical /spl Sigma//spl Delta/ modulation in micromachined inertial sensors

Analysis of second-order electromechanical sigma-delta (/spl Sigma//spl Delta/) inertial sensors shows that in-band quantization error introduces a resolution penalty, which cannot be eliminated by oversampling. In addition, a tradeoff between resolution and phase compensation forces such systems to operate with reduced phase margin. This paper introduces high-order electromechanical /spl Sigma//spl Delta/ modulation as an approach, which eliminates the quantization noise overhead and allows for increased phase compensation without degrading the resolution. Quasi-linear analysis is used to evaluate the contribution of the individual noise sources to the output of the system and to examine the effect of noise interaction on the behavior of electromechanical /spl Sigma//spl Delta/ modulators.     

Adaptive order reduction scheme for high-order single-bit /spl Delta//spl Sigma/ Modulators

A scheme for achieving adaptive reduction in the order of the loop filter of usual high-order, single-stage, single-bit Delta-Sigma (/spl Delta//spl Sigma/) modulators is proposed in order to improve their performance. The resulting /spl Delta//spl Sigma/ modulators can recover from instability effectively, having also an extended input signal range in comparison to that of the corresponding conventional /spl Delta//spl Sigma/ modulators.     

IF-sampling fourth-order bandpass /spl Delta//spl Sigma/ modulator for digital receiver applications

Bandpass modulators sampling at high IFs (/spl sim/200 MHz) allow direct sampling of an IF signal, reducing analog hardware, and make it easier to realize completely software-programmable receivers. This paper presents the circuit design of and test results from a continuous-time tunable IF-sampling fourth-order bandpass /spl Delta//spl Sigma/ modulator implemented in InP HBT IC technology for use in a multimode digital receiver application. The bandpass /spl Delta//spl Sigma/ modulator is fabricated in AlInAs-GaInAs heterojunction bipolar technology with a peak unity current gain cutoff frequency (f/sub T/) of 130 GHz and a maximum frequency of oscillation (f/sub MAX/) of 130 GHz. The fourth-order bandpass /spl Delta//spl Sigma/ modulator consists of two bandpass resonators that can be tuned to optimize both wide-band and narrow-band operation. The IF is tunable from 140 to 210 MHz in this /spl Delta//spl Sigma/ modulator for use in multiple platform applications. Operating from /spl plusmn/5-V power supplies, the fabricated fourth-order /spl Delta//spl Sigma/ modulator sampling at 4 GSPS demonstrates stable behavior and achieves a signal-to-(noise + distortion) ratio (SNDR) of 78 dB at 1 MHz BW and 50 dB at 60 MHz BW. The average SNDR performance measured on over 250 parts is 72.5 dB at 1 MHz BW and 47.7 dB at 60 MHz BW.     

Tunable continuous-time bandpass /spl Sigma//spl Delta/ modulators with fractional delays

An analytical design methodology for continuous-time (CT) bandpass (BP) /spl Sigma//spl Delta/ modulators is presented. Second- and fourth-order tunable continuous time BP /spl Sigma//spl Delta/ modulator design equations are presented. A novel /spl Sigma//spl Delta/ loop architecture, where the traditional CT BP loop filter function is replaced with the filter function with fractional delays, is proposed. Validity of the methodology is confirmed by mixed-signal behavioral simulations.     

A time-interleaved continuous-time /spl Delta//spl Sigma/ modulator with 20-MHz signal bandwidth

This paper presents the first implementation results for a time-interleaved continuous-time /spl Delta//spl Sigma/ modulator. The derivation of the time-interleaved continuous-time /spl Delta//spl Sigma/ modulator from a discrete-time /spl Delta//spl Sigma/ modulator is presented. With various simplifications, the resulting modulator has only a single path of integrators, making it robust to DC offsets. A time-interleaved by 2 continuous-time third-order low-pass /spl Delta//spl Sigma/ modulator is designed in a 0.18-/spl mu/m CMOS technology with an oversampling ratio of 5 at sampling frequencies of 100 and 200 MHz. Experimental results show that a signal-to-noise-plus-distortion ratio (SNDR) of 57 dB and a dynamic range of 60 dB are obtained with an input bandwidth of 10 MHz, and an SNDR of 49 dB with a dynamic range of 55 dB is attained with an input bandwidth of 20 MHz. The power consumption is 101 and 103 mW, respectively.     

A 10.7-MHz self-calibrated switched-capacitor-based multibit second-order bandpass /spl Sigma//spl Delta/ modulator with on-chip switched buffer

A second-order multibit bandpass /spl Sigma//spl Delta/ modulator (BP/spl Sigma//spl Delta/M) used for the digitizing of AM/FM radio broadcasting signals at a 10.7-MHz IF is presented. The BP/spl Sigma//spl Delta/M is realized with switched-capacitor (SC) techniques and operates with a sampling frequency of 37.05 MHz. The input impulse current, required by the SC input branch, is minimized by the use of a switched buffer without deteriorating the overall system performance. The accuracy of the in-band noise shaping is ensured with two self-calibrating control systems. In a 0.18-/spl mu/m CMOS technology, the device die size is 1 mm/sup 2/ and the power consumption is 88 mW. In production, the BP/spl Sigma//spl Delta/M features at least 78-dB dynamic range and 72-dB peak SNR within a 200-kHz bandwidth (FM bandwidth). The intermodulation (IMD) is -65 dBc for two tones at -11 dBFS. The robustness of the aforementioned performance is demonstrated by the fact that it has been realized with the BP/spl Sigma//spl Delta/M embedded in the noisy on-chip environment of a complete mixed-signal FM receiver.     

Design of double-sampling /spl Sigma//spl Delta/ modulation A/D converters with bilinear integrators

Double-sampling techniques allow to double the sampling frequency of a switched capacitor /spl Sigma//spl Delta/ analog-to-digital convertors without increasing the clock frequency. Unfortunately, path mismatch between the double sampling branches may cause noise folding, which could ruin the modulator's performance. The fully floating double-sampling integrator is an interesting building block to be used in such a double sampling /spl Sigma//spl Delta/ modulator because its operation is tolerant to path mismatch. However, this circuit exhibits an undesired bilinear filter effect. This effectively increases the order of the modulator by one. Due to this, previously presented structures don't have enough freedom to fully control the modulator pole positions. In this paper, we introduce modified topologies for double-sampling /spl Sigma//spl Delta/ modulators built with bilinear integrators. We show that these architectures provide full control of the modulator pole positions and hence can be used to implement any noise transfer function. Additionally, analytical expressions are obtained for the residual folded noise.     

Hexagonal /spl Sigma//spl Delta/ modulators in power electronics

Design techniques for /spl Sigma//spl Delta/ modulators from communications are applied and adapted to improve the spectral characteristics of high frequency power electronic applications. A high frequency power electronic circuit can be regarded as a quantizer in an interpolative /spl Sigma//spl Delta/ modulator. We review one dimensional /spl Sigma//spl Delta/ modulators and then generalize to the hexagonal sigma-delta modulators that are appropriate to three-phase converters. A range of interpolative modulator designs from communications can then be generalized and applied to power electronic circuits. White noise spectral analysis of sigma-delta modulators is generalized and applied to analyze the designs so that the noise can be shaped to design requirements. Simulation results for an inverter show significant improvements in spectral performance.     

A vertically integrated tool for automated design of /spl Sigma//spl Delta/ modulators

We present a tool that starting from high-level specifications of switched-capacitor (SC) /spl Sigma//spl Delta/ modulators calculates optimum specifications for their building blocks and then optimum sizes for the block schematics. At both design levels, optimization is performed using statistical techniques to enable global design and innovative heuristics for increased computer efficiency as compared with conventional statistical optimization. The tool uses an equation-based approach at the modulator level, a simulation-based approach at the cell level, and incorporates an advanced /spl Sigma//spl Delta/ behavioral simulator for monitoring and design space exploration. We include measurements taken from two silicon prototypes: (1) a 16 b @ 16 kHz output rate second-order /spl Sigma//spl Delta/ modulator; and (2) a 17 b @ 40 kHz output rate fourth-order /spl Sigma//spl Delta/ modulator. Both use SC fully differential circuits and were designed using the proposed tool and manufactured in a 1.2 /spl mu/m CMOS double-metal double-poly technology.<>     

A 2-GS/s 3-bit /spl Delta//spl Sigma/-modulated DAC with tunable bandpass mismatch shaping

Direct digital synthesis of signals in the hundreds of megahertz can lead to simpler, smaller transceivers, free of images and LO feedthrough that plague systems requiring analog upconversion. We present a 3-bit, 2 GS/s, /spl Delta//spl Sigma/-modulated DAC in InP HBT technology. The DAC is linearized using bandpass mismatch shaping. The mismatch shaper uses seven tunable 1.5-bit discrete-time bandpass /spl Delta//spl Sigma/ modulators to dynamically route the digital signals to the DACs. These /spl Delta//spl Sigma/ modulators operate in the analog domain to decrease system complexity and power consumption. The mismatch-shaped DAC can generate narrowband signals between 250-750 MHz with >68 dB SNR in a 1-MHz bw, >74-dB SFDR, and <-80-dBc intermodulation distortion with an 8.1-W power consumption.     

Resonator-based multi-stage /spl Sigma//spl Delta/ modulator for wideband applications with improved dynamic range

A new design methodology for wideband, multi-stage, multi-bit /spl Sigma//spl Delta/ modulators (/spl Sigma//spl Delta/Ms) with improved dynamic range, is presented. The key to improving dynamic range is to have the first stage oscillated, then the coarse quantisation noise vanishes and hence circuit non-linearities do not cause a leakage quantisation noise problem. Based on the proposed methodology, a fourth-order four-bit /spl Sigma//spl Delta/M can achieve the dynamic range of 80 dB at the OSR of 8 without using additional calibration techniques.     

High-level synthesis of switched-capacitor, switched-current and continuous-time /spl Sigma//spl Delta/ modulators using SIMULINK-based time-domain behavioral models

This paper presents a high-level synthesis tool for /spl Sigma//spl Delta/ modulators (/spl Sigma//spl Delta/Ms) that combines an accurate SIMULINK-based time-domain behavioral simulator with a statistical optimization core. Three different circuit techniques for the modulator implementation are considered: switched-capacitor, switched-current and continuous-time. The behavioral models of these circuits, that take into account the most critical limiting factors, have been incorporated into the SIMULINK environment by using S-function blocks, which drastically increase the computational efficiency. The precision of these models has been validated by electrical simulations using HSPICE and experimental measurements from several silicon prototypes. The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for /spl Sigma//spl Delta/M synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, processing capabilities, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of /spl Sigma//spl Delta/Ms using both discrete-time and continuous-time circuit techniques.     

Sigma-delta (/spl Sigma//spl Delta/) quantization and finite frames

The K-level Sigma-Delta (/spl Sigma//spl Delta/) scheme with step size /spl delta/ is introduced as a technique for quantizing finite frame expansions for /spl Ropf//sup d/. Error estimates for various quantized frame expansions are derived, and, in particular, it is shown that /spl Sigma//spl Delta/ quantization of a unit-norm finite frame expansion in /spl Ropf//sup d/ achieves approximation error where N is the frame size, and the frame variation /spl sigma/(F,p) is a quantity which reflects the dependence of the /spl Sigma//spl Delta/ scheme on the frame. Here /spl par//spl middot//spl par/ is the d-dimensional Euclidean 2-norm. Lower bounds and refined upper bounds are derived for certain specific cases. As a direct consequence of these error bounds one is able to bound the mean squared error (MSE) by an order of 1/N/sup 2/. When dealing with sufficiently redundant frame expansions, this represents a significant improvement over classical pulse-code modulation (PCM) quantization, which only has MSE of order 1/N under certain nonrigorous statistical assumptions. /spl Sigma//spl Delta/ also achieves the optimal MSE order for PCM with consistent reconstruction.     

Numerical method for determining the quantization error PDF of single-bit /spl Sigma//spl Delta/ Modulators

Existing models for the quantizer of /spl Sigma//spl Delta/ modulators make assumptions on the probability density function (pdf) of the quantization error, or some other convenient signal of the modulator. In this paper, a method for the determination of this pdf for single-bit /spl Sigma//spl Delta/ modulators is presented. First, a numerical method is proposed in order to solve the simplified equation for the quantization error pdf for first-order systems considering noiseless and noisy dc input signals. Then, it is shown how most practical high-order (>2)/spl Sigma//spl Delta/ modulators, resulting from well-established design methods, can be modeled as first-order systems plus an additive noise source at the input. Hence, their quantization error pdf is analyzed using the proposed method. Simulation results are shown to be in considerable agreement with those of the proposed method.     

A fast block-based nonlinear decoding algorithm for /spl Sigma//spl Delta/ modulators

Previous work has established that the digital output of a /spl Sigma//spl Delta/ modulator as an A/D converter contains more information about the analog input than is extracted with conventional linear filtering. Under reasonable mathematical assumptions, optimal nonlinear decoding of the digital output can achieve significantly larger signal-to-noise ratios than linear filtering. However, the hitherto proposed decoding algorithms only demonstrate conceptual feasibility and are impractical from a computational point of view. We present a new block-based decoding algorithm that, like previous work, employs projections onto convex sets. The algorithm owes its speed to a change of projection norm, an accelerated convergence scheme, and a decimation-like subsampling; it is on the order of 10/sup 4/-10/sup 5/ times faster than one previously published algorithm for typical parameter values, and about 2-10 times slower than linear decoding. The new algorithm is applicable to all currently popular /spl Sigma//spl Delta/ architectures.<>