Experimental extraction of degradation parameters after constant voltage stress and substrate hot electron injection on ultrathin oxides

The impact of hot electrons on gate oxide degradation is studied by investigating devices under constant voltage stress and substrate hot electron injection in thin silicon dioxide (2.5–1.5 nm). The build-up defects measured using low voltage stress induced leakage current is reported. Based on these results, we propose to extract the critical parameter of the degradation under simultaneous tunnelling and substrate hot-electron stress. During a constant voltage stress the oxide field, the injected charge and the energy of carriers are imposed by V_G and cannot be studied independently. Substrate hot electron injection allows controlling the current density independent of the substrate bias and oxide voltage. The results provide an understanding for describing the reliability and the parameters dependence under combined substrate hot electron injection and constant voltage stress tunnelling.     

Modeling of the I–V characteristics of high-field stressed MOS structures using a Fowler–Nordheim-type tunneling expression

The gate current–voltage characteristic of a high-field stressed metal-oxide-semiconductor structure with trapped charge within the insulator barrier is consistent with a Fowler–Nordheim-type tunneling expression. Instead of considering a correction for the cathode electric field as usual, we use an effective local electric field that takes into account the distortion of the oxide conduction band profile caused by the trapped charge. An energy level at the injecting interface, introduced as an optimization parameter of the model, controls the tunneling distance used for calculating the effective field. Trap generation in the oxide is induced by high-field constant current stress and subsequent electron trapping at different injection levels is monitored by measuring the associated flat band voltage shift. The model applies for positive gate injection regardless the stress polarity and the involved parameters are obtained by fitting the experimental data without invoking any particular theoretical model for the trapping dynamics. In addition, it is shown how the presented model accounts for consistently both the current–voltage and voltage–current characteristics as a function of the injected charge through the oxide.     

Origin of positive charge generated in thin SiO2 filmsduring high-field electrical stress

The characteristics of electron capture in a 131-Å silicon dioxide after hot-hole injection have been studied, which have been compared with those after high-field Fowler-Nordheim (FN) electron injection. After hole injection from the silicon substrate into the oxide, positive charges accumulated in the oxide and electrons could be captured even at low oxide fields only under the positive gate polarity. The charge centroid of the captured electrons was near the substrate-SiO ₂ interface. The low-field electron capture can be explained based on the electron tunneling from the substrate into the positive charge and neutral trap centers created near the substrate-SiO₂ interface. In order to investigate the initial stage of the oxide degradation due to high-field FN stress, electrons were injected from the gate and the charge fluence was selected to be -1.0 C/cm². After the high-field stress, positive charges appeared in the oxide and electrons were captured only under the positive gate polarity by the positive charge and neutral trap centers, which were distributed near the interface. These facts are explained on the basis of the model describing that hole injection and trapping are the dominant causes for the generation of the positive charge centers during high-field FN stress     

Degradation of short-channel MOSFET's under constant current stress across gate and drain

We have employed a technique of constant current stress between the gate and drain of a MOS transistor to study the degradation of the threshold voltage, transconductance, and substrate current characteristics of the transistor. From the transistor characteristics, we propose that the degradation mechanism is a combined effect of trapping of holes in the gate oxide created by impact ionization due to the high electric field (> 8 MV/cm) across the oxide, and electron trapping phenomena. The degradation characteristics of the transistor under this constant current stress are quite similar to that observed normally due to the injection of hot electrons in the gate oxide when the transistor is biased in "ON" condition and the gate and drain voltages are selected to produce maximum substrate current.     

Electrical properties of thin RF sputtered Ta2O5 films after constant current stress

Stress-induced leakage currents (SILCs) in thin Ta₂O₅ films after short- and long-term constant current stress (CCS) at both gate polarities at different levels of injected current were investigated. The behavior of the SILCs and the change of quasistatic C–V characteristics after the degradation confirmed the variations of gate voltage with time during CCS necessary to maintain the injected current density through the oxide.The conduction mechanisms were also investigated. Initially, normal Poole–Frenkel (PF) mechanism dominates in the oxide at medium fields (0.4– 1.7 MV/cm) independently of the deposition temperature or annealing steps. After the degradation modified PF with different compensation factors appears. After long-term degradation conduction mechanism goes back to PF.     

超薄栅n-MOSFETs热载流子寿命预测模型

对氧化层厚度为 4和 5 nm的 n- MOSFETs进行了沟道热载流子应力加速寿命实验 ,研究了饱和漏电流在热载流子应力下的退化 .在饱和漏电流退化特性的基础上提出了电子流量模型 ,此模型适用于氧化层厚度为 4— 5 nm或更薄的器件     

Determination of the Fowler-Nordheim tunneling barrier from nitride to oxide in oxide:nitride dual dielectric

Using a simple but novel method of analysis, the voltage drop across the oxide (pad-oxide) in the oxide:nitride dual dielectric is determined for both positive and negative gate polarities. From the Fowler-Nordheim plot of the oxide voltage drop, the electron barrier from nitride to oxide is 3.2 ± 0.2 eV. However, the current injection from the nitride electrode is about 7 orders of magnitude lower than the current injection from the silicon electrode under the same oxide field values. This large field-current difference between the two directions of electron injection is consistent with the large difference observed in the J ★ t (charge fluence to breakdown) data.     

Degradation of electron irradiated MOS capacitors

We have investigated the degradation of MOS structure due to high energy electron irradiation as a function of radiation dose and gate bias applied during the irradiation. Devices have been characterized by current–voltage measurements, in order to study charge accumulation also at the gate interface. Three types of oxide charge have been observed: the unstable positive charge, due to trapped holes induced by the electron irradiation; the negative charge in the oxide bulk, deriving from capture of electrons injected during electrical measurements in radiation generated traps; and border traps, at both oxide interfaces.     

Effects of the metal gate on the stress-induced traps in Ta2O5/SiO2 stacks

The degradation of Ta₂O₅-based (10 nm) stacked capacitors with different top electrodes, (Al, W, Au) under constant current stress has been investigated. The variation of electrical characteristics after the stress is addressed to gate-induced defects rather than to poor-oxidation related defects. The main wearout parameter in Ta₂O₅ stacks is bulk-related and a generation only of bulk traps giving rise to oxide charge is observed. The post-stress current–voltage curves reveal that stress-induced leakage current (SILC) mode occurs in all capacitors and the characteristics of pre-existing traps define the stress response. The results are discussed in terms of simultaneous action of two competing processes: negative charge trapping in pre-existing electron traps and stress-induced positive charge generation, and the domination of one of them in dependence on both the stress level and the gate used. The charge build-up and the trapping/detrapping processes modify the dominant conduction mechanism and the gate-induced defects are precursors for device degradation. It is concluded that the impact of the metal gate on the ultimate reliability of high-k stacked capacitors should be strongly considered.     

Effects of electrical stressing in power VDMOSFETs

The effects of gate bias stressing on threshold voltage and mobility in power VDMOSFETs and underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed in terms of the mechanisms responsible. It is shown that gate bias stressing causes significant threshold voltage shift and mobility degradation in power VDMOSFETs; the negative bias stressing causes more rapid initial changes of both threshold voltage and mobility, but the final threshold voltage shift and mobility reduction are significantly larger in devices stressed by positive gate bias. In the case of positive bias stressing, electron tunnelling from neutral oxide traps associated with trivalent silicon defects into the oxide conduction band is proposed as the main mechanism responsible for positive oxide-trapped charge buildup, while subsequent hole tunnelling from the charged oxide traps to interface-trap precursors Si_s–H is shown to be the dominant mechanism responsible for the interface trap buildup. In the case of negative bias stressing, hole tunnelling from the silicon valence band to oxygen vacancy defects is shown to be responsible for positive oxide-trapped charge buildup, while subsequent electro-chemical reactions of interfacial precursors Si_s–H with the charged oxide traps and H⁺ ions are proposed to be responsible for interface trap buildup.     

Effects of high field stresses on threshold voltage of CMOS transistors

In this paper, the threshold voltage instabilities of CMOS transistors under gate bias stress at high gate oxide electric fields have been investigated. It is shown that in presence of the negative gate bias stress threshold voltage of n-channel MOSTs decreases, while threshold voltage of p-channel MOSTs increases. These results are explained by positive fixed oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps. On the other hand, it is shown that in the presence of the positive gate bias stress threshold voltage of n-channel MOSTs decreases at the beginning as well, but after a certain time period starts to increase, while threshold voltage of p-channel MOSTs continuously increases. The initial threshold voltage behaviour is explained by positive fixed oxide charge increase as well; however, in this case it is caused by the electron tunneling from oxide electron traps into oxide conduction band. The later threshold voltage increase of n-channel MOSTs is explained by surface state charge increase due to tunnel current flowing through the oxide.     

Definition of curve fitting parameter to study tunneling and trapping of electrons in Si/ultra-thin SiO2/metal structures

The tunneling of electrons through metal–oxide–silicon (MOS) structures with ultra-thin oxide is modeled using a linear model for the electron potential energy, an approach which simplifies the computation of both the interface potential and the field penetration distance in the substrate. The one-particle quantum problem is split into finding the metastable states induced by the internal field penetration in the substrate and the running states in the gate region. The two states are assumed to be connected by the condition for the continuity of the probability density at the substrate–dielectric interface. The electron probability current and the total gate current density are obtained for different gate voltages. As the model yields excellent fittings with experimental current–voltage (I–V) data for MOS structures, it was further applied to constant current stressing analysis in order to obtain values for important electron trapping parameters in the oxide. The resultant estimates of the electron trapping cross-section fall in the range of other independent determinations in the literature.     

1.2kV SiC MOSFET器件URS应力退化机理研究

本文首次研究了1.2kV碳化硅(Silicon Carbide,SiC)MOSFET在非钳位重复应力(Unclamped Repetitive Stress,URS)应力下的退化现象,并通过软件仿真和电荷泵测试技术对该现象进行了深入的分析.研究结果表明:URS应力会使得器件积累区由于碰撞电离产生大量的电子空穴对,其中的热空穴将在电场的作用下注入到氧化层中,使氧化层中出现许多空间正电荷,这些空间正电荷的存在使得器件的导通电阻与阈值电压出现下降,关态漏电流出现上升.     

Charge pumping spectroscopy: HfSiON defect study after substrate hot electron injection

Spectroscopic charge pumping (CP) is used to study the evolution of the energy distribution of trapped electrons within HfSiON/SiO₂ gate stacks under substrate hot electron injection (SHEI). Base level CP measurements with large pulse amplitude allow an efficient charging/discharging of traps and reaching two defect bands in the HfSiON situated at 0.40 and 0.85 eV above the Si conduction band, respectively. Unlike standard constant voltage stress (CVS), SHEI enables full control of the stress by separately controlling the applied gate field, the injected electron energy, and the fluence. During CVS, HfSiON defects at 0.40 eV are generated. Conversely, during SHEI, either the shallow or the deep defects are preferentially created depending on the gate field as well as electron energy.     

SILC dynamics in MOS structures subject to periodic stress

This work investigates stress-induced leakage current (SILC) in thin-oxide MOS capacitors subject to (quasiperiodic) ac voltage stress, under the condition of fixed charge fluence through the oxide. It shows that both trap creation and spontaneous trap annealing play a significant role when the duration of, and the time between, high-voltage pulses are comparable with characteristic times of trap dynamics. A phenomenological model is introduced that is able to accurately represent the main physical phenomena due to pulsed voltage stress under conditions of interest for unconventional programming schemes for fast programming nonvolatile memories (NVMs) with acceptable oxide degradation.     

Investigation on hot-carrier-induced degradation of SOI NLIGBT

The hot-carrier-induced (HCI) degradations of silicon-on-insulator (SOI) lateral insulated gate N-type bipolar transistor (NLIGBT) are investigated in detail by DC voltage stress experiment, TCAD simulation and charge pumping test. The substrate current I_sub and on-state resistance Ron at different voltage stress conditions are measured to assess the HCI effect on device performance. The electric field and impact ionization rate are simulated to assist in providing better physical insights. And charge pumping current is measured to determinate the front-gate interface states density directly. The degradation mechanisms under different gate voltage stress conditions are then presented and summarized.     

热载流子应力下p-MOSFETs在低栅电压范围的统一退化模型

研究了低栅电压范围的热载流子统一退化模型.发现对于厚氧化层的p-MOSFETs主要退化机制随应力电压变化而变化,随着栅电压降低,退化机制由氧化层俘获向界面态产生转变,而薄氧化层没有这种情况,始终是界面态产生;此外退化因子与应力电压成线性关系.最后得出了不同厚度的p-MOSFETs的统一退化模型,对于厚氧化层,退化由电子流量和栅电流的乘积决定,对于薄氧化层,退化由电子流量决定.     

热载流子应力下p-MOSFETs在低栅电压范围的统一退化模型

研究了低栅电压范围的热载流子统一退化模型.发现对于厚氧化层的p-MOSFETs主要退化机制随应力电压变化而变化,随着栅电压降低,退化机制由氧化层俘获向界面态产生转变,而薄氧化层没有这种情况,始终是界面态产生;此外退化因子与应力电压成线性关系.最后得出了不同厚度的p-MOSFETs的统一退化模型,对于厚氧化层,退化由电子流量和栅电流的乘积决定,对于薄氧化层,退化由电子流量决定.     

A lifetime prediction method for hot-carrier degradation insurface-channel p-MOS devices

Hot carrier degradation of p-MOS devices at low gate voltages (V_g<V_d) is examined. It is shown that the electronic gate current is the principal factor in stress damage in this gate voltage range and that the damage itself consists of trapped electrons, localized close to the drain junction. The saturation of the transconductance change as a function of time which is seen at long stress times of high stress voltages results from a change in the injected gate current as a function of time. This is caused by changes in electric field in the silicon due to charge trapping in the oxide during stress. The saturation effect can, however, be transformed into a simple power law if the time axis is multiplied by the square of the instantaneous gate current. This allows for the development of a lifetime-prediction method. The method is applied to 1.0-μm p-MOS devices, and a lifetime is estimated     

Probing stress effects in HfO2 gate stacks with time dependent measurements

Effects of constant voltage stress (CVS) on gate stacks consisting of an ALD HfO₂ dielectric with various interfacial layers were studied with time dependent sensing measurements: DC I–V, pulse I–V, and charge pumping (CP) at different frequencies. The process of injected electron trapping/de-trapping on pre-existing defects in the bulk of the high-κ film was found to constitute the major contribution to the time dependence of the threshold voltage (V_t) shift during stress. The trap generation observed with the low frequency CP measurements is suggested to occur within the interfacial oxide layer or the interfacial layer/high-κ interface, with only a minor effect on V_t.