在线色度分析仪的设计应用

针对业主要求实现在线色度检测的需要,通过选用合适的在线色度仪组成实时色度测量系统,并综合考虑在线色度测量系统的供电、仪表安装、使用环境等设计要素,实现了业主将不合格产品用泵打入处理罐,人工加入吸附剂调节产品性质,在保持介质循环前提下,根据色度仪的实时检测数据,人工判别产品是否合格,在产品合格后将合格产品打入产品罐的目的。     

Monitoring machine based synthesis technique for concurrent error detection in finite state machines

This paper discusses a new design methodology for concurrent error detection in synchronous sequential circuits based on the use of monitoring machines. In this approach, an auxiliary sequential circuit, called the monitoring machine, operates in lock-step with the main machine, such that any fault in either of the two machines is immediately detected. This methodology is independent of the fault model. It can be applied to FSMs with pre-encoded states and can also be used for ones being synthesised. It also provides a systematic framework for the combined optimisation of the main and monitoring machines, and for exploring tradeoffs in their implementation. The design of monitored sequential circuits is a two-fold problem; namely one of designing an optimal monitoring machine given the main machine, and the other of encoding the main machine states so that the resulting monitoring machine is minimal. This paper formally discusses the design of both the main and monitoring machines and techniques for their combined optimisation. Tradeoffs in their implementation based on selective fault detection are also examined. Through experimental results, it is shown that the proposed synthesis technique is eminently suitable for the design of low-cost sequential circuits with concurrent error detection. The monitoring machine is less costly than the main machine. It is also not identical to it. As a result, a monitored sequential circuit has significantly lower hardware cost and improved fault coverage than previous implementations. Presently at Texas Instruments (India) Ltd., Bangalore, India.     

12位A/D转换器ADS7864在电网谐波分析仪中的应用

ADS7864是Burr-Brown公司开发的12位6通道A/D转换器,介绍了ADS7864的工作原理、内部结构、工作模式及编程要点,给出了ADS7864在电网谐波分析仪中与数字信号处理器TMS320F206的接口应用实例,并且对DSP与A/D转换器的接口特点进行了总结.     

一个高效的门限共享验证签名方案及其应用

基于离散对数问题提出一个新的门限共享验证签名方案，该方案是EIGamal签名方案和Shamir门限方案的结合。在该方案中，n个验证者中任意t个可以验证签名的有效性，而t-1个或更少的验证者不能验证签名的有效性。伪造该方案的签名等价于伪造EIGamal签名。与已有方案相比，该方案的签名效率更高。最后基于该门限共享验证签名方案提出一个新的口令共享认证方案。     

A quasi-optimal scheduling of intermediate signatures for multiple signature analysis compaction testing schemes

In this article, a strategy based on the use of intermediate signatures is proposed that enables the exact fault coverage of compact testing schemes to be determined in a feasible computation time. Two models to predict fault simulation time, a fault simulator dependent and independent model, are developed and used by a dynamic programming based algorithm to find the optimal scheduling of the signatures with respect to the total simulation time. Simulation results for both models are then presented demonstrating the feasibility of the proposed strategy.This work was supported in part by grants from the Natural Sciences and Engineering Research Council (NSERC) of Canada, the Canadian Microelectronics Corporation (CMC) and the British Columbia Advanced Systems Institute (B.C. A.S.I.).     

Hardware reduction in continuous checksum-based analog checkers: Algorithm and its analysis

Fault-tolerant design of analog circuits is more difficult than that of digital circuits. Chatterjee has proposed a continuous checksum-based technique to design fault-tolerant linear analog circuits. However, hardware overhead of the embedded checker is an important issue in this technique, which has never been addressed before. This paper proposes an algorithm for reduction of hardware overhead in the checker. Without changing the original circuit, the proposed algorithm can not only reduce the number of passive elements, but also the number of analog operators so that the error detection circuitry in the checker has optimal hardware overhead. As the basis of the algorithm, a serial of theoretic results, including the concept and existence conditions of all-non-zero solutions, have also been presented to verify the algorithm.     

A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores

We have introduced a low-cost at-speed BIST architecture that enables conventional microprocessors and DSP cores to test their functional blocks and embedded SRAMs in system-on-a-chip architectures using their existing hardware and software resources. To accommodate our proposed new test methodology, minor modifications should be applied to base processor within its test phase. That is, we modify the controller to interpret some of the instructions differently only within the initial test mode. In this paper, we have proposed a fuctional self-test methodology that is deterministic in nature. In our proposed architecture, a self test program called BIST Program is stored in an embedded ROM as a vehicle for applying tests. We first start with testing processor core using our proposed architedture. Once the testing of the processor core is completed, this core is used to test the embedded SRAMs. A test algorithm which utilizes a mixture of existing memory testing techniques and covers all important memory faults is presented in this paper. The proposed memory test algorithm covers 100% of the faults under the fault model plus a data retention test. The hardware overhead in the proposed architecture is shown to be negligible. This architecture is implemented on UTS-DSP (University of Tehran and Iran Communicaton Industries (SAMA)) IC which has been designed in VLSI Circuits and Systems Laboratory.     

A methodology for the design of SFS/SCD circuits for a class of unordered codes

We present two design methods that produce concurrently testable and cascadable combinational blocks for a given logic function. In the first method, the designed block is strongly fault-secure and code-disjoint. Any unordered coding scheme can be used for the input and output. The second method produces designs that are strongly fault-secure and strongly code-disjoint. Here the encoding requires some simple density properties that are seen to be satisfied by the commonly used coding schemes. This makes the method applicable to a larger class of coding schemes than the existing methods. We also show that our designs have lower hardware overhead.     

Design of Self-Testing Checkers for m-out-of-n Codes Using Parallel Counters

This paper extends the design method of self-testing checkers (STCs) for some m-out-of-n (m/n) codes, proposed recently in IEEE Trans. Comput., 1995 by Dimakopoulos et al. The checkers are built using a pair of parallel counters (composed of full-adders and half-adders) with a total of n inputs and a 2-rail STC. We show here how to build this type of checkers for a number of m/n codes for which previous methods failed.     

A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs

In this paper a new circuit for concurrent soft and timing error detection in CMOS ICs is presented. The circuit is based on current mode sense amplifier topologies to provide fast error detection times. After an error has been detected it can be corrected by using a retry cycle.     

一种低复杂实现框架及在多码元差分检测中的应用

本文基于信息论考虑提出了一种低复杂实现的框架,对最大似然序列检测的分组（block)检测结构分析了该低复杂实现方案的性能并提出两命题,可用于寻求低复杂实现算法,另外,我们将该低复杂实现框架成功应用于高斯白声信道及衰落信道下多码元差分检测（MSDDD,multi-symbol differential detection)的低复杂实现,在基本保持其的条件下实现了检测复杂度多码元观察长度的线性增长,而最佳MSDD复杂度呈指数增工。     

A Wavelet Packet Algorithm for Classification and Detection of Moving Vehicles

In this paper we propose a robustalgorithm that solves two related problems: 1) Classificationof acoustic signals emitted by different moving vehicles. Therecorded signals have to be assigned to pre-existing categoriesindependently from the recording surrounding conditions. 2) Detectionof the presence of a vehicle in a certain class via analysisof its acoustic signature against the existing database of recordedand processed acoustic signals. To achieve this detection withpractically no false alarms we construct the acoustic signatureof a certain vehicle using the distribution of the energies amongblocks which consist of wavelet packet coefficients. We allowno false alarms in the detection even under severe conditions;for example when the acoustic recording of target object is asuperposition of the acoustics emitted from other vehicles thatbelong to other classes. The proposed algorithm is robust evenunder severe noise and a range of rough surrounding conditions.This technology, which has many algorithmic variations, can beused to solve a wide range of classification and detection problemswhich are based on acoustic processing which are not relatedto vehicles. These have numerous applications.     

一种可分类数据的聚类算法及其应用

文章给出了一种新颖、高效的用于可分类数据的聚类算法－WeiSC，该算法具有好的精确性，适合大规模数据库中数据的聚类。通过理论推导和实验，证明了算法的正确性和有效性，并结合入侵检测中操作行为的识别，给出了该算法的一个应用实例。     

高约束度卷积码的一种译码方法及其性能

本文提出了高约束度卷积码的一种新的译码方法──状态扩展（ＳＳＤ）方法。该方法先将译码状态扩展一倍，再用最大似然维特比译码原理进行译码，目的是通过增加储存量来减少运算量。ＳＳＤ方法度量值迭代简单，判决输出方便。文中以约束度分别为Ｋ＝７和Ｋ＝９的两种卷积码为例，讨论ＳＳＤ译码方法、性能及用ＤＳＰ器件的实现问题，并得出了几个结论。     

卫星移动通信信道LR2模型及系统性能分析

在对卫星移动通信信道传播特性进行分析的基础上,综合目前提出的各种卫星移动信道传播模型,提出了一种新的Lognormal—Rice—Rayleigh模型(简称LR^2模型)。从该模型可以推导到其它各种经典的卫星移动信道传播模型,并且具有良好的全波段特性(从UHF到Ka)和实际逼真度。还给出了LR^2模型从UHF到Ka各个波段的仿真效果和参数优化公式,全面分析了与信道模型有关的各种参数如电平通过率(LCR)、平均衰落时长(AFD)、相位分布、误码率、块差错率等,为信道模型的应用作了较全面的阐述。     

高维空间下求解MDA的扰动算法及其在人脸识别中的应用

本文提出了一种在高维空间下直接求MDA(Multiple discriminant analysis)最佳解的扰动算法，并把这一算法应用于人脸的识别中。在传统的MDA求解算法中，一般要求训练样本的个数足够大，以至于其类内散射矩阵为非奇异矩阵，即所谓的“小样本”问题。但是，在入脸识别中，由于人脸空间的维数非常大，而训练样本的个数有限，造成类内散射矩阵为奇异矩阵，从而使得用传统的求解方法失效。为了能在高维空间中求出MDA的最佳解，本文采用扰动的思想，巧妙地避开了矩阵的奇异性问题并找到了最佳变换矩阵。此外，把这一算法用于人脸的识别中，对ORL人脸图像库的实验显示，采用本文提出的算法达到比较低的错误率，其错误率仅为特征脸(Eigenface)方法的49．9％，为Fisher脸(Fisherface)的7914％。     

Short test procedures for R-2R D/A converters by electrical modeling and application of the ambiguity algorithm

A reduced physical model of the integral non-linearity error in high resolution R-2R D/A converters is obtained by circuit analysis and application of the ambiguity algorithm. Its relationships with the well establisheda priori model based on Rademacher functions is discussed. Experiments, carried out on a sample of commercial 12 bit converters, demonstrate that functional test programs based on this model achieve shorter test times and lower prediction errors than those based on larger models obtained by straight QR factorization.     

MEI系数的快速算法

不变性测试方程法已被证明是解决电磁问题的一种有效方法。目前电大尺寸问题中ＭＥＩ系数的计算已成为一个瓶颈。提出了一个快速算法用于加速ＭＥＩ系数的计算,它使用快速多极子方法计算测试子的散射场,使得ＭＥＩ系数的计算速度从Ｏ（Ｎ＾２）变为Ｏ（Ｎ＾１．５Ｌｏｇ２Ｎ）。