高频电子电路中的耦合系数及耦合电容

在高频电路中,有时用到电容耦合回路,其调谐特性和频率特性与耦合系数直接相关.因此,耦合系数的确定与耦合电容的选择是该电路设计中的一个重要问题.在现有高频电路教材中,一般对电容耦合回路耦合系数的确定与耦合电容的选择这一重要问题未作深入讨论.为此,本文归纳总结了电容耦合回路设计中,耦合系数的确定与耦合电容的选择这个重要问题.     

液晶介电常数对耦合电容的影响

采用2DMOS模拟软件对数据线与其相邻像素电极所构成的耦合电容Cpd进行了模拟,重点研究了介电常数对数据线左右侧的耦合电容Cpd的影响机理及趋势.通过模拟得出:数据线左侧的耦合电容Cpd主要受液晶层间的电场力影响,数据线右侧的耦合电容Cpd主要受到耦合电容Cpd间的电场力影响,而总耦合电容Cpd中占主要部分的是右侧耦合电容Cpd,因此可通过降低右侧耦合电容Cpd的方法来降低总耦合电容Cpd.     

FDTD法研究散热片与器件间的耦合电容

散热片与器件间的电容耦合是电路产生共模辐射的主要原因之一，其对研究电路的辐射发射特别重要。然而长期以来人们将该电容简化为平板电容，采用静电场推导的电容公式计算。但在高频端，散热片和器件的尺寸与波长相比拟，分布参数影响了该耦合电容的数值。所以本文提出了采用FDTD法计算散热片与器件间的高频耦合电容的构想。数值计算的结果表明：该电容已经不能看作是一简单常数，而是随频率变化的量。频率较低时，耦合电容随频率升高快速减小。且耦合电容具有频率选择性。激励源位于散热片的中心耦合电容小；绝缘层厚度越薄，相对介电常数越大得到的高频耦合电容越大，但不是线性变化。在实际散热片的选择和安装过程前必须对其产生的耦合电容进行预测，以期在最实用的条件下得到最小的耦合电容。     

能量回收电容耦合逻辑及其综合方法

提出了一种新型能量回收电路ERCCL(能量回收电容耦合逻辑),该电路的能耗低于传统CMOS电路及其他能量回收电路.ERCCL利用电容耦合进行逻辑求值,因此可以在一个门中低能耗地实现高扇入、高复杂度的逻辑.同时ERCCL是一种阈值逻辑.所以一个基于ERCCL的系统可以大大减少逻辑门数,从而降低系统能耗.针对ERCCL提出了一种阈值逻辑综合方法.用基准电路集MCNC做了相应的实验.与SIS的综合结果相比,该方法大约减少80%的逻辑门.     

能量回收电容耦合逻辑及其综合方法

提出了一种新型能量回收电路ERCCL（能量回收电容耦合逻辑）,该电路的能耗低于传统CMOS电路及其他能量回收电路．ERCCL利用电容耦合进行逻辑求值,因此可以在一个门中低能耗地实现高扇入、高复杂度的逻辑．同时ERCCL是一种阈值逻辑．所以一个基于ERCCL的系统可以大大减少逻辑门数,从而降低系统能耗．针对ERCCL提出了一种阈值逻辑综合方法．用基准电路集MCNC做了相应的实验．与SIS的综合结果相比,该方法大约减少80％的逻辑门．     

电容耦合单电子晶体管有源负载

本文基于单电子隧道效应的半经典模型,由电容耦合单电子晶体管的本征,电流电压特征出发,研究了在各种组态下,电容耦合单电子晶体管有源负载的本征电流－电压特征,讨论了它们的交流小信号等效电路,所得到的结论对于单电子模拟电路物设计具有指导意义。     

瓷介电容在广播电视信号传输处理电路中的应用经验

0 引言瓷介电容分为一类瓷介电容和二类瓷介电容,在广播电视电路中的应用范围包括一类(CG):谐振回路、高频耦合、高频放大器、低噪声电路、高频旁路以及要求低损耗、电容量高稳定和绝缘电阻高的电路,二类(X7R或X5R):电源滤波、旁路、低频耦合电路或对损耗和电容量稳定性要求不高的电路中。     

电容滤波电路工作波形的Multisim仿真分析

基于探索电容滤波电路工作波形仿真实验技术的目的,采用Multisim10仿真软件对电容滤波电路的工作波形进行了仿真实验测试,给出了Multisim仿真实验方案,仿真分析了滤波电容选取不同数值时电路工作波形、电路性能的变化情况。结论是仿真实验可直观形象地描述电容滤波电路的工作特性,有利于系统地研究电路的构成及电路元件参数的选择。     

基于"有效电容"的耦合RC互连延时分析

本文在保证互连延时特性不变的基础上将两相邻耦合RC互连中的耦合电容和静态互连电路等效为一“有效电容”,并将其用于有源互连的Elmore延时计算。与传统的采用Miller电容的方法进行了比较,它不但提高了计算精度而且反映了延时随信号上升时间变化的规律。本文方法与Elmore延时具有相同的计算复杂度,可广泛用于考虑耦合电容的面向性能的布线优化。     

电荷再分配DAC级间耦合电容值的优化设计

介绍了多级耦合结构高分辨率电荷再分配DAC级间耦合电容值的设计方法。重点讨论了如何根据寄生电容值,对耦合电容值进行优化。将该方法应用到一个16位电荷再分配逐次逼近A/D转换器的设计中。通过Cadence环境下的Spectre仿真工具进行仿真,验证了该方法的正确性。     

消除电容传感器寄生电容干扰的几种方法

电容传感器结构简单，分辨率高，但寄生电容的存在严重影响了其工作特性，文章分析了寄生电容存在的原因，采用驱动电缆技术、运算放大器驱动技术、整体屏蔽技术、集成组合技术可有效减小寄生电容，提高传感器的性能。     

Low-frequency capacitance measurements

The letter proposes a technique for the fast determination at extremely low frequencies of the capacitance and leakage components of capacitors. The proposed method permits the measurement of C and G in only a few cycles. An apparatus is described employing this technique for the automatic measurement of m.o.s. capacitance as a function of frequency and bias voltage.     

Junction capacitance switches

The design of junction capacitance switches consisting of a combination of abrupt junctions is considered. Theoretical characteristics are calculated for ideally abrupt junctions. The possibilities of fabrication by alloying and epitaxial growth are briefly discussed.     

Inductor winding capacitance cancellation using mutual capacitance concept for noise reduction application

In this paper, the properties of mutual capacitance between two capacitors are first discussed. It is found that the effects of mutual capacitance can be represented by two positive or negative capacitors across the two capacitors. These two equivalent capacitors can be used to cancel the parasitic capacitance of inductors. Because the mutual capacitance can be emulated using two small capacitors, the proposed method can easily be implemented in practical components. The prototypes are then built and the cancellation is verified using a network analyzer. Further EMI measurements in a practical power circuit prove that there is a significant improvement in the inductor's filtering performance.     

A basic capacitance switch

The use of a thin dielectric electron tunneling element along with basic conventional circuit elements is discussed. The circuits considered perform as a voltage-controlled capacitance switch, a voltage-controlled capacitance staircase generator, and a read only computer memory element.     

Tunnel-diode junction capacitance measurement

This paper describes a basic HF (as contrasted to VHF or microwave frequency) substitution technique for measurement of tunnel-diode junction capacitance. This technique was devised to solve the problem of series lead inductance errors resulting from the high conductance of these diodes and the resultant fractional Q's of their junction capacitances in the HF region. The paper also describes an extension of this technique which has made possible the determination of diode capacitances as low as 2 µµf in the negative resistance region for diodes having time constants<10^{-10}with an uncertainty of less than ±0.25 µµf.     

MIS capacitance and derivative of capacitance,with application to nonparabolic band semiconductors

Theoretical capacitance (C-V) and derivative of capacitance (C′-V) curves for an MIS structure with a semiconductor having a nonparabolic conduction band and a parabolic valence band are calculated for single level trap, uniform and nonuniform surface state distributions. The Kane model is used to describe the nonparabolic conduction band. The effects of varying the hole effective mass, Kane matrix element, temperature, surface state densities (both donor and acceptor types), and the degeneracy factors for the surface states is examined. The computed results are based on Hg_0·8Cd_0·2TeZnS device parameters.     

Parasitic capacitance of submicrometer MOSFET's

We systematically investigated the dependence of parasitic capacitance on gate length, gate electrode thickness, and gate oxide thickness using a 2-D device simulator. We showed that the model commonly used for parasitic capacitance is not accurate and also showed that more the rigorous model proposed by Kamchouchi should be used for submicrometer devices. Furthermore, we proposed a simple model that ensures the same accuracy as that of the Kamchouchi model     

Investigation of interconnect capacitance characterization usingcharge-based capacitance measurement (CBCM) technique andthree-dimensional simulation

This paper examines the recently introduced charge-based capacitance measurement (CBCM) technique through use of a three-dimensional (3-D) interconnect simulator. This method can be used in conjunction with simulation at early process development stages to provide designers with accurate parasitic interconnect capacitances. Metal to substrate, interwire, and interlayer capacitances are each discussed and overall close agreement is found between CBCM and 3-D simulation. Full process interconnect characterization is one possible application of this new compact, high-resolution test structure     

大容量MLCC的工艺设计

采用四层端电极(Ni/Cu/Ni/Sn)结构设计,底层为Ni,电镀Cu/Ni/Sn的工艺方法,制作了大容量MLCC。研究了四层结构和三层结构(Cu/Ni/Sn)对电容量等基本电性能、可靠性和内应力的影响。结果表明:制作1206规格10μFMLCC,C为9.86～10.46μF、tanδ为(360～390)×10–4、绝缘电阻≥1.5×108Ω、耐电压值为175～205V,四层结构与三层结构电性能相当。可靠性测试中,四层结构抗机械和热冲击能力提高了20%,且有利于瓷体内应力释放。