A CMOS pipelined single channel digital echo canceller

Recent advances in LSI/VLSI have made the integration of digital echo cancellers both feasible and economical. The design presented features a universal CMOS ALU which is capable of direct I/O with /spl mu/-law encoded data. The ALU is pipelined to achieve high processing speed with low power dissipation. Based on this /spl mu/-law ALU, a 128-tap CMOS pipelined single channel digital echo canceller was designed and simulated, and a prototype was built. Experimental results for a 4 kHz sampling rate are presented.     

A decision feedback equalizer with time-reversal structure

This work describes the use of a receiver with a time-reversal structure for low-complexity decision feedback equalization of slowly fading dispersive indoor radio channels. Time-reversal is done by storing each block of received signal samples in a buffer and reversing the sequential order of the signal samples in time prior to equalization. As a result, the equivalent channel impulse response as seen by the equalizer is a time-reverse of the actual channel impulse response. Selective time-reversal operation, therefore, allows a decision feedback equalizer (DFE) with a small number of forward filter taps to perform equally well for both minimum-phase and maximum-phase channel characteristics. The author evaluates the theoretical performance bounds for such a receiver and quantifies the possible performance improvement for discrete multipath channels with Rayleigh fading statistics. Two extreme cases of DFE examples are considered: an infinite-length DFE; and a DFE with a single forward filter tap. Optimum burst and symbol timing recovery is addressed and several practical schemes are suggested. Simulation results are presented. The combined use of equalization and diversity reception is considered     

A fast computation algorithm for the decision feedback equalizer

A novel fast algorithm for computing the minimum MSE decision feedback equalizer settings is proposed. The equalizer filters are computed indirectly, first by estimating the channel, and then by computing the coefficients in the frequency domain with the discrete Fourier transform (DFT). Approximating the correlation matrices by circulant matrices facilitates the whole computation with very small performance loss. The fractionally spaced equalizer settings are derived. The performance of the fast algorithm is evaluated through simulation. The effects of the channel estimation error and finite precision arithmetic are briefly analyzed. Results of simulation show the superiority of the proposed scheme     

A blind decision feedback equalizer incorporating fixed lagsmoothing

A new type of blind decision feedback equalizer (DFE) incorporating fixed lag smoothing is developed in this paper. The structure is motivated by the fact that if we make full use of the dependence of the observed data on a given transmitted symbol, delayed decisions may produce better estimates of that symbol. To this end, we use a hidden Markov model (HMM) suboptimal formulation that offers a good tradeoff between computational complexity and bit error rate (BER) performance. The proposed equalizer also provides estimates of the channel coefficients and operates adaptively (so that it can adapt to a fading channel for instance) by means of an online version of the expectation-maximization (EM) algorithm. The resulting equalizer structure takes the form of a linear feedback system including a quantizer, and hence, it is easily implemented. In fact, because of its feedback structure, the proposed equalizer shows some similarities with the well-known DFE. A full theoretical analysis of the initial version of the algorithm is not available, but a characterization of a simplified version is provided. We demonstrate that compared to the zero-forcing DFE (ZF-DFE), the algorithm yields many improvements. A large range of simulations on finite impulse response (FIR) channels and on typical fading GSM channel models illustrate the potential of the proposed equalizer     

A low-power 128-tap digital adaptive equalizer for broadband modems

This paper describes a modem receiver chip containing two 64-tap adaptive finite impulse response (FIR) filters configured in parallel as in-phase and quadrature-phase filters. Each filter has a span of 16 symbols and can be configured for T/2, T/3, or T/4 fractional spacing. A zero-latency pipeline technique is used that allows adaptive filters of arbitrary length without degrading the speed. Power is saved at the algorithmic, architectural, and circuit levels. The chip has support for dynamically tuning coefficient precision, updating rates and filter lengths to reduce power consumption. The chip was fabricated in 0.5-μm CMOS technology and consumes 535 mW of power when operating at 50 MHz with 128 taps, T/4 spacing, and symbol-rate power-of-two LMS updating. This can be further reduced to 280 mW using dynamic power reduction techniques. The power in the FIR filter is 162 mW with maximum precision converged coefficients which corresponds to 5.1 mW per multiply-accumulate operation     

Adaptive Bayesian decision feedback equalizer for dispersive mobileradio channels

The paper investigates adaptive equalization of time-dispersive mobile radio fading channels and develops a robust high performance Bayesian decision feedback equalizer (DFE). The characteristics and implementation aspects of this Bayesian DFE are analyzed, and its performance is compared with those of the conventional symbol or fractional spaced DFE and the maximum likelihood sequence estimator (MLSE). In terms of computational complexity, the adaptive Bayesian DFE is slightly more complex than the conventional DFE but is much simpler than the adaptive MLSE. In terms of error rate in symbol detection, the adaptive Bayesian DFE outperforms the conventional DFE dramatically. Moreover, for severely fading multipath channels, the adaptive MLSE exhibits significant degradation from the theoretical optimal performance and becomes inferior to the adaptive Bayesian DFE     

An LMS-based decision feedback equalizer for IS-136 receivers

In digital mobile communication systems, intersymbol interference is one of the main causes of degrading system performance. Decision feedback equalization (DFE) is the commonly used remedy for this problem. Since the channel is fast-varying, an adaptive algorithm possessing a fast convergence property is then required. The least mean square (LMS) algorithm is well known for its simplicity and robustness; however, its convergence is slow. As a consequence, the LMS algorithm is rarely considered in this application. In this paper, we consider an LMS-based DFE for the North American IS-136 system. We propose an extended multiple-training LMS algorithm accelerating the convergence process. The convergence properties of the multiple-training LMS algorithm are also analyzed. We prove that the multiple-training LMS algorithm can converge regardless of its initial value and derive closed-form expressions for the weight error vector power. We further take advantage of the IS-136 downlink slot format and divide a slot into two subslots. Bidirectional processing is then applied to each individual subslot. The proposed LMS-based DFE has a low computational complexity and is suitable for real-world implementation. Simulations with a 900-MHz carrier show that our algorithm can meet the 3% bit error rate requirement for mobile speeds up to 100 km/hr     

A systolic array realization of the adaptive decision feedback equalizer

This paper presents a systolic array architecture for the adaptive decision feedback equalizer. The design is based on an algebra developed earlier by Kung and Lin (Proceedings of the Conference of Elliptic Problem Solvers, Monterey, CA, January 1983; Research Report CMU-CS-84-100, Department of Computer Science, Carnegie-Mellon University, Pittsburgh, PA, April 1983.) and is largely made up of two basic processing cells that are computationally equivalent and simple to realize. To maintain accuracy of the algorithm, the array needs to be operated by a clock with a speed twice of that the input. The increase in clock speed can, however, be exploited to reduce the total number of adders and multipliers by about 50%.     

A nonlinear electrical equalizer with decision feedback for OOK optical communication systems

In this paper we introduce a nonlinear equalizer using the Radial Basis Function (RBF) network with decision feedback equalizer (DFE) for electronic dispersion compensation in optical communication systems with on-off-keying and a direct detection receiver. The RBF method introduces a non-linear equalization technique suitable for optical communication direct detection systems that include nonlinear transformation at the photodetector. A bit error rate performance comparison shows that the RBF with DFE out performs the RBF without DFE and achieves similar results provided by maximum likelihood sequence estimator.     

Fuzzy stochastic gradient decision feedback equalizer for VSBterrestrial HDTV broadcasting

We present a fuzzy stochastic gradient (FSG) decision feedback equalizer (DFE) for VSB terrestrial HDTV broadcasting. This equalizer employs a well-designed fuzzy Takagi-Sugeno (1985) model to automatically regulate the step size of the descent gradient vector, combining a fast convergence rate and a low excess mean square error (MSE). The only penalty paid is a slight increase in the computational complexity compared with the LMS algorithm. Simulation results show that this equalizer provides 3.5 dB signal-to-noise ratio (SNR) improvement at a BER of 3.0×10^-6 with respect to the conventional LMS DFE recommended by the Grand Alliance     

Frequency domain decision feedback equalizer for time-reversal space-time block coding

In this paper,a frequency domain decision feedback equalizer is proposed for single carrier transmission with time-reversal space-time block coding (TR-STBC).It is shown that the diagonal decision feed...     

A decision feedback recurrent neural equalizer as an infiniteimpulse response filter

An adaptive decision feedback recurrent neural equalizer (DFRNE), which models a kind of an IIR structure, is proposed. Its performance is compared with the traditional linear and nonlinear equalizers with FIR structures for various communication channels. The small size and high performance of the DFRNE makes it suitable for high-speed channel equalization     

An edge-based dual adaptive decision feedback equalizer for Gbps serial links

This paper presents an adaptive edge-DFE for 2PAM Gbps serial links. The optimal tap coefficients of the DFE are obtained by minimizing the jitter of received data. Reference voltage for generating DFE error signal is also obtained iteratively using an edge-DFE like algorithm. Issues critical to the proposed adaptive edge-DFE are examined in detail. The effectiveness of the proposed adaptive edge-DFE has been validated using a 5 Gbps serial link designed in a 65 nm 1.2 V CMOS technology. The effect of PVT (process, voltage, and temperature) variations on the performance of the proposed DFE has also been investigated. Simulation results demonstrate that the DFE is capable of opening completely closed data eyes when the DFE is absent. Equalized data have 55 % vertical-opening and 86.5 % horizontal eye-opening with 25 ns adaption time.     

A new configuration for echo canceller adaptable during double talkperiods

A three-port echo canceler (EC) configuration is proposed which observes the signal of the near-end side on a two-wire circuit in addition to the four-wire circuit signals. Embedding these signals on hybrid ports into a three-dimensional autoregressive process, echo path and innovations of near- and far-end speeches can be estimated through a three-channel lattice filter. The new configuration is then able to track echo path time variance, even during double talk (DT), and requires no changeover at either the beginning or end of DT, thus eliminating the need for DT detection. Two echo synthesizers utilizing inverse lattice and the echo path estimate possess guaranteed stability without the need for testing     

A 35 Mb/s mixed-signal decision-feedback equalizer for disk drivesin 2-μm CMOS

A 35 Mb/s mixed-signal adaptive decision-feedback equalizer (DFE) has been implemented in a 2-μm CMOS technology. The DFE has four feedback taps for cancelling intersymbol interference (ISI) and one tap for cancelling dc offset. The ISI is cancelled using fully differential analog circuits. Coefficient adaptation is digital, and two adaptation rates are available. The DFE occupies 24 mm² and dissipates 165 mW     

HBP: improvement in BP algorithm for an adaptive MLP decision feedback equalizer

Though the decision feedback equalizer (DFE) with multilayer perceptron (MLP) structure can be trained effectively by the backpropagation (BP) algorithm, it is always accompanied by the problem of local minimum. In order to solve some problems of the local minimum in the BP algorithm and to improve the performance of the BP algorithm under the same MLP structure, we combine the hierarchical approach and the BP algorithm to implement the MLP DFE, and we call the new scheme hierarchical BP (HBP) algorithm. Based on the hierarchical approach, from the input layer to the output layer of the MLP, every two layers of neural nodes (with one hidden layer) will be trained with an individual BP algorithm. Therefore, the entire MLP can be trained by several independent BP algorithms, unlike the standard BP algorithm, which utilizes only one BP algorithm to train the whole MLP structure. The results of performance evaluation indicate that the HBP algorithm not only strongly reduces the mean squared error but also yields a much lower bit-error rate than the standard BP algorithm does for equal computational cost and conditions.     

A resonant switch for LNA protection in watt-level CMOS transceivers

An integrated resonant switch designed to protect low-noise amplifier (LNA) circuits in CMOS transceivers is reported. The design implements the receive-path portion of a transmit/receive switch protecting 3-V-process transistors from 5 W (22-V peak) transmit signals while simultaneously helping to achieve a good LNA noise figure on receive and low power loss on transmit. Since the approach is to combine an LNA's matching network and switch functions, the design has no traditional insertion loss on receive. The effective loss to the transmitted signal is less than 0.5 dB using moderate quality inductors (Q>6) and 0.1 dB using Q=12 inductors achievable in most RF-aware CMOS silicon-on-insulator foundries at UHF through S-band frequencies.     

A 125-MHz mixed-signal echo canceller for Gigabit Ethernet oncopper wire

A discrete-time analog echo canceller is described that reduces the echo in the front end of Gigabit Ethernet twisted-pair interfaces. Echo cancellation in the analog domain by means of four taps reduces the complexity of the digital echo canceller and crosstalk cancellers. Designed in a 0.4-μm CMOS technology, the circuit employs an LMS algorithm to adapt to the cable length and impedance discontinuities, providing an echo suppression of 10 dB. The design operates at 125 MHz while consuming 43 mW from a 3-V supply     

A high-performance custom standard-cell CMOS equalizer for telecommunications applications

A high-performance CMOS programmable amplitude equalizer has been implemented with a dynamic range greater than 100 dB and supply rejection greater than 60 dB at 1 kHz from both supplies. This was accomplished using a balanced architecture. A nonreturn-to-zero sample-and-hold circuit is proposed that is also parasitic-insensitive. The circuits are implemented using a standard-cell methodology.