RF oscillator implementation using integrated CMOS surface acoustic wave resonators

This work is a proof of concept that a monolithic CMOS surface acoustic wave (SAW) resonator can function as an RF oscillator. The design of the oscillator includes the measurement characteristics of the CMOS SAW resonator, its matching networks, and RF amplifier is described. The integrated SAW resonator, with its operating frequency controlled by the spacing of its transducers was fabricated using a combination of CMOS plus post-CMOS processes. Based on the operation and performance of the SAW resonators, an equivalent circuit model of the CMOS SAW resonator was developed. A series resonant oscillator design was simulated using Microwave Office^TM. The designed matching network improves both the insertion losses and the phase slope of the resonator, while the RF amplifier provides sufficient gain to ensure oscillation. Measurements conducted on the RF-CMOS SAW oscillator demonstrated oscillation at 600 MHz.     

10 MHz CMOS OTA-C voltage-controlled quadrature oscillator

A quadrature-type voltage-controlled oscillator with operational transconductance amplifiers and capacitors (OTA-C) is presented. A monolithic integrated CMOS test circuit is introduced to verify theoretical results. The attainable frequency range of oscillation of the chip test circuit is 3-10.34 MHz. The total harmonic distortion (THD) is 0.20-1.87% for corresponding peak-to-peak amplitude voltages between 100 mV and 1 V. This amplitude can be controlled either by using a diode connection of two MOS transistors or a proposed nonlinear resistor.<>     

Digitally controlled oscillator

A monolithic integrated digitally controlled oscillator circuit is discussed. The oscillator has an output frequency range from 19.07 Hz to more than 20 MHz with a resolution of 19.07 Hz. It is fully linear over the complete control range with respect to the digital control word, has the long-term stability of a quartz oscillator, and the output clock edge uncertainty has a standard deviation of less than 0.5 ns. The circuit requires only a reference quartz as an external component. It operates from a single 5-V power supply, is fabricated in a 1.5-μm double-metal single-poly standard CMOS process, and requires an area of 4.1 mm²     

Current‐mode quadrature oscillator using current differencing transconductance amplifiers

This article presents a new electronically tunable single‐element‐controlled current‐mode quadrature sinusoidal oscillator circuit using current differencing transconductance amplifiers (CDTAs). The proposed oscillator is consisted of two CDTAs, two grounded capacitors and one grounded resistor, which is beneficial to monolithic integrated circuit implementation both in CMOS and bipolar technologies. The condition of oscillation and the frequency of oscillation are independently controllable. The frequency of oscillation can also be electronically controlled by adjusting the bias current of CDTA. The circuit provides four quadrature current outputs and two quadrature voltage outputs. The current output terminals possess high impedance level. PSPICE simulation results are used to verify the performance of the proposed circuit implemented at the transistor level. The measurement results support the computer simulations.     

基于背靠背PN变容管的低相位噪声LCVCO研究

研究了一种新型单片集成LC压控振荡器。该压控振荡器在传统的单端PN变容管电路结构基础上,通过对调谐电路进行改进,在保证调谐范围的前提下,有效地降低了相位噪声。压控振荡器使用高Q值螺旋电感,并采用SMIC0.18μm1P6M混合信号CMOS工艺实现。仿真结果表明,在调谐范围不变情形下,新型设计的VCO相位噪声比传统的改善了16.25dB@1kHz、8.08dB@100kHz。压控振荡器的中心频率1.8GHz,工作电压为1.8V,工作电流为3mA。     

An integrated CMOS micromechanical resonator high-Q oscillator

A completely monolithic high-Q oscillator, fabricated via a combined CMOS plus surface micromachining technology, is described, for which the oscillation frequency is controlled by a polysilicon micromechanical resonator with the intent of achieving high stability. The operation and performance of micromechanical resonators are modeled, with emphasis on circuit and noise modeling of multiport resonators. A series resonant oscillator design is discussed that utilizes a unique, gain-controllable transresistance sustaining amplifier. We show that in the absence of an automatic level control loop, the closed-loop, steady-state oscillation amplitude of this oscillator depends strongly upon the dc-bias voltage applied to the capacitively driven and sensed μresonator. Although the high-Q of the micromechanical resonator does contribute to improved oscillator stability, its limited power-handling ability outweighs the Q benefits and prevents this oscillator from achieving the high short-term stability normally expected of high-Q oscillators     

Recent progress of submicron CMOS using 6H-SiC for smart powerapplications

Silicon carbide (SiC) CMOS circuits have been developed recently to provide monolithic control for SiC MOS power switching devices. Although SiC CMOS is not well suited for high-end microprocessor applications, it must provide the necessary response time performance required for safe operation in high-voltage power switching applications. Despite previous developments in SiC CMOS process technology; which have enabled digital circuit operation using a 5 V power supply, circuit switching speeds were in the microsecond range. An obvious way to improve circuit performance is to scale device lateral and vertical dimensions. This paper describes recent progress in the development of a submicron, single metal, p-well CMBS process technology using 6H-SiC. Conventional NMOS transistors are fabricated with 0.5-mm (drawn) channel lengths and exhibit acceptable short-channel effects. Conventional PMOS transistors exhibit punchthrough at 0.8-mm channel lengths and require considerable channel engineering efforts which are also presented. Several digital logic gates and a ring oscillator have been fabricated with nanosecond gate switching performance. Performance limiting factors like parasitic series resistance is also investigated     

Chaotic synchronization using monolithic Chua oscillators†

This paper presents experimental evidence of the synchronization between two monolithic chaotic oscillators. These oscillators have been fabricated using g_m — C design techniques in a 2-4 μm double-poly n-well CMOS technology. The circuit realizes an oscillator from Chua's circuit family and features electrical control of the parameters in the piecewise-linear function and on-chip tuning of the oscillator natural frequencies. The area of the circuit including pads is 5 mm² and the power dissipation is less than l-8mW for a symmetrical biasing of ±2.5V.     

一种CMOS矩形波振荡器设计

振荡器是数字集成电路中常用的单元电路之一,为兼顾振荡频率和CMOS工艺集成,文中从电路结构着手,设计了一种CMOS矩形波振荡器。该振荡器采用标准CMOS电路,能够提供稳定的矩形波信号,信号输出频率和脉宽均可调节。     

Novel Miniature and Broadband Millimeter-Wave Monolithic Star Mixers

In this paper, three monolithic star mixers using a new miniature dual balun are proposed. The first one is a double spiral transformer mixer, and the second one is a trifilar transformer mixer. Both of these are fabricated using a commercial GaAs pseudomorphic HEMT process. The third is a 3-D transformer mixer, which is fabricated using a commercial CMOS process. These mixers exhibit bandwidths over 25-45 GHz (57%) with local oscillator isolations better than 20 dB. These star mixers are smaller than (lambda/6timeslambda/6) for the mixer core area. Compared with traditional star mixers, these mixers demonstrate 80% size reduction, and achieve good performance with the smallest chip size among all star mixers using monolithic microwave integrated circuit processes.     

无线局域网接收机用频率综合器的关键技术

对无线局域网接收机用锁相环型频率综合器的几项关键技术进行了研究.首先分析了锁相环型频率综合器的结构并提出了系统的主要参数.采用TSMC 0.18μm射频CMOS工艺设计了一个具有低相位噪声的单片LC调谐型压控振荡器.其在4.189GHz频点上4MHz频偏处所测得的相位噪声为-117dBc/Hz.采用TSMC 0.18μm混合信号CMOS工艺实现了具有低功耗的下变频模块电路.该电路在1.8V电源供电下可正常工作,功耗为13mW.     

45ps的超高速全耗尽CMOS/SOI环振

亚微米全耗尽 SOI( FDSOI) CMOS器件和电路经过工艺投片 ,取得良好的结果 ,其中工作电压为 5V时 ,0 .8μm全耗尽 CMOS/ SOI1 0 1级环振的单级延迟仅为 45ps;随着硅层厚度的减薄和沟道长度的缩小 ,电路速度得以提高 ,0 .8μm全耗尽 CMOS/ SOI环振比 0 .8μm部分耗尽 CMOS/ SOI环振快 30 % ,比 1 μm全耗尽 CMOS/ SOI环振速度提高 1 5% .     

一种具有省电模式CMOS振荡器电路

提出了一种适用于电源转换芯片的具有省电模式的CMOS振荡器电路,其特有的变频模式和间歇模式可以有效降低整个电源系统在轻载与空载时的功率损失,使得整个系统能随负载的变轻而线性降低开关频率,并在空载状态下进入间歇模式。基于SinoMOS1μm40V CMOS工艺,仿真和流片结果证明了该振荡器电路能够为电源转换系统芯片降低功耗提供所需要的功能,即根据负载情况自动调整PWM开关频率。     

一款用于LED驱动芯片的CMOS振荡器

研究一款适用于LED驱动芯片的CMOS振荡器电路.其工作原理是在环路振荡器中加入恒定电流源,以恒定电流对电容充电、MOS管对电容快速放电以产生锯齿波再经锁存器产生周期脉冲信号.与传统的环路振荡器相比,此电路的优点是振荡频率精确、波形稳定,振荡频率在一定的电源电压范围内对电源电压变化不敏感.此振荡器电路已经成功应用于一款LED驱动芯片中.     

A novel monolithic ultraviolet image sensor based on a standard CMOS process

We present a monolithic ultraviolet(UV) image sensor based on a standard CMOS process.A compact UV sensitive device structure is designed as a pixel for the image sensor.This UV image sensor consists of a CMOS pixel array,high-voltage switches,a readout circuit and a digital control circuit.A 16×16 image sensor prototype chip is implemented in a 0.18μm standard CMOS logic process.The pixel and image sensor were measured. Experimental results demonstrate that the image sensor has a high sensitivity of 0.072 V/(mJ/cm~2) and can capture a UV image.It is suitable for large-scale monolithic bio-medical and space applications.     

A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks

A fully CMOS integrated RF transceiver for ubiquitous sensor networks in sub-gigahertz industrial, scientific, and medical (ISM)-band applications is implemented and measured. The integrated circuit is fabricated in 0.18-mum CMOS technology and packaged in leadless plastic chip carrier (LPCC) package. The fully monolithic transceiver consists of a receiver, a transmitter, and an RF synthesizer with on-chip voltage-controlled oscillator. The chip fully complies with the IEEE 802.15.4 wireless personal area network in sub-gigahertz mode. The cascaded noise figure of the overall receiver is 9.5 dB and the overall transmitter achieves less than 6.3% error vector magnitude for 40 kb/s mode. The chip uses 1.8-V power supply and the power consumption is 25 mW for reception mode and 29 mW for transmission mode     

体硅热膜传感器单片集成工艺的研究

针对MEMS热膜式传感器的发展趋势和在实用化过程中存在的问题,提出了一种新型的单片电路和体硅MEMS热膜式传感器实现集成制造的嵌入式CMOS工艺技术,解决了MEMS制造工艺和CMOS集成电路工艺之间存在的兼容性问题。通过这种嵌入式CMOS工艺技术,可以实现具备最小体积、最低成本的MEMS器件。通过这种嵌入式热膜式传感器和CMOS处理电路的单片集成制造工艺,实现了一款热膜式传感器和IC放大电路的集成部件,并完成了相关基本电性能测试和传感器功能的演示验证,证明了设计的工艺路线的可行性。     

体硅衬底上的CMOS Fin FET

介绍了一种制作在普通体硅上的 CMOS Fin FET.除了拥有和原来 SOI上 Fin FET类似的 Fin FET结构 ,器件本身在硅衬底中还存在一个凹槽平面 MOSFET,同时该器件结构与传统的 CMOS工艺完全相容 ,并应用了自对准硅化物工艺 .实验中制作了多种应用该结构的 CMOS单管以及 CMOS反相器、环振电路 ,并包括常规的多晶硅和 W/Ti N金属两种栅电极 .分析了实际栅长为 110 nm的硅基 CMOS Fin FET的驱动电流和亚阈值特性 .反相器能正常工作并且在 Vd=3V下 2 0 1级 CMOS环振的最小延迟为 14 6 ps/门 .研究结果表明在未来 VL SI制作中应用该结构的可行性     

A 10-Gb/s CDR/DEMUX with LC delay line VCO in 0.18-/spl mu/m CMOS

A monolithic 10-Gb/s clock/data recovery and 1:2 demultiplexer are implemented in 0.18-/spl mu/m CMOS. The quadrature LC delay line oscillator has a tuning range of 125 MHz and a 60-MHz/V sensitivity to power supply pulling. The circuit meets SONET OC-192 jitter specifications with a measured jitter of 8 ps p-p when performing error-free recovery of PRBS 2/sup 31/-1 data. Clock and data recovery (CDR) is achieved at 10 Gb/s, demonstrating the feasibility of a half-rate early/late PD (with tri-state) based CDR on 0.18-/spl mu/m CMOS. The 1.9/spl times/1.5 mm/sup 2/ IC (not including output buffers) consumes 285 mW from a 1.8-V supply.     

A monolithic 5.9-GHz CMOS I/Q direct-down converter utilizing a quadrature coupler and transformer-coupled subharmonic mixers

We report the first monolithic 5.9-GHz CMOS I/Q direct-down converter by using a quadrature coupler and transformer-coupled subharmonic mixers (SHMs). Consuming 3.5mW, each SHM achieves a voltage gain of 10.8dB, 7.9-dBm IIP3, and 54-dBm IIP2. The input-referred dc-offset due to local oscillator self-mixing is -80.9dBm.