8英寸薄层硅外延片的均匀性控制方法

8英寸(1英寸=2.54 cm)薄层硅外延片的不均匀性是制约晶圆芯片良率水平的瓶颈之一.研究了硅外延工艺过程中影响薄外延层厚度和电阻率均匀性的关键因素,在保证不均匀性小于3％的前提下,外延层厚度和电阻率形成中间低、边缘略高的“碗状”分布可有效提高晶圆的良率水平.通过调整生长温度和氢气体积流量可实现外延层厚度的“碗状”分布,但调整温区幅度不得超过滑移线的温度门槛值.通过提高边缘温度来提高边缘10 mm和6 mm的电阻率,同时提高生长速率以提高边缘3 mm的电阻率,获得外延层电阻率的“碗状”分布,8英寸薄层硅外延片的的边缘离散现象得到明显改善,产品良率也有由原来的94％提升至98.5％,进一步提升了8英寸薄层硅外延片产业化良率水平.     

用于功率器件的P型厚高阻外延片

本文论述在常压ＣＶＤ硅外延系统中，通过ｅ＿ｑＰ＝Ｂ－Ａ／Ｔ，分别计算出ＳｉＨ－Ｃｌ＿３、ＰＣｌ＿３和ＢＣｌ＿３的Ａ和Ｂ二常数值。采用低温深冷工艺，进一步提高硅源的纯度，通过控制ＳｉＨＣｌ＿３的蒸汽压，在晶向为（１１１）和（１００），掺硼电阻率（４～８）×１０￣（－３）Ω·ｃｍ的抛光衬底硅片上，生长出外延层电阻率为３５０Ω·ｃｍ（杂质浓度３．５×１０￣（１３）／ｃｍ￣３），外延层厚度达１２０μｍ的ｐ／ｐ￣＋／硅外延片，制成器件的击穿电压可达１０００Ｖ。     

平板式外延炉大尺寸硅外延层的均匀性调控

硅外延层是在硅单晶抛光衬底上采用化学气相沉积方法生长的一层单晶硅薄膜。本实验以150 mm的大尺寸硅抛光片为衬底生长高均匀性外延层，结合傅里叶变换红外线光谱分析（FT-IR）、电阻率测试仪等测试设备对外延层电学参数进行了分析。对平板式外延炉的流场、热场与厚度、电阻率均匀性的相互作用规律进行了研究，最终制备出表面质量良好、片内和片间不均匀性小于1%的外延层。     

三氯氢硅本征电阻率(纯度)的测试方法

三氯氢硅(SiHCl3)作为硅外延片的关键原材料,其纯度直接影响着硅外延层的性能。一般三氯氢硅纯度的测试方法有两种,除采用化学分析方法测试外,通常用生长不掺杂外延层(本征外延层)的方法来确定。即采取测量三氯氢硅生长后的硅外延本征电阻率的方法来衡量其纯度。而影响硅外延本征电阻率的主要因素为系统的自掺杂,增加硅外延的生长时间可以有效抑制系统自掺杂,但无限制的增加生长时间必然导致生产成本的增加。文中通过实验数据,确定了一个合理的硅外延本征生长工艺过程,从而达到了评价三氯氢硅纯度的目的。     

300 mm直径硅外延片均匀性控制方法

随着摩尔定律的逐步实现,大直径硅片的应用规模逐渐扩大,然而,大直径硅外延片的片内均匀性成为了外延的主要问题之一.使用具有五路进气结构的单片外延炉生长300 mm直径硅外延片.相对于传统的三路进气结构,五路进气可以分别对硅片表面的5个区域的气流进行调节,实现单独分区调控,从而提升了外延层厚度均匀性的可调性.实验中,采用两步外延方法,进一步提升了片内电阻率均匀性.通过对工艺参数进行优化,300 mm硅外延片的外延层厚度不均匀性达到0.8％,电阻率不均匀性为1.62％(边缘排除5 mm),成功提升了300 mm直径硅外延片的外延层厚度和电阻率均匀性控制水平.     

C-V测试方法及仪表简介

目前,大量半导体元件和集成电路是在硅外延片上制造的,所以硅外延层电阻率的测量对监控外延层电气特性有着十分重要的意义。从单晶外延到元件工艺直到制成产品要经过十几道工序,每道工序都会引起杂质分布状况的变化,这就使电阻率成为一个十分不稳定的因素。因此,在大量生产中,只有迅速、准确地测     

重掺磷衬底上外延层生长工艺研究

重掺磷衬底上硅外延片是制作集成电路开关电源的肖特基二极管和场控高频电力电子器件的首选产品。重掺磷衬底外延片可以大幅降低压降中半导体部分引起的压降所占的比例。介绍了重掺磷外延片的一种实用生产技术,在高浓度衬底外延后失配现象、杂质外扩抑制方法、减少外延过程中衬底磷杂质的挥发等方面进行了研究。在研究的基础上使用CSD公司的EpiPro5000型外延设备进行工艺试验,采用盖帽层分层生长、变流量赶气和低温度生长等工艺条件控制磷杂质的扩散和挥发,从而减少自掺杂效应,获得良好的电阻率均匀性和陡峭的外延层过渡区。试验结果已成功应用于大规模生产,得到了用户认可。     

6英寸高均匀性P型硅外延片的工艺研究

主要进行了6英寸(152.4 mm)高均匀性P型硅外延片的生产工艺研究。利用PE-2061S型桶式外延炉,在重掺硼的硅衬底上化学气相沉积P/P+型硅外延层。通过流场调节工艺、基座包硅工艺、变流量解吸工艺、两步生长工艺等关键工艺的改进,对非主动掺杂效应进行了有效抑制,利用FTIR(傅里叶变换红外线光谱分析)、C-V(电容-电压测试)、SRP(扩展电阻技术)等测试方法对外延层的电学参数以及过渡区形貌进行了测试,得到结晶质量良好、厚度不均匀性<1%、电阻率不均匀性<1.5%的6英寸P型高均匀性硅外延片,各项参数均可以达到器件的使用要求。     

用于先进CMOS电路的150mm硅外延片外延生长

随着大规模和超大规模集成电路特征尺寸向亚微米、深亚微米发展,下一代集成电路对硅片的表面晶体完整性和电学性能提出了更高的要求.与含有高密度晶体原生缺陷的硅抛光片相比,硅外延片一般能满足这些要求.该文报道了应用于先进集成电路的150mm P/P+CMOS硅外延片研究进展.在PE2061硅外延炉上进行了P/P+硅外延生长.外延片特征参数,如外延层厚度、电阻率均匀性,过渡区宽度及少子产生寿命进行了详细表征.研究表明:150mm P/P+CMOS硅外延片能够满足先进集成电路对材料更高要求,     

用于先进 CMOS电路的 150 mm硅外延片外延生长

随着大规模和超大规模集成电路特征尺寸向亚微米、深亚微米发展,下一代集成电路对硅片的表面晶体完整性和电学性能提出了更高的要求.与含有高密度晶体原生缺陷的硅抛光片相比,硅外延片一般能满足这些要求.该文报道了应用于先进集成电路的150mmP/P+CMOS硅外延片研究进展.在PE2061硅外延炉上进行了P/P+硅外延生长.外延片特征参数,如外延层厚度、电阻率均匀性,过渡区宽度及少子产生寿命进行了详细表征.研究表明:150mmP/P+CMOS硅外延片能够满足先进集成电路对材料更高要求,     

Growth and electrical properties of high-quality Mg-doped P-type A10.2Ga0.8N films

The growth of high-performance Mg-doped p-type AlxGa1-xN(X=0.2)using metal-organic chemical vapor deposition is reported.The influence of growth conditions(growth temperature,magnesium flow,and thermal annealing temperature)on the electrical properties of Mg-doped p-type AlxGa1-xN(X=0.2)has been investigated.Using the optimized conditions,we obtained a minimum p-type resistivity of 0.71 Ωcm for p-type AlGaN with 20% Al fraction.     

Growth of phosphorus-doped p-type ZnO thin films by MOCVD

Phosphorus-doped p-type ZnO thin films are prepared on glass substrates by metalorganic chemical vapor deposition (MOCVD). DEZn, O2, and P2O5 powders are used as reactant and dopant sources. The p-type ZnO films are grown at a temperature between 673 K and 723 K. The best p-type sample has a low resistivity of A strong emission peak at 3.354 eV corresponding to neutral acceptor bound excitons is observed at 77 K in the photoluminescence spectra, which further verifies the p-type characteristics of the films.     

Effects of substrate temperature on electrical and structural properties of copper thin films

This paper addresses the effects of substrate temperature on electrical and structural properties of dc magnetron sputter-deposited copper (Cu) thin films on p-type silicon. Copper films of 80 and 500 nm were deposited from Cu target in argon ambient gas pressure of 3.6 mTorr at different substrate temperatures ranging from room temperature to 250 °C. The electrical and structural properties of the Cu films were investigated by four-point probe and atomic force microscopy. Results from our experiment show that the increase in substrate temperature generally promotes the grain growth of the Cu films of both thicknesses. The RMS roughness as well as the lateral feature size increase with the substrate temperature, which is associated with the increase in the grain size. On the other hand, the resistivity for 80 nm Cu film decreases to less than 5 μΩ-cm at the substrate temperature of 100 °C, and further increase in the substrate temperature has not significantly decreased the film resistivity. For the 500 nm Cu films, the increase in the grain size with the substrate temperature does not conform to the film resistivity for these Cu films, which show no significant change over the substrate temperature range. Possible mechanisms of substrate-temperature-dependent microstructure formation of these Cu films are discussed in this paper, which explain the interrelationship of grain growth and film resistivity with elevated substrate temperature.     

Effect of boron on the resistivity of compensated 4H-SiC

High-resistivity 4H-SiC samples grown by sublimation with a high growth rate are studied. The measurements show resistivity values up to a high of 10⁴ Ωcm. The secondary ion mass spectroscopy (SIMS) results revealed a presence of only common trace impurities such as nitrogen, aluminum, and boron. To understand the compensation mechanism in these samples, capacitance deep-level transient spectroscopy (DLTS) on the p-type epilayers has been performed. By correlation between the growth conditions and SIMS results, we apply a model in which it is proposed that an isolated carbon vacancy donorlike level is a possible candidate responsible for compensation of the shallow acceptors in p-type 4H-SiC. A relation between cathodoluminescence (CL) and DLTS data is taken into account to support the model.     

Current confinement and leakage currents in planarburied-ridge-structure laser diodes on n-substrate

An electrical device model for the planar buried-ridge-structure laser on n-type substrate is discussed. It takes into account the finite p-type contact resistivity, the two-dimensional current spreading, and the electron leakage current by drift and diffusion. Using this model, the influence of the relevant device parameters on the leakage current in InGaAsP/InP devices emitting at 1.3 μm is investigated. It is shown that leakage currents are negligible at room temperature if the contact stripe width does not exceed the sum of the active region width and the p-type confinement layer thickness, but they increase markedly with broader contact stripes and with contact resistivities above 10^-5 Ω-cm². The most important parameter influencing the leakage currents is the doping level of the P-InP confinement layer. With a p-type doping level of 1×10¹⁸ cm^-3, a p-type contact resistivity below 10^-5 Ω-cm² and a contact stripe width of 6 μm, the model calculations predict a maximum operation temperature exceeding 100°C. This agrees fairly well with experimental data proving that the rather simple planar buried-ridge-structure laser performs as well as more sophisticated devices incorporating current-blocking layers     

N掺杂MgZnO薄膜的p型导电稳定性研究

利用磁控溅射技术,以Mg0.06Zn0.94O为陶瓷靶材,制备了N掺杂p型Mg0.1 3Zn0.8 7O薄膜,薄膜的电阻率为42.45Ω·cm,载流子浓度为3.70×1017/cm3,迁移率为0.40cm2·V-1·s-1。研究了该薄膜p型导电性质在室温空气下随时间的变化情况。实验结果表明,薄膜的电阻率逐渐升高,载流子浓度降低,五个月以后,薄膜转变为n型导电,电阻率为85.58Ω·cm,载流子浓度为4.53×1016/cm3,迁移率为1.61cm2·V-1·s-1。真空热退火后重新转变为p型。结果显示,其p型导电类型的转变与在空气中吸附H2O或H2等形成浅施主有关。     

高补偿硅的阻-温特性

采用5·cm的p型单晶硅,通过在高温下扩散金属锰的方法,可以得到高补偿硅。笔者选择没有光照下,室温电阻率为5.84×104·cm的样品,进行测量电阻随温度的变化关系(温度从77 K上升到300 K)。测试结果表明:在没有光照条件下测试时,电阻随温度的变化同普通的半导体;但在受到光照时,却出现极不相同的情况,这种不同,可能来自所掺杂的硅是一种光敏材料及掺入的杂质是一种深能级杂质。     

P-type ZnO thin films prepared by in situ oxidation of DC sputtered Zn3N2:Ga

The feasibility of a new fabrication route for N and Ga codoped p-type ZnO thin films on glass substrates, consisting of DC sputtering deposition of Zn3N2:Ga precursors followed by in situ oxidation in high purity oxygen, has been studied. The effects of oxidation temperature on the structural, optical and electrical properties of the samples were investigated by X-ray diffraction (XRD), scanning electron microscopy (SEM), optical transmittance and Hall effect measurements. The results were compared to a control film without Ga. XRD analyses revealed that the Zn3N2 films entirely transformed into ZnO films after annealing Zn3N2 films in oxygen over 500 ℃ for 2 h. Hall effect measurements confirmed p-type conduction in N and Ga codoped ZnO films with a low resistivity of 19.8 Ω·cm, a high hole concentration of 4.6 × 1018 cm-3 and a Hall mobility of 0.7 cm2/(V·s). These results demonstrate a promising approach to fabricate low resistivity p-type ZnO with high hole concentration.     

InSb分子束外延原位掺杂技术研究

对InSb分子束外延薄膜的本征掺杂、N型掺杂以及P型掺杂进行了研究,其中分别以Be作P 型以及以Si、Te作N 型的掺杂剂。实验采用半绝缘的GaAs衬底作为InSb分子束外延用衬底,通过采用低温生长缓冲层技术降低大失配应力,获得高质量InSb外延膜。实验样品采用霍尔测试以及SIMS测试掺杂浓度和迁移率分析掺杂规律、掺杂元素偏聚和激活规律的影响因素。     

Influence of growth temperature and growth rate of p-GaN layers on the characteristics of green light emitting diodes

We investigated the electrical and structural qualities of Mg-doped p-type GaN layers grown under different growth conditions by metalorganic chemical vapor deposition (MOCVD). Lower 300 K free-hole concentrations and rough surfaces were observed by reducing the growth temperature from 1,040°C to 930°C. The hole concentration, mobility, and electrical resistivity were improved slightly for Mg-doped GaN layers grown at 930°C with a lower growth rate, and also an improved surface morphology was observed. In_0.25Ga_0.75N/GaN multiple-quantum-well light emitting diodes (LEDs) with p-GaN layers grown under different conditions were also studied. It was found from photoluminescence studies that the optical and structural properties of the multiple quantum wells in the LED structure were improved by reducing the growth temperature of the p-layer due to a reduced detrimental thermal annealing effect of the active region during the GaN:Mg p-layer growth. No significant difference in the photoluminescence intensity depending on the growth time of the p-GaN layer was observed. However, it was also found that the electroluminescence (EL) intensity was higher for LEDs having p-GaN layers with a lower growth rate. Further improvement of the p-GaN layer crystalline and structural quality may be required for the optimization of the EL properties of long-wavelength (∼540 nm) green LEDs.