A 1-mil/SUP 2/ single-transistor memory cell in n silicon-gate technology

For a comparison of different single-transistor cell designs and sense/refresh amplifier designs figures of merit are derived from the quasi-static behavior of the memory circuit during sensing. The principles of the different cell designs are discussed. A cell with the most favorable design has been realized with a standard n silicon-gate process sequence and contact photolithography. It uses aluminum word lines of 5 /spl mu/m width and separation, a contact hole with a size of 4 /spl mu/m to 6 /spl mu/m, and diffused bit lines with a width of 4 /spl mu/m. For the 1-mil/SUP 2/ memory cell a sense/refresh amplifier based on the gated flip-flop principle has been realized. The sensitivity of this amplifier, which is determined by the integrated circuit element tolerances is estimated and measured.     

A four-level storage 4-Gb DRAM

A 4-Gb DRAM with multilevel-storage memory cells has been developed. This large memory capacity is achieved by storing data at four levels, each corresponding to two-bit-data storage in a single memory cell. The four-level storage reduces the effective cell size by 50%. A sense amplifier using charge coupling and charge sharing was developed for the four-level sensing and restoring. The sense amplifier uses a hierarchical bit-line scheme and operates in a time-sharing mode, thus reducing the sense amplifier area. A 4-Gb DRAM fabricated using 0.15-μm CMOS technology measures 986 mm². The memory cell is 0.23 μm². Its capacitance of 60 fF is achieved by using a high-dielectric-constant material BST     

A high-speed, small-area, threshold-voltage-mismatch compensationsense amplifier for gigabit-scale DRAM arrays

A high-speed small-area DRAM sense amplifier with a threshold-voltage (V_T) mismatch compensation function is proposed. This sense amplifier features a novel hierarchical data-line architecture with a direct sensing scheme that uses only NMOS transistors in the array, and simple V_T mismatch compensation circuitry using a pair of NMOS switching transistors. The layout area of the sense amplifier is reduced to 70% of that of a conventional CMOS common I/O sense amplifier due to the removal of PMOS transistors from the array. The readout time is improved to 35% of that of a conventional CMOS sense amplifier because of direct sensing and a 1/10 reduction in V_T mismatch. This sense amplifier eliminates the sensitivity degradation and the area overhead increase that are expected in gigabit-scale DRAM arrays     

A 25 ns 64K static RAM

A high-performance 64K/spl times/1-bit CMOS SRAM is described. The RAM has an access time of 25 ns with active power of 350 mW and standby power of 15 mW. The access time has been obtained by using a 1.5 /spl mu/m rule CMOS process, advanced double-level A1 interconnection technology, an equalizer circuit, and a digit line sense amplifier that is the first sense amplifier directly connected to digit lines. The WRITE recovery circuit is effective in improving WRITE characteristics, and a block selecting circuit was used for low power dissipation.     

A high-speed clamped bit-line current-mode sense amplifier

A clamped bit-line current-mode sense amplifier that maintains a low-impedance fixed potential on the bit lines is introduced. Using a general model for active-drive memory cells that include the two-transistor (2T) and three-transistor (3T) dynamic cells and the four-transistor/two-resistor (4T-2R) and six-transistor (6T) static cells, the new sense amplifier is shown to have a response speed that is insensitive to bit-line capacitance. This is achieved by relocating the large bit-line capacitance to a node within the sense amplifier that has only a minimal effect on the speed of the circuit. Bit-line clamping also minimizes inter-bit-line voltage noise coupling     

BiCMOS circuit technology for high-speed DRAMs

A BiCMOS circuit technology featured by a novel bit-line sense amplifier has been developed. The bit-line sense amplifier is composed of a BiCMOS differential amplifier, the impedance-converting means featured by the CMOS current mirror circuit or the clocked CMOS inverter between the bit line and the base node of the BiCMOS differential amplifier, and a conventional CMOS flip-flop. This technology can reduce the access time to half that of a conventional CMOS DRAM access time. Applied to a 1-kb DRAM test chip, a new BiCMOS circuit technology was successfully verified. Furthermore, the sensitivity and area penalty of the new BiCMOS bit-line sense amplifier and future applications to megabit DRAMs are discussed     

An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs

The input referred offset voltage occurring in the full latch V/sub DD/ biased sense amplifier has been analyzed extensively. The process variations in the matched nMOS and pMOS transistors have been accounted by /spl plusmn/2.5% variation in V/sub T/ and /spl plusmn/5% variation in /spl beta/, from typical values. Effect of various design parameters on the sense amplifier offset has been studied and reported. It has been shown that the rise time of the sense amplifier enable signal (SAEN) has a profound effect on the offset voltage. The slower transition of SAEN signal is proposed to result in high speed as well as low-power consumption in SRAM application. An analytical model has been derived for simplified latch to model the effect of rise time of SAEN signal on offset voltage.     

A high-performance very low-voltage current sense amplifier for nonvolatile memories

A high-performance sense amplifier for nonvolatile memories capable of working under a very low-voltage power supply is presented. The topology of the sense amplifier uses a pure current-mode comparison allowing power supplies lower than 1 V to be used and includes two subcircuits which improve slew rate performance. The sense amplifier was implemented in an EEPROM realized with a 0.18-/spl mu/m EEPROM technology. Experimental results showed a read access time of about 30 ns with a power supply of 1.65 V.     

一种新型的SOI灵敏放大器

本文利用"灵巧的体接触(Smart-Body-Contact)"技术设计出一种新型的SOI灵敏放大器.采用Hspice软件对体硅的和新型的交叉耦合灵敏放大器进行模拟和比较,发现新型的交叉耦合灵敏放大器比体硅的交叉耦合灵敏放大器延迟时间缩短30%,最小电压分辨可达0.05V.最后,我们成功地将该电路应用于CMOS/SOI 64Kb SRAM电路,电路存取时间仅40ns.     

具有低失调电压的新型灵敏放大器设计

由于器件尺寸越来越小,器件之间的失配越来越严重,由器件失配引起的失调电压对灵敏放大器性能的影响越来越大。针对此情况,根据灵敏放大器的工作原理,提出了一种具有失调电压自调整的灵敏放大器,通过增加校准支路来平衡灵敏放大器两边的放电速度,从而降低失调电压,减小其对灵敏放大器性能的影响。基于SMIC 65 nm CMOS工艺的后仿真结果显示,在电源电压1.2 V、TT工艺角、室温条件下,相比于传统的灵敏放大器,该新型灵敏放大器的失调电压的标准偏差降低了61.9%,SRAM的读关键路径延迟降低了25%。     

一种高可靠电流灵敏放大器设计

提出了一种带反馈放大器的电流灵敏放大器 ,将用于放大的 NMOS管同时作为位线多路选择器( MU X) ,与一般的电流灵敏放大器相比 ,延迟时间更短 ,而且更适于低电源电压工作。同时分析了阈值电压失配对电流灵敏放大器的影响 ,结果表明 ,失配不仅可能增大灵敏放大器时延 ,甚至造成误放大 ;带反馈放大器的电流灵敏放大器能够有效地抑制阈值失配的影响 ,其性能和可靠性良好。     

一种高速CMOS SRAM读出灵敏放大器的设计

提出了一种ＣＭＯＳ ＳＲＡＭ读出灵敏放大器的新结构。该放大器同传统的ＰＭＯＳ电流镜放大器和ＰＭＯＳ交叉耦合放大器相比，具有速度快、增益大、功耗小等特点，可广泛应用于ＳＲＡＭ的设计中。最后，用ＨＳＰＩＣＥ的仿真结果证明了该设计的正确性及其优点。     

A 50-/spl mu/A standby 1M/spl times/1/256K/spl times/4 CMOS DRAM with high-speed sense amplifier

A 1M word/spl times/1-bit/256K word/spl times/4-bit CMOS DRAM with a test mode is described. The use of an improved sense amplifier for the half-V/SUB CC/ sensing scheme and a novel half-V/SUB CC/ voltage generator have yielded a 56-ns row access time and a 50-/spl mu/A standby current at typical conditions. High /spl alpha/-particle immunity has been achieved by optimizing the impurity profile under the bit line, based on a triple-layer polysilicon n-well CMOS technology. The RAM, measuring 4.4/spl times/12.32 mm/SUP 2/, is fit to standard 300-mil plastic packages.     

ISDN loop extension using a mid span amplifier

The 5·5 km range of the basic rate ISDN loop has been extended by using a negative impedance amplifier and by using a 2 wire/4 wire (2w/4w) amplifier. The negative impedance amplifier extends the range of the loop by 1·0 km, whereas the 2w/4w amplifier extends the range by 1·5 km at the expense of increased complexity. As part of the amplifer design, a resistor/capacitor network has been developed which closely matches the characteristic impedance of telephone cable. Error rate tests have been conducted using various lengths of cable and an operating ISDN line.     

A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme

This paper reports a 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using a novel two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) and sense wordline/bitline (SWL/SBL) tag-sense amplifiers with an eight-transistor (8-T) tag cell in Level 2 (L2) and a 10-T shrunk logic swing (SLS) memory cell. with the ground/floating (G/F) data sense amplifier in Level 1 (L1) for high-speed operation for low-voltage low-power VLSI system applications. Owing to the reduced loading at the SWL in the new 11-T tag cell using the WLOTC scheme, the 10-T SLS memory cell with G/F sense amplifier in L1, and the split comparison of the index signal in the 8-T tag cells with SWL/SBL tag sense amplifiers in L2, this 0.8-V cache memory implemented in a 1.8-V 0.18-/spl mu/m CMOS technology has a measured L1/L2 hit time of 11.6/20.5 ns at the average dissipation of 0.77 mW at 50 MHz.     

A high performance sense amplifier for a 5 V dynamic RAM

Increasing dynamic RAM cell density and the use of a single low-voltage power supply have made it mandatory to store the full power supply voltage in the cell and to be able to detect smaller signals reliably with the initial sense amplifier. The authors present a circuit design approach that restores the cell to a full V/SUB DD/ `1' level, preamplifies the initial charge imbalance before sensing by conventional techniques, and is used in the Fairchild 64K design. Design requirements and a detailed analysis of the amplifier are presented along with simulated results, followed by performance data. The circuit analysis shows how the key design parameters should be chosen and the effects of clock timing variations on the performance of the sense amplifier.     

Novel high speed circuit structures for BiCMOS environment

Novel high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier are presented. A generic 0.8 μm complementary BiCMOS technology has been used in the circuit design. Circuit simulations show superior performance of the novel circuits over conventional designs. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuit and the BiCMOS sense amplifier are improved by 20, 250, and 60%, respectively. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V     

特定领域软件体系结构研究

在分析典型的软件体系结构概念之后，给出了一种新的、通用的软件体系结构定义。目前，大多数软件体系结构的研究主要集中在特定领域软件体系结构，其包括域工程和应用工程。通过分析域工程中域分析的几种不同的概念．提出了域分析和动态域模型的定义，建立了特定领域软件体系结构开发模型，并成功地应用于一复杂的软件系统开发。最后还指出了软件体系结构领域的发展方向。     

A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM

An ultrahigh-speed 1-Mb emitter-coupled logic (ECL)-CMOS SRAM with 550-ps clock-access time, 900-MHz operating frequency, and 12-μm² memory cells has been developed using 0.2-μm BiCMOS technology. Three key techniques for achieving the ultrahigh speed are a BiCMOS word decoder/driver with an nMOS level-shift circuit, a sense amplifier with a voltage-clamp circuit, and a BiCMOS write circuit with a variable-impedance bitline load. The proposed word decoder/driver and sense amplifier can reduce the delay times of the circuits to 54% and 53% of those of conventional circuits. The BiCMOS write circuit can reduce the power dissipation of the circuit by 74% without sacrificing writing speed. These techniques are especially useful for realizing ultrahigh-spaced high-density SRAMs, which will be used as cache and control memories in mainframe computers     

A 9-ns 1-Mbit CMOS SRAM

A 1-Mbit CMOS static RAM (SRAM) with a typical address access time of 9 ns has been developed. A high-speed sense amplifier circuit, consisting of a three-stage PMOS cross-coupled sense amplifier with a CMOS preamplifier, is the key to the fast access time. A parallel-word-access redundancy architecture, which causes no access time penalty, was also incorporated. A polysilicon PMOS load memory cell, which had a large on-current-to-off-current ratio, gave a much lower soft-error rate than a conventional high-resistance polysilicon load cell. The 1-Mbit SRAM, fabricated using a half-micrometer, triple-poly, and double-metal CMOS technology, operated at a single supply voltage of 5 V. An on-chip power supply converter was incorporated in the SRAM to supply a partial internal supply voltage of 4 V to the high-performance half-micrometer MOS transistors.<>