可重构分组密码处理结构的研究与设计

文章分析了主要分组密码算法操作特征以及处理结构的特点,结合可重构处理结构的设计方法,提出一种可重构密码处理结构.设计实现了基于可重构密码处理结构的验证原型.分析结果表明,在验证原型上执行的分组密码算法都可达到较高的性能.     

面向分组密码的可重构异构多核并行处理架构

现有的可重构分组密码实现结构中,专用指令处理器吞吐率不高,阵列结构资源利用率低、算法映射过程复杂.为此,设计了分组密码可重构异构多核并行处理架构RAMCA（Reconfigurable Asymmetrical Multi-Core Architecture）,分析了典型SP（AES-128）、Feistel（SMS4）、L-M（IDEA）及MISTY（KASUMI）结构算法在RAMCA上的映射过程.在65nm CMOS工艺下完成了逻辑综合和功能仿真.实验表明,RAMCA工作频率可达到1GHz,面积约为1.13mm²,消除工艺影响后,对各分组密码算法的运算速度均高于现有专用指令处理器以及Celator、RCPA和BCORE等阵列结构密码处理系统.     

一种基于流处理框架的可重构分簇式分组密码处理结构模型

可重构密码处理结构是一种面向信息安全处理的新型体系结构,但具有吞吐量和利用率不足的问题。该文提出一种基于流处理框架的阵列结构可重构分组密码处理模型(Stream based Reconfigurable Clustered block Cipher Processing Array, S-RCCPA)。针对分组密码算法特点,采用粗粒度可重构功能单元、基于Crossbar的分级互连网络、分布式密钥池存储结构以及静态与动态相结合的重构方式,支持密码处理路径的动态重组,以不同并行度的虚拟流水线执行密码任务。对典型分组密码算法的适配结果表明,在 CMOS工艺下,依据所适配算法结构的不同,规模为41的S-RCCPA模型的典型分组密码处理性能可达其它架构的5.28~47.84倍。     

面向对称密码领域的可重构阵列设计

通过研究密码系统的特点,提出一种面向对称密码领域的可重构阵列结构.该阵列普遍适用于分组密码和流密码系统,灵活性高.通过配置信息的更新,可以快速动态切换加密功能,切换时间小于20 ns.该结构包含几个16×16的比特阵列和8×8的字节阵列,AES算法实现分组密码的加密速率为640 Mb/s～2.56 Gb/s,DES算法为1.6 Gb/s～3.2 Gb/s,SMS4算法为318 Mb/s～1.6 Gb/s,流密码Geffe的加密速率为400 Mb/s.与文献[1]～[3]相比,SMS4算法的性能有接近2倍的提升.     

RSA密码算法的可重构设计与实现

本文对RSA密码算法的实现和可重构性进行了分析,在对模幂模块和模乘模块进行了可重构设计的基础上,提出一种可重构RSA硬件架构,使其能够适配256bit、512bit、1024bit、2048bit四种不同密钥长度的应用。RSA可重构设计在FPGA上进行了实现与测试,结果表明,工作在200MHz时钟时,2048bit密钥长度RSA在最坏情况下数据吞吐量可达46kb／s,能够满足高性能的信息安全系统对RSA算法的加密速度要求。     

PVHArray:一种流水可伸缩的层次化可重构密码逻辑阵列结构

针对密码算法的高效能实现问题,该文提出了一种基于数据流的粗粒度可重构密码逻辑阵列结构PVHArray.通过研究密码算法运算及控制结构特征,基于可重构阵列结构设计方法,提出了以流水可伸缩的粗粒度可重构运算单元、层次化互连网络和面向周期级的分布式控制网络为主体的粗粒度可重构密码逻辑阵列结构及其参数化模型.为了提升可重构密码逻辑阵列的算法实现效能,该文结合密码算法映射结果,确定模型参数,构建了规模为4×4的高效能PVHArray结构.基于55nm CMOS工艺进行流片验证,芯片面积为12.25mm²,同时,针对该阵列芯片进行密码算法映射.实验结果表明,该文提出高效能PVHArray结构能够有效支持分组、序列以及杂凑密码算法的映射,在密文分组链接（CBC）模式下,相较于可重构密码逻辑阵列REMUS_LPP结构,其单位面积性能提升了约12.9%,单位功耗性能提升了约13.9%.     

可重构分组密码指令集处理器自动映射方法研究

计算资源与寄存器资源分配是可重构处理器自动并行映射的重要问题,该文针对可重构分组密码指令集处理器的资源分配问题,建立算子调度参数模型和处理器资源参数模型,研究了分组密码并行调度与资源消耗之间的约束关系;在此基础上提出基于贪婪思维、列表调度和线性扫描的自动映射算法,实现了分组密码在可重构分组密码指令集处理器上的自动映射。通过可用资源变化实验验证算法并行映射的有效性,并对AES-128算法的映射效果做了横向对比验证算法的先进性,所提自动映射算法对分组密码在可重构处理中的并行计算研究有一定的指导意义。     

可重构分组密码指令集处理器自动映射方法研究

计算资源与寄存器资源分配是可重构处理器自动并行映射的重要问题,该文针对可重构分组密码指令集处理器的资源分配问题,建立算子调度参数模型和处理器资源参数模型,研究了分组密码并行调度与资源消耗之间的约束关系;在此基础上提出基于贪婪思维、列表调度和线性扫描的自动映射算法,实现了分组密码在可重构分组密码指令集处理器上的自动映射.通过可用资源变化实验验证算法并行映射的有效性,并对AES-128算法的映射效果做了横向对比验证算法的先进性,所提自动映射算法对分组密码在可重构处理中的并行计算研究有一定的指导意义.     

TD-SCDMA移动终端加密的FPGA设计

介绍了一种密钥长度为128bit,分组长度为64bit,内核为KASUMI的f9算法的数据完整性算法,并利用FPGA设计了该算法的硬件模块构成,最后进行了该算法在硬件设计上可行性的评估。由于该数据完整性算法提供了可靠的安全性和可达2Mbit/s的加密速度,使其在移动通信中有着广阔的应用前景。     

TD-SCDMA移动终端加密的FPGA

介绍了一种密钥长度为128 bit,分组长度为64 bit,内核为KASUMI的f9算法的数据完整性算法,并利用FPGA设计了该算法的硬件模块构成,最后进行了该算法在硬件设计上可行性的评估.由于该数据完整性算法提供了可靠的安全性和可达2 Mbit/s的加密速度,使其在移动通信中有着广阔的应用前景.     

ADSL网络体系结构

ADSL是DSL的一种非对称版本，是目前一种重要的宽带接入方式，ADSL能够向终端用户提供8Mbit/s的下行传输速率和1Mbit/s的上行传输速率，比传统的28．8kbit/s模拟调制解调器快将近200倍。文中讨论了一组能够支持基于PPP／ATM／ADSL接入网体系结构的核心网体系结构，分析了几种不同组网方式的特征与协议栈模型。     

An 11 mm$^{2}$ , 70 mW Fully Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12$ mu$ m CMOS

With the rapid evolution of wireless standards and increasing demand for multi-standard products, the need for flexible RF and baseband solutions is growing. Flexibility is required to be able to adapt to unstable standards and requirements without costly hardware re-spins, and also to enable hardware reuse between products and between multiple wireless standards in the same device, ultimately saving both development cost and silicon area. In this paper a fully programmable baseband processor suitable for standards such as DVB-T/H and mobile WiMAX is presented. The processor is based on the SIMT architecture which utilizes a unique type of vector instructions to provide processing parallelism while minimizing the control complexity of the processor. The architecture has been demonstrated in a prototype chip which was proven in a complete DVB-T/H system demonstrator. The chip occupies 11 mm² in a 0.12 mum CMOS process. It includes 1.5 Mbit of single port SRAM and 200 k logic gates. The measured power consumption for the highest DVB-T/H data rate (31.67 MBit/s) is 70 mW at 70 MHz. This outperforms both area and power figures of previously presented non-programmable DVB-T/H solutions.     

Easily Adaptable On‐Chip Debug Architecture for Multicore Processors

Nowadays, the multicore processor is watched with interest by people all over the world. As the design technology of system on chip has developed, observing and controlling the processor core's internal state has not been easy. Therefore, multicore processor debugging is very difficult and time‐consuming. Thus, we need a reliable and efficient debugger to find the bugs. In this paper, we propose an on‐chip debug architecture for multicore processors that is easily adaptable and flexible. It is based on the JTAG standard and supports monitoring mode debugging, which is different from run‐stop mode debugging. Compared with the debug architecture that supports the run‐stop mode debugging, the proposed architecture is easily applied to a debugger and has the advantage of having a desirable gate count and execution cycle. To verify the on‐chip debug architecture, it is applied to the debugger of the prototype multicore processor and is tested by interconnecting it with a software debugger based on GDB and configured for the target processor.     

New nibbled-page architecture for high-density DRAMs

A nibbled-page architecture which can be used to access all column addresses on the selected row address randomly in units of 8 bits at the 100 Mbit/s data rate is discussed. To realize such high-speed architecture, three key circuit techniques have been developed. An on-chip interleaved circuit has been used for the high-speed serial READ and WRITE operations. Column address prefetch and WE signal prefetch techniques have been introduced to eliminate idle time between 8 bit units. The nibbled-page architecture has been successfully implemented in an experimental 16 Mb DRAM, and 100 Mb/s operation has been achieved. The DRAM with nibbled-page mode is very effective in simplifying the design of high-speed data transfer systems     

The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture

This paper describes the design and implementation of the massively parallel processor based on the matrix architecture which is suitable for portable multimedia applications. The proposed architecture in this paper achieves the high performance of 40 GOPS in the case of consecutive fixed-point 16-bit additions at 200MHz clock frequency and the small power dissipation of 250mW. In addition, 1Mbit SRAM for data registers and 2048 2-bit-grained processing elements connected by a flexible switching network are integrated in the small area of 3.1 mm ² in 90nm CMOS low standby technology. These design techniques and architectures described in this paper are attractive for realizing area-efficient, energy-efficient, and high-performance multimedia processors     

Scalable shared-buffering ATM switch with a versatile searchablequeue

The shared-buffering architecture is promising to make a large-scale ATM switch with small buffer size. However, there are two important problems, namely, memory-access speed and complex-control implementation. Advanced 0.5 μm CMOS technology now makes it possible to integrate a huge amount of memory, and enables us to apply more sophisticated architecture than ever before. We propose the funnel-structured expandable architecture with shared multibuffering and the advanced searchable-address queueing scheme for these two problems. The funnel structure gives a flexible capability to build various sizes of ATM switches which are proportional to the number of LSI chips. The searchable-address queue, in which all the addresses of the stored cells for different output ports are queued in a single-FIFO hardware and the earliest address is found by the search function provided inside the queue, can reduce the total memory capacity drastically, and enables the address queue to be contained inside the LSI chip. This technique also has a great advantage for implementing the multicast and multilevel priority-control functions. A 622 Mbit/s 32×8 ATM switch LSI chip set, which consists of a BX-LSI and a CX-LSI, is developed using 0.5 μm pure CMOS technology. By using four chip sets, a 622 Mbit/s 32×32 switch can be installed on one board     

Bidirectional fibre-optical transmission using a multiple-quantum-well (MQW) modulator/detector

We demonstrate a simple architecture for bidirectional optical fibre transmission which uses an MQW device as both modulator and photodetector. We achieved transmission of 50 Mbit/s and 600 Mbit/s in both directions over one 3.34 km-long single-mode fibre at 860 nm wavelength. Coherent Rayleigh interference was found to be a limiting factor in single-source bidirectional systems.     

Optimization and Implementation of a Viterbi Decoder Under Flexibility Constraints

This paper discusses the impact of flexibility when designing a Viterbi decoder for both convolutional and TCM codes. Different trade-offs have to be considered in choosing the right architecture for the processing blocks and the resulting hardware penalty is evaluated. We study the impact of symbol quantization that degrades performance and affects the wordlength of the rate-flexible trellis datapath. A radix-2-based architecture for this datapath relaxes the hardware requirements on the branch metric and survivor path blocks substantially. The cost of flexibility in terms of cell area and power consumption is explored by an investigation of synthesized designs that provide different transmission rates. Two designs are fabricated in a digital 0.13- $mu{hbox {m}}$ CMOS process. Based on post-layout simulations, a symbol baud rate of 168 Mbaud/s is achieved in TCM mode, equivalent to a maximum throughput of 840 Mbit/s using a 64-QAM constellation.      

An analog on-line-learning K-means processor employing fully parallel self-converging circuitry

A hardware-efficient on-line-learnable processor was developed for the K-means clustering of highly dimensional vectors. Based on our proposed sample updating strategy, an incremental number of sample vectors can be clustered by a constant set of VLSI circuits. In order to speed up the learning process, we developed an analog fully parallel self-converging circuitry to implement the K-means algorithm. Upon receiving a sample vector on-line, the K-means learning autonomously proceeds and converges within a single system clock cycle (0.1 μs at 10 MHz). Furthermore, the chip-area and inner connection explosion problem was solved by using the proposed architecture. A proof-of-concept processor was designed and verified by the HSPICE and Nanosim simulations. The images from an actual database were used as learning samples in the form of 64 dimensional feature vectors. From the simulation results, all the samples were clustered into correct categories with a randomly ill initialization. In addition, the number of sample vectors can be freely increased.     

一种新型的基于IEEE 802.3ab的SFP

文章讨论了一种新型的基于IEEE802.3ab的SFP(即1000Base TSFP),从电路设计、PCB设计和电磁兼容性设计3个方面对1000Base TSFP的设计进行了系统地描述,并遵循以上设计原则研制出了高性能的1000Base TSFP,其不但可以将1000Mbit/s的信号在标准5类线上传输180m,并且具有10/100/1000Mbit/s自适应能力.