一种全CMOS工艺吉比特以太网串并-并串转换电路

本文介绍了一种单片集成的吉比特以太网串并－并串转换电路。在芯片中，模拟锁相环产生1．25GHz高速时钟（当芯片用于光纤网络，时钟速率就为1．06GHz)，同时一个10到1多路选择器完成并行数据到串行的转换。在接收端，差分输入信号依次经过均衡电路、双端－单端转换电路转换成数字信号。同时，数据和时钟提取电路提取出时钟，并将数据重新同步。最后，串并转换电路完成串行－并行转换和字节同步。实验芯片采用0．35μmSPTM CMOS工艺，芯片面积为1．92mm^2，在最高输入输出数据波特率条件下的功耗为900mW。     

一种采用半速结构的CMOS串行数据收发器的设计

设计了一种单片集成的CMOS串行数据收发器．该收发器用于线上速率为1.25Gb/s的千兆以太网中,全集成了发送和接收的功能,主要由时钟发生器、时钟数据恢复电路、并串／串并转换电路、线驱动器和均衡器组成．为了降低系统设计难度和电路功耗,收发器采用了半速率时钟结构．电路采用1.8V 0.18μm 1P6M CMOS数字工艺,芯片面积为2.0mm×1.9mm．经Cadence Spectre仿真验证以及流片测试,电路工作正常,功能良好．     

一种高速低抖动四相位时钟电路的设计

超高速A/D转换器对精准的时钟电路提出严格要求,时钟抖动是影响其精度的重要因素。文章在分析时钟抖动对A/D转换器的影响后,介绍了一种适用于GHz的低抖动四相位时钟电路。电路采用时钟恢复电路、四相位分布网络和相位校正电路,得到占空比稳定、相位误差小的四相位时钟。采用0. 18μm CMOS工艺实现,电路仿真表明,四相位输出时钟抖动102 fs,占空比调整范围30%～70%,功耗277 mW@1. 8 V。     

一种采用半速结构的CMOS串行数据收发器的设计

设计了一种单片集成的CMOS串行数据收发器.该收发器用于线上速率为1.25Gb/s的千兆以太网中,全集成了发送和接收的功能,主要由时钟发生器、时钟数据恢复电路、并串/串并转换电路、线驱动器和均衡器组成.为了降低系统设计难度和电路功耗,收发器采用了半速率时钟结构.电路采用1.8V 0.18μm 1P6M CMOS数字工艺,芯片面积为2.0mm×1.9mm.经Cadence Spectre仿真验证以及流片测试,电路工作正常,功能良好.     

0.18μm CMOS工艺3.125Gb/s发送器的设计

介绍了一种采用深亚微米CMOS工艺实现单片集成发送器的设计.它适用于IEEE 802.3ae多通道10Gbps以太网接口(Ethernet).发送器主要由时钟发生器、多路选择器、占空比调整电路和片内阻抗匹配的线驱动器组成.为了提高传输速率发送器采用多相时钟结构,并且针对该种结构对发送器的功耗进行了系统优化.文中设计的电路采用0.18μm工艺仿真,总体功耗为95mW,线驱动器差分输出幅度为1600mV,发送器的系统抖动为50ps.     

一种用于FPGA的270MHz到1.5GHz可重构多功能锁相环时钟发生器

本文设计实现了一种用于FPGA芯片的可重构多功能的锁相环时钟发生器。该时钟发生器具有可配置的时钟发生和延时补偿两种模式,分别实现时钟倍频和相位对准的功能。输出时钟信号还具有可编程的相移和占空比调节等高级时钟变化功能。为了提高相位对准和相移的精度,本文设计了一种具有新的快速起振技术的压控振荡器。本文还提出了一种延时分割方法以提高用于实现相移和占空比调节功能的后端分频器的速度。整个时钟发生器使用0.13μm标准CMOS工艺设计制作。测试结果表明,能够实现270MHz到1.5GHz的宽调节范围,当锁定在1GHz时,整个电路功耗为18mW,rms抖动小于9ps,锁定时间为2μs左右。     

2.5Gb/s 0.18μm CMOS时钟数据恢复电路

采用TSMC公司标准的0．18μm CMOS工艺，设计并实现了一个全集成的2．5Gb／s时钟数据恢复电路．时钟恢复由一个锁相环实现．通过使用一个动态的鉴频鉴相器，优化了相位噪声性能．恢复出2．5GHz时钟信号的均方抖动为2．4ps，单边带相位噪声在10kHz频偏处为-111dBc／Hz．恢复出2．5Gb／s数据的均方抖动为3．3ps．芯片的功耗仅为120mW．     

基于半速率锁相环的5Gb/s CMOS单片时钟恢复电路

利用TSMC的O．18μm CMOS工艺,设计实现了单片集成的5 Gb/s锁相环型时钟恢复电路。该电路采用由半速率鉴相器、四相位环形电流控制振荡器、电荷泵以及环路滤波器组成的半速率锁相环结构。测试表明：在输入速率为5 Gb/s、长度为211-1伪随机序列的情况下,恢复出时钟的均方根抖动为4．7 ps。在偏离中心频率6MHz频率处的单边带相位噪声为-112．3 dBe/Hz。芯片面积仅为0．6mm×O．6 mm,采用1.8 V电源供电,功耗低于90 mW。     

2.5 Gb/s PS/PI型半速率时钟数据恢复电路设计

采用标准0.18 μm CMOS工艺,设计了一种相位选择(PS)/相位插值(PI)型半速率时钟数据恢复电路。该电路主要由半速率Bang-Bang鉴相器、改进型PS/PI电路、数字滤波器和数字控制器等模块构成。改进型PS/PI电路通过两个相位选择器和两个相位插值器实现正交时钟的产生,相较于传统结构,减少了两个相位选择器,降低了复杂度和功耗。数字滤波器和数字控制器通过Verilog代码自动综合生成,降低了设计难度。Cadence仿真结果表明,输入2.5 Gb/s伪随机数据时,电路在1.8 μs时锁定,锁定后恢复出的时钟和数据峰峰值抖动分别为17.71 ps和17.89 ps,可以满足短距离I/O接口通信的需求。     

基于130 nm CMOS工艺的5 Gbit/s 10:1并串转换芯片

介绍了一种基于GSMC 130 nm CMOS工艺的高速率低功耗10:1并串转换芯片。在核心并串转换部分,该芯片使用了多相结构和树型结构相结合的方式,在输入半速率时钟的条件下,实现了10路500 Mbit/s并行数据到1路5 Gbit/s串行数据的转换。全芯片完整后仿真结果显示,在工作电压(1.2±10%)V、温度-55~100℃、全工艺角条件下,该芯片均可正确完成10:1并串转换逻辑功能,并输出清晰干净的5 Gbit/s眼图。在典型条件下,芯片整体功耗为25.2 mW,输出电压摆幅可达到260 mV。     

A 2.5-GHz four-phase clock generator with scalable no-feedback-looparchitecture

An accurate yet simple multiphase clock generator has been developed by using a delay compensation technique based on phase interpolation that supplies a multiphase clock signal without increasing local circuit area. This generator is applied to the 2.5-GHz four-phase clock distribution of a 5-Gb/s×8-channel receiver fabricated with 0.13-μm CMOS technology. The four-phase generator in the receiver consumes 30 mW and occupies only 0.009 mm². It requires only 1.5 clock cycles to produce accurate phase differences and can operate from 1.5 to 2.8 GHz, with a range of phase error within ±5     

A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time

A portable clock generator, which solves the duty ratio and jitter problems of the input clock, has been developed. In the proposed clock generator, the complementary delay line generates a series of multiphase clocks. The 0-to-1 transition detector finds the 2 pi phase delayed position among the multiphase clocks produced by the complementary delay line, and then, the select signal generator chooses the proper path to generate the delayed output clock. As a result, the proposed open-loop and full-digital architecture achieves a fast lock time of two clock cycles. Also, it is a simple, robust and portable IP and consumes only 17 mW at an input clock frequency of 1.6 GHz. In addition, a complementary delay line is implemented to achieve high phase resolution over a wide frequency range. The proposed clock generator is implemented in a 0.18-mum CMOS process and, occupies an active area of 170 mum times 120 mum. Also, it operates at various input frequencies ranging from 800 MHz to 1.6 GHz.     

A 34 Gb/s Distributed 2:1 MUX and CMU Using 0.18$muhbox m$CMOS

A 34 Gb/s 2:1 serializer consisting of a CMOS MUX and CMU using a 0.18$muhbox m$SiGe BiCMOS process is presented. The serializer is based on distributed amplifier topology realized using spiral inductors. The circuit also includes an on-chip 2-channel$2^7-1$PRBS generator. The 34 Gb/s serial output has single-ended voltage swing of 380 mV with rise/fall time of 13 ps, and measured ISI is less than 5 ps p-p.     

Digital multiphase clock/pattern generator

In telecommunications systems, the commonly used method to generate clocks is based on phase-locked loop or delay-locked loop related frequency synthesis. In this paper, we address a method of digital multiphase clock/pattern generation (MPCG) to generate a system clock or pulse pattern vector when a multiphase clock is available. The advantages of the multiphase clock method are: (a) the design method is digital; (b) the working frequency range is very wide; and (c) the sensitivity to noise is less than analog methods. Different approaches to implement the basic blocks in MPCG are described. A design example implemented in BiCMOS uses eight clock phases at 622 MHz obtained by dividing a 5-GHz clock to generate a clock at 622 MHz×32/53=376 MHz. By such a method, we can generate a pulse pattern vector as well. The maximum time resolution is equal to half of the phase difference. A low power solution is achieved without loss of circuit speed     

A Single-Stage Direct Interpolation Multiphase Clock Generator with Phase Error Averaging

Multiphase clock generators are conventionally implemented with a feedback loop. This paper presents a non-feedback approach to generate multiphase clocks. A simple architecture of direct phase interpolation is proposed, in which the edges of two phase-adjacent signals are used to control the discharge (or charge) of two capacitors respectively, producing time-overlapped slopes. A resistor chain connected to the two capacitors is used to interpolate a number of new slopes in between. The generated phase resolution depends on the number and ratios of resistors thus is not limited by an inverter delay. Based on this architecture, a multiphase clock generator is developed. In addition, a phase error averaging circuit is used to correct interphase errors. The multiphase clock generator has been fabricated in a 0.35 m, 3.3 V CMOS process. The measured performance shows it can produce 8 evenly spaced clock signals in one input clock period and work in an input clock range from 300 MHz to 600 MHz. The measured maximum jitter performance is rms 6.8 ps and peak-to-peak 47 ps, respectively.     

A 50-Gbit/s 450-mW Full-Rate 4:1 Multiplexer With Multiphase Clock Architecture in 0.13- μm InP HEMT Technology

A full-rate multiplexer (MUX) with a multiphase clock architecture for over 40 Gbit/s optical communication systems is presented. The 4:1 MUX is comprised of a re-timer based on a D-type flip-flop (DFF) and a clock tree system that uses EXOR-type delay buffers to match its skews well to those of the data. The supply voltage is reduced to -1.5 V by analyzing the voltage allocation. Fabricated in a 0.13-mum InP HEMT technology, a DFF test circuit achieved 75-Gbit/s operation and exhibited performance sufficient to re-time 50-Gbit/s serialized data. The 4:1 MUX measurement results demonstrate successful 50-Gbit/s operation at room temperature, and 40-Gbit/s operation, which has 10^-11 error free for 2³¹ - 1 pseudorandom bit stream (PRBS) data, up to an ambient temperature of 90 degrees or down to - 1.24 V of supply voltage. The circuit consumes 450 mW at a - 1.5-V supply and exhibits an output jitter of 283 fs rms at 50-Gbit/s operation. We also propose a multiphase clock generator for a MUX that has a serialization of more than four channels     

An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation

A distributed DLL (DDLL) with low jitter and high phase accuracy is proposed for the multiphase clock generator. The high-speed multiphase clock generator produces a five-phase clock at a frequency range of 8 to 10 GHz. Additionally, the discrete-time model for the distributed DLL and the analysis about stability and noise are proposed in this work. The measured rms jitter is 293.3 fs and the maximum phase mismatch is 1.4 ps. The proposed architecture can suppress the jitter by 58%. The distributed DLL occupies 0.03 ${hbox{mm}}^{2}$ active area in a 90-nm CMOS technology and consumes 15 mA from a 1.0-V supply.      

A wide-range all digital DLL for multiphase clock generation

This paper presents a wide-range all digital delay-locked loop (DLL) for multiphase clock generation. Using the phase compensation circuit (PCC), the large phase difference is compensated in the initial step. Thus, the proposed solution can overcome the false-lock problem in conventional designs, and keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. Furthermore, the proposed all digital multiphase clock generator has wide ranges and is not related to specific process. Thus, it can reduce the design time and design complexity in many different applications. The DLL is implemented in a 0.13 μm CMOS process. The experimental results show that the proposal has a wide frequency range. The peak-to-peak jitter is less than 7.7 ps over the operating frequency range of 200 MHz-1 GHz and the power consumption is 4.8 mW at 1 GHz. The maximum lock time is 20 clock cycles.     

Half-Rate Duobinary Transmitter Architecture for Chip-to-Chip Interconnect Applications

For a high speed duobinary transmitter clock frequency defines the transmission limit. A conventional duobinary transmitter needs a clock frequency equal to the data rate. In this work we propose a duobinary transmitter that uses a clock frequency half of the output data rate and hence achieves double the transmission rate for a given clock frequency as compared to a conventional duobinary transmitter. In the proposed transmitter the duobinary precoder is integrated into the last stage of a tree structured serializer to combine two NRZ data streams at half the transmission data rate. Two modes for the precoder have been incorporated into the design. The first mode is applicable for data transmission over copper whereas the second mode is suitable for wavelength division multiplexed optical transmission. A DLL based clock multiplier unit is employed to produce the high frequency clock with 50% duty cycle needed for the precoding operation. It incorporates a clock generation logic with integrated duty cycle control. A charge pump with dynamic current matching and a high resolution PFD are employed to reduce static phase error in locking and hence achieves improved jitter performance. A new delay cell along with automatic mode selection is proposed. To cover a wide range of data rate, the DLL is designed for a wide locking range and maintains almost 50% duty cycle. The design is implemented in 1.8-V, 0.18 μm Digital CMOS technology with an f _T of 27 GHz. Simulations shows that, the duobinary transmitter circuit works up-to 10 Gb/s and consumes 60 mW of power.     

A 0.6-2.5-GBaud CMOS tracked 3 × oversampling transceiverwith dead-zone phase detection for robust clock/data recovery

For generation of the multiphase clocks for a serializer, a wide-range multiphase delay-locked loop (DLL) is used in the transmitter to avoid the detrimental characteristics of a phase-locked loop (PLL), such as jitter peaking and accumulated phase error. A tracked 3 × oversampling technique with dead-zone phase detection is incorporated in the receiver for robust clock/data recovery in the presence of excessive jitter and intersymbol interference (ISI). Due to the dead-zone phase detection, phase adjustment is performed only on the tail portions of the transition histogram in the received data eye, thereby exhibiting wide pumping-current range, large jitter tolerance, and small phase error. A voltage-controlled oscillator (VCO), based on a folded starved inverter, shows about 50% less jitter than one with replica bias. The transceiver, implemented in 0.25-μm CMOS technology, operates at 2.5 GBaud over a 10-m 150-Ω STP cable and at 1.25 GBaud over a 25-m cable with a bit error rate (BER) of less than 10^-13